From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37F48C433F5 for ; Tue, 30 Nov 2021 13:05:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ml6dPDRG2g8/xmSW3O7qiTOh1n3YgW2hi711mtGgwdQ=; b=DO2yKOncaDjQfL yKzane2S1YUa+Rz2opCH//d7bw4EfVHiDVulSm72b0LqgLUFNPdFrYjEhtqAtwG8P+rXBSn6+EX2X RmhmjjfYdF35Xl8CVbVpWB7dvB1nKlkBI6szwY+/CB/sSmi5kHfU+HyODAiuYeBeKP2cfk3bhtyNW I8jD7Bs2vFbtkpDIcXTCsGLP07yi9rWjSMbbnA35M6hZmF7ONhHdE69klh84kElQ7JbDFpeY4aj3h pgJG513XaEDFgQKj8C4P0en/8mbaCpZy2jHs/Ua614IqKyh91Qv+zf1hXkagIo8QXtck3y2/VXnI3 90NZwOwvrE+G+LQE03aw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ms2nR-005EIG-OX; Tue, 30 Nov 2021 13:03:45 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ms2jV-005CTQ-LN for linux-arm-kernel@lists.infradead.org; Tue, 30 Nov 2021 12:59:43 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 13D3FCE177F; Tue, 30 Nov 2021 12:59:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2C1C4C53FCF; Tue, 30 Nov 2021 12:59:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638277178; bh=IIQyUHMzdn4I8ZMbssYX1n3RjsHZ+XIcSaEYqEhW8Bw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kjQ2HnBhb4K6bKM6Kd4kIej/h6e16TdgDws37LtBbjhASX6UH4PbUgVZpPU0w4/oC A7Vz5uzyeDxT6NSYcCeSwRoORIcNaSi3NC7kBgo53FxFOxVOUvzc9Sim5i3TLR3CHW D5FB6zhhcUMS1TplwUvIgwX92nuti+TiXUIalwKD7XwJxI+UBdkApcwIY97Y8iY9Zt dta18QxLpt4azO8znMBJXvvDwIiY5j78lmW2MKCD2/p/0L1+gW+2bxRfqvDS+ZbWlP JrPQ+Jcq4FEyq8YiibhGXNUeTEP9Kz+SM2hQzOVexrTOGecC46AKuBRF6XcFrK37jj GWgmQT5yTJzVA== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk Cc: Ard Biesheuvel , Nicolas Pitre , Arnd Bergmann , Kees Cook , Keith Packard , Linus Walleij , Nick Desaulniers , Tony Lindgren Subject: [PATCH v2 11/12] ARM: smp: defer TPIDRURO update for SMP v6 configurations too Date: Tue, 30 Nov 2021 13:59:00 +0100 Message-Id: <20211130125901.3054-12-ardb@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211130125901.3054-1-ardb@kernel.org> References: <20211130125901.3054-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3144; h=from:subject; bh=IIQyUHMzdn4I8ZMbssYX1n3RjsHZ+XIcSaEYqEhW8Bw=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBhpiATmOuET8dZMt5RXsFAxSj8TAEnsaICjO7tsQog GSzI5lqJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCYaYgEwAKCRDDTyI5ktmPJDHjC/ 4lrDicjnxrzLlmOenPJPA2bP1z1y75N2vXEeCNcQpYNRScngG9+CvhOQGMC06M8MPGtBvmZWDe0i0u hN93G39CsHRRpnQDLsEnxZICQoAR9D6J3Y8C93DlrEhM0gau9LPOdwUJPtbk6Knn2oecdvEdjw89pA mpMWqYX+9lC5iDQrB9QTYzIq78lalg+dwDU5kNXGwRMTpPV8fIRAJPAe6P3neK5adEZM5TC7Qb+ZyK WQKHmQJeSBqoyp+rzcIgP7BXMKPz7QckoonPnA2vecjlqiM3JGG/NZtIvKUDlC7NC1rDGJyQWNkZ/j 42fmUqYZ8SmKsi1hKb6GaYRPJDTDb5zuvZx0+qLbrP5PVPKFgnUcosuo/GJiEqPs43Xb4SBkeJ38VI Uf5DNaohVYPI/PtltD+Bj5hD7256XvZkeMPwsSl17Duw/Hgxf1kO70zkkX+ah/z29t/TKC/GTcA7QR yPI7+/SFi5gZXXt3dC9jBnzzNmM6GRLDebindLH31GeHk= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211130_045942_091704_96428671 X-CRM114-Status: GOOD ( 18.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Defer TPIDURO updates for user space until exit also for CPU_V6+SMP configurations so that we can decide at runtime whether to use it to carry the current pointer, provided that we are running on a CPU that actually implements this register. This is needed for THREAD_INFO_IN_TASK support for UP systems, which requires that all SMP capable systems use the TPIDRURO based access to 'current' as the only remaining alternative will be a global variable which only works on UP. Acked-by: Linus Walleij Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/tls.h | 13 +++++++------ arch/arm/kernel/entry-header.S | 11 ++++++++++- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index c3296499176c..d712c170c095 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -18,13 +18,14 @@ .endm .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2 - ldr \tmp1, =elf_hwcap - ldr \tmp1, [\tmp1, #0] + ldr_va \tmp1, elf_hwcap mov \tmp2, #0xffff0fff tst \tmp1, #HWCAP_TLS @ hardware TLS available? streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register +#ifndef CONFIG_SMP mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register +#endif mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it .endm @@ -43,7 +44,7 @@ #elif defined(CONFIG_CPU_V6) #define tls_emu 0 #define has_tls_reg (elf_hwcap & HWCAP_TLS) -#define defer_tls_reg_update 0 +#define defer_tls_reg_update IS_ENABLED(CONFIG_SMP) #define switch_tls switch_tls_v6 #elif defined(CONFIG_CPU_32v6K) #define tls_emu 0 @@ -81,11 +82,11 @@ static inline void set_tls(unsigned long val) */ barrier(); - if (!tls_emu && !defer_tls_reg_update) { - if (has_tls_reg) { + if (!tls_emu) { + if (has_tls_reg && !defer_tls_reg_update) { asm("mcr p15, 0, %0, c13, c0, 3" : : "r" (val)); - } else { + } else if (!has_tls_reg) { #ifdef CONFIG_KUSER_HELPERS /* * User space must never try to access this diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 268f7f4c5c05..cb82ff5adec1 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -292,12 +292,21 @@ .macro restore_user_regs, fast = 0, offset = 0 -#if defined(CONFIG_CPU_32v6K) && !defined(CONFIG_CPU_V6) +#if defined(CONFIG_CPU_32v6K) || defined(CONFIG_SMP) +#if defined(CONFIG_CPU_V6) && defined(CONFIG_SMP) +ALT_SMP(b .L1_\@ ) +ALT_UP( nop ) + ldr_va r1, elf_hwcap + tst r1, #HWCAP_TLS @ hardware TLS available? + beq .L2_\@ +.L1_\@: +#endif @ The TLS register update is deferred until return to user space so we @ can use it for other things while running in the kernel get_thread_info r1 ldr r1, [r1, #TI_TP_VALUE] mcr p15, 0, r1, c13, c0, 3 @ set TLS register +.L2_\@: #endif uaccess_enable r1, isb=0 -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel