All of lore.kernel.org
 help / color / mirror / Atom feed
From: Vinod Koul <vkoul@kernel.org>
To: unlisted-recipients:; (no To-header on input)
Cc: linux-arm-msm@vger.kernel.org,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	Vinod Koul <vkoul@kernel.org>
Subject: [PATCH 14/15] arm64: dts: qcom: sm8450: add cpufreq support
Date: Wed,  1 Dec 2021 12:59:14 +0530	[thread overview]
Message-ID: <20211201072915.3969178-15-vkoul@kernel.org> (raw)
In-Reply-To: <20211201072915.3969178-1-vkoul@kernel.org>

From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>

The change adds a description of a SM8450 cpufreq-epss controller and
references to it from CPU nodes.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 8f0819df8039..29c5abcfa074 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
 			next-level-cache = <&L2_0>;
 			power-domains = <&CPU_PD0>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_0: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -62,6 +63,7 @@ CPU1: cpu@100 {
 			next-level-cache = <&L2_100>;
 			power-domains = <&CPU_PD1>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_100: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -76,6 +78,7 @@ CPU2: cpu@200 {
 			next-level-cache = <&L2_200>;
 			power-domains = <&CPU_PD2>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_200: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -90,6 +93,7 @@ CPU3: cpu@300 {
 			next-level-cache = <&L2_300>;
 			power-domains = <&CPU_PD3>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_300: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -104,6 +108,7 @@ CPU4: cpu@400 {
 			next-level-cache = <&L2_400>;
 			power-domains = <&CPU_PD4>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_400: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -118,6 +123,7 @@ CPU5: cpu@500 {
 			next-level-cache = <&L2_500>;
 			power-domains = <&CPU_PD5>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_500: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -133,6 +139,7 @@ CPU6: cpu@600 {
 			next-level-cache = <&L2_600>;
 			power-domains = <&CPU_PD6>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_600: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -147,6 +154,7 @@ CPU7: cpu@700 {
 			next-level-cache = <&L2_700>;
 			power-domains = <&CPU_PD7>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 2>;
 			L2_700: l2-cache {
 			      compatible = "cache";
 			      next-level-cache = <&L3_0>;
@@ -170,7 +178,9 @@ core2 {
 				core3 {
 					cpu = <&CPU3>;
 				};
+			};
 
+			cluster1 {
 				core4 {
 					cpu = <&CPU4>;
 				};
@@ -182,7 +192,9 @@ core5 {
 				core6 {
 					cpu = <&CPU6>;
 				};
+			};
 
+			cluster2 {
 				core7 {
 					cpu = <&CPU7>;
 				};
@@ -943,6 +955,21 @@ rpmhpd_opp_turbo_l1: opp10 {
 
 		};
 
+		cpufreq_hw: cpufreq@17d91000 {
+			compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
+			reg = <0 0x17d91000 0 0x1000>,
+			      <0 0x17d92000 0 0x1000>,
+			      <0 0x17d93000 0 0x1000>;
+			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
+			#freq-domain-cells = <1>;
+		};
+
 		gem_noc: interconnect@19100000 {
 			reg = <0 0x19100000 0 0xbb800>;
 			compatible = "qcom,sm8450-gem-noc";
-- 
2.31.1


  parent reply	other threads:[~2021-12-01  7:30 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-01  7:29 [PATCH 00/15] arm64: dts: qcom: Add support for SM8450 SoC and QRD board Vinod Koul
2021-12-01  7:29 ` [PATCH 01/15] arm64: dts: qcom: Add base SM8450 DTSI Vinod Koul
2021-12-01 15:03   ` Konrad Dybcio
2021-12-06  5:39     ` Vinod Koul
2021-12-07 14:35       ` Bjorn Andersson
2021-12-07 14:53   ` Bjorn Andersson
2021-12-01  7:29 ` [PATCH 02/15] arm64: dts: qcom: Add base SM8450 QRD DTS Vinod Koul
2021-12-01 15:05   ` Konrad Dybcio
2021-12-01  7:29 ` [PATCH 03/15] arm64: dts: qcom: sm8450: Add tlmm nodes Vinod Koul
2021-12-07 14:37   ` Bjorn Andersson
2021-12-01  7:29 ` [PATCH 04/15] arm64: dts: qcom: sm8450-qrd: Add reserved gpio range for QRD Vinod Koul
2021-12-01 15:07   ` Konrad Dybcio
2021-12-06  5:53     ` Vinod Koul
2021-12-07 14:56       ` Bjorn Andersson
2021-12-01  7:29 ` [PATCH 05/15] arm64: dts: qcom: sm8450: Add reserved memory nodes Vinod Koul
2021-12-01 15:11   ` Konrad Dybcio
2021-12-06  5:42     ` Vinod Koul
2021-12-01  7:29 ` [PATCH 06/15] arm64: dts: qcom: sm8450: add smmu nodes Vinod Koul
2021-12-01 15:13   ` Konrad Dybcio
2021-12-01  7:29 ` [PATCH 07/15] arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes Vinod Koul
2021-12-01 15:14   ` Konrad Dybcio
2021-12-01  7:29 ` [PATCH 08/15] arm64: dts: qcom: sm8450: add ufs nodes Vinod Koul
2021-12-01 15:16   ` Konrad Dybcio
2021-12-01  7:29 ` [PATCH 09/15] arm64: dts: qcom: sm8450-qrd: enable " Vinod Koul
2021-12-01 15:18   ` Konrad Dybcio
2021-12-06  5:58     ` Vinod Koul
2021-12-07 15:01       ` Bjorn Andersson
2021-12-01  7:29 ` [PATCH 10/15] arm64: dts: qcom: sm8450: add interconnect nodes Vinod Koul
2021-12-01 15:20   ` Konrad Dybcio
2021-12-06  6:12     ` Vinod Koul
2021-12-01  7:29 ` [PATCH 11/15] arm64: dts: qcom: sm8450: add spmi node Vinod Koul
2021-12-01 15:22   ` Konrad Dybcio
2021-12-01  7:29 ` [PATCH 12/15] arm64: dts: qcom: sm8450-qrd: include pmic files Vinod Koul
2021-12-01 15:23   ` Konrad Dybcio
2021-12-07 15:05     ` Bjorn Andersson
2021-12-07 15:51       ` Vinod Koul
2021-12-01  7:29 ` [PATCH 13/15] arm64: dts: qcom: sm8450: Add rpmhpd node Vinod Koul
2021-12-01 15:24   ` Konrad Dybcio
2021-12-01  7:29 ` Vinod Koul [this message]
2021-12-01 15:28   ` [PATCH 14/15] arm64: dts: qcom: sm8450: add cpufreq support Konrad Dybcio
2021-12-09  7:11     ` Vinod Koul
2021-12-01  7:29 ` [PATCH 15/15] arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes Vinod Koul
2021-12-01 15:30   ` Konrad Dybcio
2021-12-09  7:13     ` Vinod Koul

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211201072915.3969178-15-vkoul@kernel.org \
    --to=vkoul@kernel.org \
    --cc=bjorn.andersson@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=vladimir.zapolskiy@linaro.org \
    --subject='Re: [PATCH 14/15] arm64: dts: qcom: sm8450: add cpufreq support' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.