From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1003C433F5 for ; Fri, 3 Dec 2021 11:07:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380277AbhLCLLP (ORCPT ); Fri, 3 Dec 2021 06:11:15 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44168 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380216AbhLCLLK (ORCPT ); Fri, 3 Dec 2021 06:11:10 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1B3B7aYA125397; Fri, 3 Dec 2021 05:07:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1638529656; bh=o2/3Sb6TDRH3rx8TWLvMcNFdX2xi3fcTYplGH9IWqHA=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=GNan/2Tu/yS8xqEBljoRMaFvSzhkOt5UfYKHw2PtOcbnIN887LoX0bCgb8GViyxTX kueOSL5EJNO7DACmjTiR4OdP+uSSnRVTT7gJriKEaMgg23MXSfHZtkCG129h1nSDUb eYejbVRm/gFI0pn51ggwO3eu6kRWHbLT39weFcE4= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1B3B7aKK052803 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 3 Dec 2021 05:07:36 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 3 Dec 2021 05:07:36 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 3 Dec 2021 05:07:36 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1B3B7ZQm019521; Fri, 3 Dec 2021 05:07:36 -0600 Date: Fri, 3 Dec 2021 16:37:34 +0530 From: Pratyush Yadav To: Nishanth Menon CC: Rob Herring , Tero Kristo , Vignesh Raghavendra , , , , , Peng Fan Subject: Re: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets Message-ID: <20211203110734.23e2t356s45ux5mu@ti.com> References: <20211113043638.4358-1-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20211113043638.4358-1-nm@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/11/21 10:36PM, Nishanth Menon wrote: > A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of ^^^ Same as previous patch, do you mean A72? J7200 does not have an A53 core and this cache node is for A72 cores anyway. With this fixed, Reviewed-by: Pratyush Yadav > 64 bytes and 16-way set-associative cache structure. > > 1MB of L2 / 64 (line length) = 16384 ways > 16384 ways / 16 = 1024 sets > > Fix the l2 cache-sets. > > [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system > [2] https://www.ti.com/lit/pdf/spruiu1 > > Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") > Reported-by: Peng Fan > Signed-off-by: Nishanth Menon > --- > arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > index 958587d3a33d..64fef4e67d76 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > @@ -86,7 +86,7 @@ L2_0: l2-cache0 { > cache-level = <2>; > cache-size = <0x100000>; > cache-line-size = <64>; > - cache-sets = <2048>; > + cache-sets = <1024>; > next-level-cache = <&msmc_l3>; > }; > -- Regards, Pratyush Yadav Texas Instruments Inc. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27CA2C433F5 for ; Fri, 3 Dec 2021 11:09:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zTv+6i58LvGhR66t2bhxx/WeSqeFVpFYjk3j0Kq7ORk=; b=BtpqAV7i9H/x8H 4CZ1YJ3MPfLX0oi7eICyqwfXmgx/VeR4JwyLrDaRPc0qvDFrY765FoCvOhn8P2gTzBTqYaVLSTT2i qOq55qq6n7u2jQKzW29BoREgeeHOiJA/8sR299Pun/Pcw+Mbt/bYnj7bw7BfouqNiH17EzU+OpvkS qCo28kmcQELEe9NJCtU5kRXXu2UrIioncqmPKywF0LYop+BY97pKNRImqJ1Mod7eNbDYo4VAT4/w4 HRqgQ26XyjWBharUlSlncCPwk+hRYcS3RMV9MIxHmzxQuKVoB2Mbvez+IMVcSgTfA77O9U7aKRCPM wDNgDnE55QI2ZFrXku4g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mt6Pm-00FIwX-S4; Fri, 03 Dec 2021 11:07:43 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mt6Pj-00FIw0-NX for linux-arm-kernel@lists.infradead.org; Fri, 03 Dec 2021 11:07:41 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1B3B7aYA125397; Fri, 3 Dec 2021 05:07:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1638529656; bh=o2/3Sb6TDRH3rx8TWLvMcNFdX2xi3fcTYplGH9IWqHA=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=GNan/2Tu/yS8xqEBljoRMaFvSzhkOt5UfYKHw2PtOcbnIN887LoX0bCgb8GViyxTX kueOSL5EJNO7DACmjTiR4OdP+uSSnRVTT7gJriKEaMgg23MXSfHZtkCG129h1nSDUb eYejbVRm/gFI0pn51ggwO3eu6kRWHbLT39weFcE4= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1B3B7aKK052803 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 3 Dec 2021 05:07:36 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 3 Dec 2021 05:07:36 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 3 Dec 2021 05:07:36 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1B3B7ZQm019521; Fri, 3 Dec 2021 05:07:36 -0600 Date: Fri, 3 Dec 2021 16:37:34 +0530 From: Pratyush Yadav To: Nishanth Menon CC: Rob Herring , Tero Kristo , Vignesh Raghavendra , , , , , Peng Fan Subject: Re: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets Message-ID: <20211203110734.23e2t356s45ux5mu@ti.com> References: <20211113043638.4358-1-nm@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211113043638.4358-1-nm@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211203_030739_879353_1C6C78AC X-CRM114-Status: GOOD ( 16.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/11/21 10:36PM, Nishanth Menon wrote: > A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of ^^^ Same as previous patch, do you mean A72? J7200 does not have an A53 core and this cache node is for A72 cores anyway. With this fixed, Reviewed-by: Pratyush Yadav > 64 bytes and 16-way set-associative cache structure. > > 1MB of L2 / 64 (line length) = 16384 ways > 16384 ways / 16 = 1024 sets > > Fix the l2 cache-sets. > > [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system > [2] https://www.ti.com/lit/pdf/spruiu1 > > Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") > Reported-by: Peng Fan > Signed-off-by: Nishanth Menon > --- > arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > index 958587d3a33d..64fef4e67d76 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > @@ -86,7 +86,7 @@ L2_0: l2-cache0 { > cache-level = <2>; > cache-size = <0x100000>; > cache-line-size = <64>; > - cache-sets = <2048>; > + cache-sets = <1024>; > next-level-cache = <&msmc_l3>; > }; > -- Regards, Pratyush Yadav Texas Instruments Inc. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel