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From: Ben Widawsky <ben.widawsky@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org,
	Alison Schofield <alison.schofield@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 7/9] cxl/acpi: Map component registers for Root Ports
Date: Fri, 3 Dec 2021 21:13:24 -0800	[thread overview]
Message-ID: <20211204051324.3ifts5otddabj4mh@intel.com> (raw)
In-Reply-To: <CAPcyv4jUebWTEOaULzDDqXf50QDEBZ3F4RAZVCO_kGXHjbo_xw@mail.gmail.com>

On 21-12-03 20:37:26, Dan Williams wrote:
> On Mon, Nov 29, 2021 at 1:47 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
> >
> > This implements the TODO in cxl_acpi for mapping component registers.
> > cxl_acpi becomes the second consumer of CXL register block enumeration
> > (cxl_pci being the first). Moving the functionality to cxl_core allows
> > both of these drivers to use the functionality. Equally importantly it
> > allows cxl_core to use the functionality in the future.
> >
> > CXL 2.0 root ports are similar to CXL 2.0 Downstream Ports with the main
> > distinction being they're a part of the CXL 2.0 host bridge. While
> > mapping their component registers is not immediately useful for the CXL
> > drivers, the movement of register block enumeration into core is a vital
> > step towards HDM decoder programming.
> >
> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> > ---
> > Changes since v1:
> > - Add comment on why component register enumeration for root ports is
> >   optional (Jonathan)
> > - Fix kdoc for cxl_find_regblock (Jonathan)
> > - Convert cxl_reg_block macro to static inline (Dan)
> > - Rename cxl_reg_block cxl_reg_block to cxl_regmap_to_base (Dan)
> > - Make cxl_regmap_to_base return CXL_RESOURCE_NONE on failure (Dan)
> 
> Hmm, it's not doing that...
> 

Oops. I'll fix that. I suppose the best check is to check @base? I don't see any
other obvious way.

  reply	other threads:[~2021-12-04  5:13 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-29 21:47 [PATCH 0/9] CXL port prep work Ben Widawsky
2021-11-29 21:47 ` [PATCH 1/9] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-11-29 21:47 ` [PATCH 2/9] cxl: Flesh out register names Ben Widawsky
2021-11-29 21:47 ` [PATCH 3/9] cxl/pci: Extract device status check Ben Widawsky
2021-12-02 17:09   ` Dan Williams
2021-12-02 17:24     ` Ben Widawsky
2021-12-02 17:32       ` Dan Williams
2021-12-04  1:18         ` Ben Widawsky
2021-12-04  1:37           ` Dan Williams
2021-11-29 21:47 ` [PATCH 4/9] cxl/pci: Implement Interface Ready Timeout Ben Widawsky
2021-11-30 13:19   ` Jonathan Cameron
2021-12-02  4:45     ` [PATCH v2 " Ben Widawsky
2021-12-02  9:54       ` Jonathan Cameron
2021-11-29 21:47 ` [PATCH 5/9] cxl/pci: Don't poll doorbell for mailbox access Ben Widawsky
2021-11-29 21:47 ` [PATCH 6/9] cxl/pci: Add new DVSEC definitions Ben Widawsky
2021-11-29 21:47 ` [PATCH 7/9] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-11-30 13:22   ` Jonathan Cameron
2021-12-04  4:37   ` Dan Williams
2021-12-04  5:13     ` Ben Widawsky [this message]
2021-12-15 15:04   ` Jonathan Cameron
2021-11-29 21:47 ` [PATCH 8/9] cxl: Introduce module_cxl_driver Ben Widawsky
2021-11-30 13:23   ` Jonathan Cameron
2021-11-29 21:47 ` [PATCH 9/9] cxl/core: Convert decoder range to resource Ben Widawsky

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