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[155.4.221.129]) by smtp.gmail.com with ESMTPSA id d23sm723918lfm.107.2021.12.04.02.55.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Dec 2021 02:55:39 -0800 (PST) From: Rikard Falkeborn To: Zhenyu Wang , Zhi Wang , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Cc: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rikard Falkeborn Subject: [PATCH 5/9] drm/i915/gvt: Constify gvt_mmio_block Date: Sat, 4 Dec 2021 11:55:23 +0100 Message-Id: <20211204105527.15741-6-rikard.falkeborn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211204105527.15741-1-rikard.falkeborn@gmail.com> References: <20211204105527.15741-1-rikard.falkeborn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These are never modified, so make them const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn --- drivers/gpu/drm/i915/gvt/gvt.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 0c0615602343..0ebffc327528 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -272,7 +272,7 @@ struct intel_gvt_mmio { /* Value of command write of this reg needs to be patched */ #define F_CMD_WRITE_PATCH (1 << 8) - struct gvt_mmio_block *mmio_block; + const struct gvt_mmio_block *mmio_block; unsigned int num_mmio_block; DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index cde0a477fb49..5e85a77da257 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -3627,11 +3627,11 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt) return 0; } -static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, - unsigned int offset) +static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, + unsigned int offset) { unsigned long device = intel_gvt_get_device_type(gvt); - struct gvt_mmio_block *block = gvt->mmio.mmio_block; + const struct gvt_mmio_block *block = gvt->mmio.mmio_block; int num = gvt->mmio.num_mmio_block; int i; @@ -3670,7 +3670,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) * accessible (should have no F_CMD_ACCESS flag). * otherwise, need to update cmd_reg_handler in cmd_parser.c */ -static struct gvt_mmio_block mmio_blocks[] = { +static const struct gvt_mmio_block mmio_blocks[] = { {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL}, {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, @@ -3753,7 +3753,7 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), void *data) { - struct gvt_mmio_block *block = gvt->mmio.mmio_block; + const struct gvt_mmio_block *block = gvt->mmio.mmio_block; struct intel_gvt_mmio_info *e; int i, j, ret; @@ -3871,7 +3871,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, struct drm_i915_private *i915 = vgpu->gvt->gt->i915; struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt_mmio_info *mmio_info; - struct gvt_mmio_block *mmio_block; + const struct gvt_mmio_block *mmio_block; gvt_mmio_func func; int ret; -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A126EC433F5 for ; Mon, 6 Dec 2021 10:21:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 063EC73E0A; Mon, 6 Dec 2021 10:19:43 +0000 (UTC) Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B71B6E8A0; Sat, 4 Dec 2021 10:55:41 +0000 (UTC) Received: by mail-lj1-x229.google.com with SMTP id e11so11079700ljo.13; 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[155.4.221.129]) by smtp.gmail.com with ESMTPSA id d23sm723918lfm.107.2021.12.04.02.55.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Dec 2021 02:55:39 -0800 (PST) From: Rikard Falkeborn To: Zhenyu Wang , Zhi Wang , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH 5/9] drm/i915/gvt: Constify gvt_mmio_block Date: Sat, 4 Dec 2021 11:55:23 +0100 Message-Id: <20211204105527.15741-6-rikard.falkeborn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211204105527.15741-1-rikard.falkeborn@gmail.com> References: <20211204105527.15741-1-rikard.falkeborn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rikard Falkeborn , intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" These are never modified, so make them const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn --- drivers/gpu/drm/i915/gvt/gvt.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 0c0615602343..0ebffc327528 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -272,7 +272,7 @@ struct intel_gvt_mmio { /* Value of command write of this reg needs to be patched */ #define F_CMD_WRITE_PATCH (1 << 8) - struct gvt_mmio_block *mmio_block; + const struct gvt_mmio_block *mmio_block; unsigned int num_mmio_block; DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index cde0a477fb49..5e85a77da257 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -3627,11 +3627,11 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt) return 0; } -static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, - unsigned int offset) +static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, + unsigned int offset) { unsigned long device = intel_gvt_get_device_type(gvt); - struct gvt_mmio_block *block = gvt->mmio.mmio_block; + const struct gvt_mmio_block *block = gvt->mmio.mmio_block; int num = gvt->mmio.num_mmio_block; int i; @@ -3670,7 +3670,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) * accessible (should have no F_CMD_ACCESS flag). * otherwise, need to update cmd_reg_handler in cmd_parser.c */ -static struct gvt_mmio_block mmio_blocks[] = { +static const struct gvt_mmio_block mmio_blocks[] = { {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL}, {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, @@ -3753,7 +3753,7 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), void *data) { - struct gvt_mmio_block *block = gvt->mmio.mmio_block; + const struct gvt_mmio_block *block = gvt->mmio.mmio_block; struct intel_gvt_mmio_info *e; int i, j, ret; @@ -3871,7 +3871,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, struct drm_i915_private *i915 = vgpu->gvt->gt->i915; struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt_mmio_info *mmio_info; - struct gvt_mmio_block *mmio_block; + const struct gvt_mmio_block *mmio_block; gvt_mmio_func func; int ret; -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73545C433EF for ; Mon, 6 Dec 2021 13:23:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 292CB7AA84; Mon, 6 Dec 2021 13:23:26 +0000 (UTC) Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B71B6E8A0; Sat, 4 Dec 2021 10:55:41 +0000 (UTC) Received: by mail-lj1-x229.google.com with SMTP id e11so11079700ljo.13; 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[155.4.221.129]) by smtp.gmail.com with ESMTPSA id d23sm723918lfm.107.2021.12.04.02.55.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Dec 2021 02:55:39 -0800 (PST) From: Rikard Falkeborn To: Zhenyu Wang , Zhi Wang , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Date: Sat, 4 Dec 2021 11:55:23 +0100 Message-Id: <20211204105527.15741-6-rikard.falkeborn@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211204105527.15741-1-rikard.falkeborn@gmail.com> References: <20211204105527.15741-1-rikard.falkeborn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Mon, 06 Dec 2021 13:23:20 +0000 Subject: [Intel-gfx] [PATCH 5/9] drm/i915/gvt: Constify gvt_mmio_block X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rikard Falkeborn , intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" These are never modified, so make them const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn --- drivers/gpu/drm/i915/gvt/gvt.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 0c0615602343..0ebffc327528 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -272,7 +272,7 @@ struct intel_gvt_mmio { /* Value of command write of this reg needs to be patched */ #define F_CMD_WRITE_PATCH (1 << 8) - struct gvt_mmio_block *mmio_block; + const struct gvt_mmio_block *mmio_block; unsigned int num_mmio_block; DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index cde0a477fb49..5e85a77da257 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -3627,11 +3627,11 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt) return 0; } -static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, - unsigned int offset) +static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, + unsigned int offset) { unsigned long device = intel_gvt_get_device_type(gvt); - struct gvt_mmio_block *block = gvt->mmio.mmio_block; + const struct gvt_mmio_block *block = gvt->mmio.mmio_block; int num = gvt->mmio.num_mmio_block; int i; @@ -3670,7 +3670,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) * accessible (should have no F_CMD_ACCESS flag). * otherwise, need to update cmd_reg_handler in cmd_parser.c */ -static struct gvt_mmio_block mmio_blocks[] = { +static const struct gvt_mmio_block mmio_blocks[] = { {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL}, {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, @@ -3753,7 +3753,7 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), void *data) { - struct gvt_mmio_block *block = gvt->mmio.mmio_block; + const struct gvt_mmio_block *block = gvt->mmio.mmio_block; struct intel_gvt_mmio_info *e; int i, j, ret; @@ -3871,7 +3871,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, struct drm_i915_private *i915 = vgpu->gvt->gt->i915; struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt_mmio_info *mmio_info; - struct gvt_mmio_block *mmio_block; + const struct gvt_mmio_block *mmio_block; gvt_mmio_func func; int ret; -- 2.34.1