From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45B2CC433EF for ; Mon, 6 Dec 2021 15:36:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=j2sMM771PnB/az+S8jK8lmHzS7Qyf2/hUEFYozysSS4=; b=LmJ3Uecxz4bvKx +4s4D+LggFz9dVjyIhTmLvaNP8RpT/dibSUqM2LzAqb+HIbB5mtnTpJp367rR5FOdkfOPIg8ZThJO x10JJEl54eMNcL/hlcSdQyIgXySnIf2dSOoL1d+QThPUuLACjFOOat9cIxUD8ZuyXE0b911UPBLfn zAWUv88bEM+H1Du3k/yBz7UJ6B1f66KHzm4gonZSh7UGWNVIVpOw/qJ4YGczNfFXzd6yUJHw+yr6s kcbqjYzd+PFVUuprgDKs8FtDdyMu7RWr1o9dp5P6lNQpU3Hjvf5MgKE25TtuhcdWl/4lYSxAkQOC9 Qp5DehqYvVKKV5Gd7e+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muG09-004Y6W-RG; Mon, 06 Dec 2021 15:34:02 +0000 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1muFyy-004XUg-0u for linux-arm-kernel@lists.infradead.org; Mon, 06 Dec 2021 15:32:51 +0000 Received: by mail-ed1-x532.google.com with SMTP id r11so44291704edd.9 for ; Mon, 06 Dec 2021 07:32:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OkDSlzNyccGJm3fGJWjOCT3PITcK8ErGOmoqjaGOv4E=; b=bOfR2lQZ+1DUDnfucrRZE39u3pjOGh4lYttVdY5SAscmopfpo5gQLQ7jnrEEbsuDBE IQShoQmRcvf1WOoPA0LDktYSv12E3jFyuCKV3RYuXvrsAnv4dOymh/nHjVfT2cGAHdQF upZ/CD86kocKjJ8ORSJOEv9GYG0gxuaXbDSG9VJL8R8KmnShHo7vf9w5DLiw6BFySiRq of12NY6tQCOGxdU6P0aQauIrFWJtAZRE6Ay2iTv6sGjez9oxZJoyPfsv+KvhGnlHo9+m SpjhbQ2nol0HkxSpWA14eKLyIOhUJZRPqm5gXdVo8uKuGnILHGKdGnb3mYVLlHSA+vLz y9Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OkDSlzNyccGJm3fGJWjOCT3PITcK8ErGOmoqjaGOv4E=; b=u9qxEKjxjW6P5I2rZh1xZSqEJaLW7vkG55mCKZnm2Ttt8crEuwvc/Y6mD+rXbf7OoD NZjUMRExQ2e2h6QsZfsv0eNW3QtBkTVDM5+JlrFDXwzpP9+1uadXtB/lKVDmbv4mVvmp W7SxDX9V5Sdf9sH7LcGfrxoUmTpaCVvJd0Q5Bc8d4xVtXvgPUyKXWSJ91KyWV2Sd4W/p erZdeKqKfV3orKzacWDdnPV7WpF2JCtKVYtJWGFEyk/qwAzZSOrU1evYlycA12cSwRx1 XYAhwb1NXkmEUo0io3/JxaS2zl8AbCtbKbqQsb4so2qM0UWEHHOqPzu7zbxCpdW3Op7H 1weg== X-Gm-Message-State: AOAM532di2GTkY6WeQREdm2t+QAwKSbXVTIyX+lSB3GWrubkSin8sNN1 gKUjaq0xv7/41KI5z3u2SqQ= X-Google-Smtp-Source: ABdhPJyLVMVVJvM4K20sd/2CGbRiBK763KKH1GUkq2okc6AfBkPHUlZobyR0rCpByu0SQLHzuJAChA== X-Received: by 2002:a50:a6ca:: with SMTP id f10mr55015973edc.81.1638804764255; Mon, 06 Dec 2021 07:32:44 -0800 (PST) Received: from localhost.localdomain ([2a02:ab88:368f:2080:eab:126a:947d:3008]) by smtp.googlemail.com with ESMTPSA id d19sm7364688edt.34.2021.12.06.07.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 07:32:43 -0800 (PST) From: David Virag To: Cc: Sam Protsenko , David Virag , Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 6/7] clk: samsung: Add initial Exynos7885 clock driver Date: Mon, 6 Dec 2021 16:31:20 +0100 Message-Id: <20211206153124.427102-7-virag.david003@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211206153124.427102-1-virag.david003@gmail.com> References: <20211206153124.427102-1-virag.david003@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211206_073248_119688_D2CC11E6 X-CRM114-Status: GOOD ( 19.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org VGhpcyBpcyBhbiBpbml0aWFsIGltcGxlbWVudGF0aW9uIGFkZGluZyBiYXNpYyBjbG9ja3MsIHN1 Y2ggYXMgVUFSVCwKVVNJLCBJMkMsIFdEVCwgZWN0LiBhbmQgdGhlaXIgcGFyZW50IGNsb2Nrcy4g SXQgaXMgaGVhdmlseSBiYXNlZCBvbiB0aGUKRXh5bm9zODUwIGNsb2NrIGRyaXZlciBhdCAnZHJp dmVycy9jbGsvc2Ftc3VuZy9jbGstZXh5bm9zODUwLmMnIHdoaWNoCndhcyBtYWRlIGJ5IFNhbSBQ cm90c2Vua28sIHRodXMgdGhlIGNvcHlyaWdodCBhbmQgYXV0aG9yIGxpbmVzIHdlcmUKa2VwdC4K CkJ1cyBjbG9ja3MgYXJlIGVuYWJsZWQgYnkgZGVmYXVsdCBhcyB3ZWxsIHRvIGF2b2lkIGhhbmdz IHdoaWxlIHRyeWluZyB0bwphY2Nlc3MgQ01VIHJlZ2lzdGVycy4KCk9ubHkgdGhlIHBhcnRzIG9m IENNVV9UT1AgbmVlZGVkIGZvciBDTVVfQ09SRSBhbmQgQ01VX1BFUkksIGEgYml0IG9mCkNNVV9D T1JFLCBhbmQgbW9zdCBvZiBDTVVfUEVSSSBpcyBpbXBsZW1lbnRlZCBhcyBvZiBub3cuCgpTaWdu ZWQtb2ZmLWJ5OiBEYXZpZCBWaXJhZyA8dmlyYWcuZGF2aWQwMDNAZ21haWwuY29tPgotLS0KQ2hh bmdlcyBpbiB2MjoKICAtIFVzZSBzaGFyZWQgY29kZSBiZXR3ZWVuIEV4eW5vczg1MCBhbmQgNzg4 NSBjbG9jayBkcml2ZXJzCiAgLSBBcyB0aGUgY29kZSB0aGF0IHdhcyBmcm9tIHRoZSBFeHlub3M4 NTAgY2xvY2sgZHJpdmVyIHdhcyBtb3ZlZCB0bwogICAgY2xrLWV4eW5vcy1hcm02NC5jIGFuZCB3 aGF0IHJlbWFpbnMgaXMgbW9zdGx5IFNvQyBzcGVjaWZpYyBkYXRhLAogICAgbW92ZSB0aGUgTGlu YXJvIGNvcHlyaWdodCBhbmQgU2FtIFByb3RzZW5rbyBhdXRob3IgbGluZXMgdGhlcmUuCgpDaGFu Z2VzIGluIHYzOgogIC0gTm90aGluZwoKQ2hhbmdlcyBpbiB2NDoKICAtIEZpeGVkIG1pc3Npbmcg aGVhZGVycwoKIGRyaXZlcnMvY2xrL3NhbXN1bmcvTWFrZWZpbGUgICAgICAgICB8ICAgMSArCiBk cml2ZXJzL2Nsay9zYW1zdW5nL2Nsay1leHlub3M3ODg1LmMgfCA1OTcgKysrKysrKysrKysrKysr KysrKysrKysrKysrCiAyIGZpbGVzIGNoYW5nZWQsIDU5OCBpbnNlcnRpb25zKCspCiBjcmVhdGUg bW9kZSAxMDA2NDQgZHJpdmVycy9jbGsvc2Ftc3VuZy9jbGstZXh5bm9zNzg4NS5jCgpkaWZmIC0t Z2l0IGEvZHJpdmVycy9jbGsvc2Ftc3VuZy9NYWtlZmlsZSBiL2RyaXZlcnMvY2xrL3NhbXN1bmcv TWFrZWZpbGUKaW5kZXggOTAxZTYzMzNjNWYwLi4wZGY3NDkxNmE4OTUgMTAwNjQ0Ci0tLSBhL2Ry aXZlcnMvY2xrL3NhbXN1bmcvTWFrZWZpbGUKKysrIGIvZHJpdmVycy9jbGsvc2Ftc3VuZy9NYWtl ZmlsZQpAQCAtMTgsNiArMTgsNyBAQCBvYmotJChDT05GSUdfRVhZTk9TX0FVRFNTX0NMS19DT04p ICs9IGNsay1leHlub3MtYXVkc3Mubwogb2JqLSQoQ09ORklHX0VYWU5PU19DTEtPVVQpCSs9IGNs ay1leHlub3MtY2xrb3V0Lm8KIG9iai0kKENPTkZJR19FWFlOT1NfQVJNNjRfQ09NTU9OX0NMSykJ Kz0gY2xrLWV4eW5vcy1hcm02NC5vCiBvYmotJChDT05GSUdfRVhZTk9TX0FSTTY0X0NPTU1PTl9D TEspCSs9IGNsay1leHlub3M3Lm8KK29iai0kKENPTkZJR19FWFlOT1NfQVJNNjRfQ09NTU9OX0NM SykJKz0gY2xrLWV4eW5vczc4ODUubwogb2JqLSQoQ09ORklHX0VYWU5PU19BUk02NF9DT01NT05f Q0xLKQkrPSBjbGstZXh5bm9zODUwLm8KIG9iai0kKENPTkZJR19TM0MyNDEwX0NPTU1PTl9DTEsp Kz0gY2xrLXMzYzI0MTAubwogb2JqLSQoQ09ORklHX1MzQzI0MTBfQ09NTU9OX0RDTEspKz0gY2xr LXMzYzI0MTAtZGNsay5vCmRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsay9zYW1zdW5nL2Nsay1leHlu b3M3ODg1LmMgYi9kcml2ZXJzL2Nsay9zYW1zdW5nL2Nsay1leHlub3M3ODg1LmMKbmV3IGZpbGUg bW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwLi5hN2IxMDYzMDI3MDYKLS0tIC9kZXYvbnVs bAorKysgYi9kcml2ZXJzL2Nsay9zYW1zdW5nL2Nsay1leHlub3M3ODg1LmMKQEAgLTAsMCArMSw1 OTcgQEAKKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wLW9ubHkKKy8qCisgKiBD b3B5cmlnaHQgKEMpIDIwMjEgRMOhdmlkIFZpcsOhZyA8dmlyYWcuZGF2aWQwMDNAZ21haWwuY29t PgorICogQXV0aG9yOiBEw6F2aWQgVmlyw6FnIDx2aXJhZy5kYXZpZDAwM0BnbWFpbC5jb20+Cisg KgorICogQ29tbW9uIENsb2NrIEZyYW1ld29yayBzdXBwb3J0IGZvciBFeHlub3M3ODg1IFNvQy4K KyAqLworCisjaW5jbHVkZSA8bGludXgvY2xrLmg+CisjaW5jbHVkZSA8bGludXgvY2xrLXByb3Zp ZGVyLmg+CisjaW5jbHVkZSA8bGludXgvb2YuaD4KKyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2Uu aD4KKyNpbmNsdWRlIDxsaW51eC9wbGF0Zm9ybV9kZXZpY2UuaD4KKworI2luY2x1ZGUgPGR0LWJp bmRpbmdzL2Nsb2NrL2V4eW5vczc4ODUuaD4KKworI2luY2x1ZGUgImNsay5oIgorI2luY2x1ZGUg ImNsay1leHlub3MtYXJtNjQuaCIKKworLyogLS0tLSBDTVVfVE9QIC0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0gKi8KKworLyogUmVn aXN0ZXIgT2Zmc2V0IGRlZmluaXRpb25zIGZvciBDTVVfVE9QICgweDEyMDYwMDAwKSAqLworI2Rl ZmluZSBQTExfTE9DS1RJTUVfUExMX1NIQVJFRDAJCTB4MDAwMAorI2RlZmluZSBQTExfTE9DS1RJ TUVfUExMX1NIQVJFRDEJCTB4MDAwNAorI2RlZmluZSBQTExfQ09OMF9QTExfU0hBUkVEMAkJCTB4 MDEwMAorI2RlZmluZSBQTExfQ09OMF9QTExfU0hBUkVEMQkJCTB4MDEyMAorI2RlZmluZSBDTEtf Q09OX01VWF9NVVhfQ0xLQ01VX0NPUkVfQlVTCQkweDEwMTQKKyNkZWZpbmUgQ0xLX0NPTl9NVVhf TVVYX0NMS0NNVV9DT1JFX0NDSQkJMHgxMDE4CisjZGVmaW5lIENMS19DT05fTVVYX01VWF9DTEtD TVVfQ09SRV9HM0QJCTB4MTAxYworI2RlZmluZSBDTEtfQ09OX01VWF9NVVhfQ0xLQ01VX1BFUklf QlVTCQkweDEwNTgKKyNkZWZpbmUgQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9QRVJJX1NQSTAJMHgx MDVjCisjZGVmaW5lIENMS19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9TUEkxCTB4MTA2MAorI2Rl ZmluZSBDTEtfQ09OX01VWF9NVVhfQ0xLQ01VX1BFUklfVUFSVDAJMHgxMDY0CisjZGVmaW5lIENM S19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9VQVJUMQkweDEwNjgKKyNkZWZpbmUgQ0xLX0NPTl9N VVhfTVVYX0NMS0NNVV9QRVJJX1VBUlQyCTB4MTA2YworI2RlZmluZSBDTEtfQ09OX01VWF9NVVhf Q0xLQ01VX1BFUklfVVNJMAkweDEwNzAKKyNkZWZpbmUgQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9Q RVJJX1VTSTEJMHgxMDc0CisjZGVmaW5lIENMS19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9VU0ky CTB4MTA3OAorI2RlZmluZSBDTEtfQ09OX0RJVl9DTEtDTVVfQ09SRV9CVVMJCTB4MTgxYworI2Rl ZmluZSBDTEtfQ09OX0RJVl9DTEtDTVVfQ09SRV9DQ0kJCTB4MTgyMAorI2RlZmluZSBDTEtfQ09O X0RJVl9DTEtDTVVfQ09SRV9HM0QJCTB4MTgyNAorI2RlZmluZSBDTEtfQ09OX0RJVl9DTEtDTVVf UEVSSV9CVVMJCTB4MTg3NAorI2RlZmluZSBDTEtfQ09OX0RJVl9DTEtDTVVfUEVSSV9TUEkwCQkw eDE4NzgKKyNkZWZpbmUgQ0xLX0NPTl9ESVZfQ0xLQ01VX1BFUklfU1BJMQkJMHgxODdjCisjZGVm aW5lIENMS19DT05fRElWX0NMS0NNVV9QRVJJX1VBUlQwCQkweDE4ODAKKyNkZWZpbmUgQ0xLX0NP Tl9ESVZfQ0xLQ01VX1BFUklfVUFSVDEJCTB4MTg4NAorI2RlZmluZSBDTEtfQ09OX0RJVl9DTEtD TVVfUEVSSV9VQVJUMgkJMHgxODg4CisjZGVmaW5lIENMS19DT05fRElWX0NMS0NNVV9QRVJJX1VT STAJCTB4MTg4YworI2RlZmluZSBDTEtfQ09OX0RJVl9DTEtDTVVfUEVSSV9VU0kxCQkweDE4OTAK KyNkZWZpbmUgQ0xLX0NPTl9ESVZfQ0xLQ01VX1BFUklfVVNJMgkJMHgxODk0CisjZGVmaW5lIENM S19DT05fRElWX1BMTF9TSEFSRUQwX0RJVjIJCTB4MTg5YworI2RlZmluZSBDTEtfQ09OX0RJVl9Q TExfU0hBUkVEMF9ESVYzCQkweDE4YTAKKyNkZWZpbmUgQ0xLX0NPTl9ESVZfUExMX1NIQVJFRDBf RElWNAkJMHgxOGE0CisjZGVmaW5lIENMS19DT05fRElWX1BMTF9TSEFSRUQwX0RJVjUJCTB4MThh OAorI2RlZmluZSBDTEtfQ09OX0RJVl9QTExfU0hBUkVEMV9ESVYyCQkweDE4YWMKKyNkZWZpbmUg Q0xLX0NPTl9ESVZfUExMX1NIQVJFRDFfRElWMwkJMHgxOGIwCisjZGVmaW5lIENMS19DT05fRElW X1BMTF9TSEFSRUQxX0RJVjQJCTB4MThiNAorI2RlZmluZSBDTEtfQ09OX0dBVF9HQVRFX0NMS0NN VUNfUEVSSV9VQVJUMQkweDIwMDQKKyNkZWZpbmUgQ0xLX0NPTl9HQVRfR0FURV9DTEtDTVVfQ09S RV9CVVMJMHgyMDFjCisjZGVmaW5lIENMS19DT05fR0FUX0dBVEVfQ0xLQ01VX0NPUkVfQ0NJCTB4 MjAyMAorI2RlZmluZSBDTEtfQ09OX0dBVF9HQVRFX0NMS0NNVV9DT1JFX0czRAkweDIwMjQKKyNk ZWZpbmUgQ0xLX0NPTl9HQVRfR0FURV9DTEtDTVVfUEVSSV9CVVMJMHgyMDdjCisjZGVmaW5lIENM S19DT05fR0FUX0dBVEVfQ0xLQ01VX1BFUklfU1BJMAkweDIwODAKKyNkZWZpbmUgQ0xLX0NPTl9H QVRfR0FURV9DTEtDTVVfUEVSSV9TUEkxCTB4MjA4NAorI2RlZmluZSBDTEtfQ09OX0dBVF9HQVRF X0NMS0NNVV9QRVJJX1VBUlQwCTB4MjA4OAorI2RlZmluZSBDTEtfQ09OX0dBVF9HQVRFX0NMS0NN VV9QRVJJX1VBUlQyCTB4MjA4YworI2RlZmluZSBDTEtfQ09OX0dBVF9HQVRFX0NMS0NNVV9QRVJJ X1VTSTAJMHgyMDkwCisjZGVmaW5lIENMS19DT05fR0FUX0dBVEVfQ0xLQ01VX1BFUklfVVNJMQkw eDIwOTQKKyNkZWZpbmUgQ0xLX0NPTl9HQVRfR0FURV9DTEtDTVVfUEVSSV9VU0kyCTB4MjA5OAor CitzdGF0aWMgY29uc3QgdW5zaWduZWQgbG9uZyB0b3BfY2xrX3JlZ3NbXSBfX2luaXRjb25zdCA9 IHsKKwlQTExfTE9DS1RJTUVfUExMX1NIQVJFRDAsCisJUExMX0xPQ0tUSU1FX1BMTF9TSEFSRUQx LAorCVBMTF9DT04wX1BMTF9TSEFSRUQwLAorCVBMTF9DT04wX1BMTF9TSEFSRUQxLAorCUNMS19D T05fTVVYX01VWF9DTEtDTVVfQ09SRV9CVVMsCisJQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9DT1JF X0NDSSwKKwlDTEtfQ09OX01VWF9NVVhfQ0xLQ01VX0NPUkVfRzNELAorCUNMS19DT05fTVVYX01V WF9DTEtDTVVfUEVSSV9CVVMsCisJQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9QRVJJX1NQSTAsCisJ Q0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9QRVJJX1NQSTEsCisJQ0xLX0NPTl9NVVhfTVVYX0NMS0NN VV9QRVJJX1VBUlQwLAorCUNMS19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9VQVJUMSwKKwlDTEtf Q09OX01VWF9NVVhfQ0xLQ01VX1BFUklfVUFSVDIsCisJQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9Q RVJJX1VTSTAsCisJQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9QRVJJX1VTSTEsCisJQ0xLX0NPTl9N VVhfTVVYX0NMS0NNVV9QRVJJX1VTSTIsCisJQ0xLX0NPTl9ESVZfQ0xLQ01VX0NPUkVfQlVTLAor CUNMS19DT05fRElWX0NMS0NNVV9DT1JFX0NDSSwKKwlDTEtfQ09OX0RJVl9DTEtDTVVfQ09SRV9H M0QsCisJQ0xLX0NPTl9ESVZfQ0xLQ01VX1BFUklfQlVTLAorCUNMS19DT05fRElWX0NMS0NNVV9Q RVJJX1NQSTAsCisJQ0xLX0NPTl9ESVZfQ0xLQ01VX1BFUklfU1BJMSwKKwlDTEtfQ09OX0RJVl9D TEtDTVVfUEVSSV9VQVJUMCwKKwlDTEtfQ09OX0RJVl9DTEtDTVVfUEVSSV9VQVJUMSwKKwlDTEtf Q09OX0RJVl9DTEtDTVVfUEVSSV9VQVJUMiwKKwlDTEtfQ09OX0RJVl9DTEtDTVVfUEVSSV9VU0kw LAorCUNMS19DT05fRElWX0NMS0NNVV9QRVJJX1VTSTEsCisJQ0xLX0NPTl9ESVZfQ0xLQ01VX1BF UklfVVNJMiwKKwlDTEtfQ09OX0RJVl9QTExfU0hBUkVEMF9ESVYyLAorCUNMS19DT05fRElWX1BM TF9TSEFSRUQwX0RJVjMsCisJQ0xLX0NPTl9ESVZfUExMX1NIQVJFRDBfRElWNCwKKwlDTEtfQ09O X0RJVl9QTExfU0hBUkVEMF9ESVY1LAorCUNMS19DT05fRElWX1BMTF9TSEFSRUQxX0RJVjIsCisJ Q0xLX0NPTl9ESVZfUExMX1NIQVJFRDFfRElWMywKKwlDTEtfQ09OX0RJVl9QTExfU0hBUkVEMV9E SVY0LAorCUNMS19DT05fR0FUX0dBVEVfQ0xLQ01VQ19QRVJJX1VBUlQxLAorCUNMS19DT05fR0FU X0dBVEVfQ0xLQ01VX0NPUkVfQlVTLAorCUNMS19DT05fR0FUX0dBVEVfQ0xLQ01VX0NPUkVfQ0NJ LAorCUNMS19DT05fR0FUX0dBVEVfQ0xLQ01VX0NPUkVfRzNELAorCUNMS19DT05fR0FUX0dBVEVf Q0xLQ01VX1BFUklfQlVTLAorCUNMS19DT05fR0FUX0dBVEVfQ0xLQ01VX1BFUklfU1BJMCwKKwlD TEtfQ09OX0dBVF9HQVRFX0NMS0NNVV9QRVJJX1NQSTEsCisJQ0xLX0NPTl9HQVRfR0FURV9DTEtD TVVfUEVSSV9VQVJUMCwKKwlDTEtfQ09OX0dBVF9HQVRFX0NMS0NNVV9QRVJJX1VBUlQyLAorCUNM S19DT05fR0FUX0dBVEVfQ0xLQ01VX1BFUklfVVNJMCwKKwlDTEtfQ09OX0dBVF9HQVRFX0NMS0NN VV9QRVJJX1VTSTEsCisJQ0xLX0NPTl9HQVRfR0FURV9DTEtDTVVfUEVSSV9VU0kyLAorfTsKKwor c3RhdGljIGNvbnN0IHN0cnVjdCBzYW1zdW5nX3BsbF9jbG9jayB0b3BfcGxsX2Nsa3NbXSBfX2lu aXRjb25zdCA9IHsKKwlQTEwocGxsXzE0MTd4LCBDTEtfRk9VVF9TSEFSRUQwX1BMTCwgImZvdXRf c2hhcmVkMF9wbGwiLCAib3NjY2xrIiwKKwkgICAgUExMX0xPQ0tUSU1FX1BMTF9TSEFSRUQwLCBQ TExfQ09OMF9QTExfU0hBUkVEMCwKKwkgICAgTlVMTCksCisJUExMKHBsbF8xNDE3eCwgQ0xLX0ZP VVRfU0hBUkVEMV9QTEwsICJmb3V0X3NoYXJlZDFfcGxsIiwgIm9zY2NsayIsCisJICAgIFBMTF9M T0NLVElNRV9QTExfU0hBUkVEMSwgUExMX0NPTjBfUExMX1NIQVJFRDEsCisJICAgIE5VTEwpLAor fTsKKworLyogTGlzdCBvZiBwYXJlbnQgY2xvY2tzIGZvciBNdXhlcyBpbiBDTVVfVE9QOiBmb3Ig Q01VX0NPUkUgKi8KK1BOQU1FKG1vdXRfY29yZV9idXNfcCkJCT0geyAiZG91dF9zaGFyZWQwX2Rp djIiLCAiZG91dF9zaGFyZWQxX2RpdjIiLAorCQkJCSAgICAiZG91dF9zaGFyZWQwX2RpdjMiLCAi ZG91dF9zaGFyZWQwX2RpdjMiIH07CitQTkFNRShtb3V0X2NvcmVfY2NpX3ApCQk9IHsgImRvdXRf c2hhcmVkMF9kaXYyIiwgImRvdXRfc2hhcmVkMV9kaXYyIiwKKwkJCQkgICAgImRvdXRfc2hhcmVk MF9kaXYzIiwgImRvdXRfc2hhcmVkMF9kaXYzIiB9OworUE5BTUUobW91dF9jb3JlX2czZF9wKQkJ PSB7ICJkb3V0X3NoYXJlZDBfZGl2MiIsICJkb3V0X3NoYXJlZDFfZGl2MiIsCisJCQkJICAgICJk b3V0X3NoYXJlZDBfZGl2MyIsICJkb3V0X3NoYXJlZDBfZGl2MyIgfTsKKworLyogTGlzdCBvZiBw YXJlbnQgY2xvY2tzIGZvciBNdXhlcyBpbiBDTVVfVE9QOiBmb3IgQ01VX1BFUkkgKi8KK1BOQU1F KG1vdXRfcGVyaV9idXNfcCkJCT0geyAiZG91dF9zaGFyZWQwX2RpdjQiLCAiZG91dF9zaGFyZWQx X2RpdjQiIH07CitQTkFNRShtb3V0X3Blcmlfc3BpMF9wKQkJPSB7ICJvc2NjbGsiLCAiZG91dF9z aGFyZWQwX2RpdjQiIH07CitQTkFNRShtb3V0X3Blcmlfc3BpMV9wKQkJPSB7ICJvc2NjbGsiLCAi ZG91dF9zaGFyZWQwX2RpdjQiIH07CitQTkFNRShtb3V0X3BlcmlfdWFydDBfcCkJPSB7ICJvc2Nj bGsiLCAiZG91dF9zaGFyZWQwX2RpdjQiIH07CitQTkFNRShtb3V0X3BlcmlfdWFydDFfcCkJPSB7 ICJvc2NjbGsiLCAiZG91dF9zaGFyZWQwX2RpdjQiIH07CitQTkFNRShtb3V0X3BlcmlfdWFydDJf cCkJPSB7ICJvc2NjbGsiLCAiZG91dF9zaGFyZWQwX2RpdjQiIH07CitQTkFNRShtb3V0X3Blcmlf dXNpMF9wKQkJPSB7ICJvc2NjbGsiLCAiZG91dF9zaGFyZWQwX2RpdjQiIH07CitQTkFNRShtb3V0 X3BlcmlfdXNpMV9wKQkJPSB7ICJvc2NjbGsiLCAiZG91dF9zaGFyZWQwX2RpdjQiIH07CitQTkFN RShtb3V0X3BlcmlfdXNpMl9wKQkJPSB7ICJvc2NjbGsiLCAiZG91dF9zaGFyZWQwX2RpdjQiIH07 CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgc2Ftc3VuZ19tdXhfY2xvY2sgdG9wX211eF9jbGtzW10g X19pbml0Y29uc3QgPSB7CisJLyogQ09SRSAqLworCU1VWChDTEtfTU9VVF9DT1JFX0JVUywgIm1v dXRfY29yZV9idXMiLCBtb3V0X2NvcmVfYnVzX3AsCisJICAgIENMS19DT05fTVVYX01VWF9DTEtD TVVfQ09SRV9CVVMsIDAsIDIpLAorCU1VWChDTEtfTU9VVF9DT1JFX0NDSSwgIm1vdXRfY29yZV9j Y2kiLCBtb3V0X2NvcmVfY2NpX3AsCisJICAgIENMS19DT05fTVVYX01VWF9DTEtDTVVfQ09SRV9D Q0ksIDAsIDIpLAorCU1VWChDTEtfTU9VVF9DT1JFX0czRCwgIm1vdXRfY29yZV9nM2QiLCBtb3V0 X2NvcmVfZzNkX3AsCisJICAgIENMS19DT05fTVVYX01VWF9DTEtDTVVfQ09SRV9HM0QsIDAsIDIp LAorCisJLyogUEVSSSAqLworCU1VWChDTEtfTU9VVF9QRVJJX0JVUywgIm1vdXRfcGVyaV9idXMi LCBtb3V0X3BlcmlfYnVzX3AsCisJICAgIENMS19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9CVVMs IDAsIDEpLAorCU1VWChDTEtfTU9VVF9QRVJJX1NQSTAsICJtb3V0X3Blcmlfc3BpMCIsIG1vdXRf cGVyaV9zcGkwX3AsCisJICAgIENMS19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9TUEkwLCAwLCAx KSwKKwlNVVgoQ0xLX01PVVRfUEVSSV9TUEkxLCAibW91dF9wZXJpX3NwaTEiLCBtb3V0X3Blcmlf c3BpMV9wLAorCSAgICBDTEtfQ09OX01VWF9NVVhfQ0xLQ01VX1BFUklfU1BJMSwgMCwgMSksCisJ TVVYKENMS19NT1VUX1BFUklfVUFSVDAsICJtb3V0X3BlcmlfdWFydDAiLCBtb3V0X3BlcmlfdWFy dDBfcCwKKwkgICAgQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9QRVJJX1VBUlQwLCAwLCAxKSwKKwlN VVgoQ0xLX01PVVRfUEVSSV9VQVJUMSwgIm1vdXRfcGVyaV91YXJ0MSIsIG1vdXRfcGVyaV91YXJ0 MV9wLAorCSAgICBDTEtfQ09OX01VWF9NVVhfQ0xLQ01VX1BFUklfVUFSVDEsIDAsIDEpLAorCU1V WChDTEtfTU9VVF9QRVJJX1VBUlQyLCAibW91dF9wZXJpX3VhcnQyIiwgbW91dF9wZXJpX3VhcnQy X3AsCisJICAgIENMS19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9VQVJUMiwgMCwgMSksCisJTVVY KENMS19NT1VUX1BFUklfVVNJMCwgIm1vdXRfcGVyaV91c2kwIiwgbW91dF9wZXJpX3VzaTBfcCwK KwkgICAgQ0xLX0NPTl9NVVhfTVVYX0NMS0NNVV9QRVJJX1VTSTAsIDAsIDEpLAorCU1VWChDTEtf TU9VVF9QRVJJX1VTSTEsICJtb3V0X3BlcmlfdXNpMSIsIG1vdXRfcGVyaV91c2kxX3AsCisJICAg IENMS19DT05fTVVYX01VWF9DTEtDTVVfUEVSSV9VU0kxLCAwLCAxKSwKKwlNVVgoQ0xLX01PVVRf UEVSSV9VU0kyLCAibW91dF9wZXJpX3VzaTIiLCBtb3V0X3BlcmlfdXNpMl9wLAorCSAgICBDTEtf Q09OX01VWF9NVVhfQ0xLQ01VX1BFUklfVVNJMiwgMCwgMSksCit9OworCitzdGF0aWMgY29uc3Qg c3RydWN0IHNhbXN1bmdfZGl2X2Nsb2NrIHRvcF9kaXZfY2xrc1tdIF9faW5pdGNvbnN0ID0gewor CS8qIFRPUCAqLworCURJVihDTEtfRE9VVF9TSEFSRUQwX0RJVjIsICJkb3V0X3NoYXJlZDBfZGl2 MiIsICJmb3V0X3NoYXJlZDBfcGxsIiwKKwkgICAgQ0xLX0NPTl9ESVZfUExMX1NIQVJFRDBfRElW MiwgMCwgMSksCisJRElWKENMS19ET1VUX1NIQVJFRDBfRElWMywgImRvdXRfc2hhcmVkMF9kaXYz IiwgImZvdXRfc2hhcmVkMF9wbGwiLAorCSAgICBDTEtfQ09OX0RJVl9QTExfU0hBUkVEMF9ESVYz LCAwLCAyKSwKKwlESVYoQ0xLX0RPVVRfU0hBUkVEMF9ESVY0LCAiZG91dF9zaGFyZWQwX2RpdjQi LCAiZm91dF9zaGFyZWQwX3BsbCIsCisJICAgIENMS19DT05fRElWX1BMTF9TSEFSRUQwX0RJVjQs IDAsIDEpLAorCURJVihDTEtfRE9VVF9TSEFSRUQwX0RJVjUsICJkb3V0X3NoYXJlZDBfZGl2NSIs ICJmb3V0X3NoYXJlZDBfcGxsIiwKKwkgICAgQ0xLX0NPTl9ESVZfUExMX1NIQVJFRDBfRElWNSwg MCwgMyksCisJRElWKENMS19ET1VUX1NIQVJFRDFfRElWMiwgImRvdXRfc2hhcmVkMV9kaXYyIiwg ImZvdXRfc2hhcmVkMV9wbGwiLAorCSAgICBDTEtfQ09OX0RJVl9QTExfU0hBUkVEMV9ESVYyLCAw LCAxKSwKKwlESVYoQ0xLX0RPVVRfU0hBUkVEMV9ESVYzLCAiZG91dF9zaGFyZWQxX2RpdjMiLCAi Zm91dF9zaGFyZWQxX3BsbCIsCisJICAgIENMS19DT05fRElWX1BMTF9TSEFSRUQxX0RJVjMsIDAs IDIpLAorCURJVihDTEtfRE9VVF9TSEFSRUQxX0RJVjQsICJkb3V0X3NoYXJlZDFfZGl2NCIsICJm b3V0X3NoYXJlZDFfcGxsIiwKKwkgICAgQ0xLX0NPTl9ESVZfUExMX1NIQVJFRDFfRElWNCwgMCwg MSksCisKKwkvKiBDT1JFICovCisJRElWKENMS19ET1VUX0NPUkVfQlVTLCAiZG91dF9jb3JlX2J1 cyIsICJnb3V0X2NvcmVfYnVzIiwKKwkgICAgQ0xLX0NPTl9ESVZfQ0xLQ01VX0NPUkVfQlVTLCAw LCAzKSwKKwlESVYoQ0xLX0RPVVRfQ09SRV9DQ0ksICJkb3V0X2NvcmVfY2NpIiwgImdvdXRfY29y ZV9jY2kiLAorCSAgICBDTEtfQ09OX0RJVl9DTEtDTVVfQ09SRV9DQ0ksIDAsIDMpLAorCURJVihD TEtfRE9VVF9DT1JFX0czRCwgImRvdXRfY29yZV9nM2QiLCAiZ291dF9jb3JlX2czZCIsCisJICAg IENMS19DT05fRElWX0NMS0NNVV9DT1JFX0czRCwgMCwgMyksCisKKwkvKiBQRVJJICovCisJRElW KENMS19ET1VUX1BFUklfQlVTLCAiZG91dF9wZXJpX2J1cyIsICJnb3V0X3BlcmlfYnVzIiwKKwkg ICAgQ0xLX0NPTl9ESVZfQ0xLQ01VX1BFUklfQlVTLCAwLCA0KSwKKwlESVYoQ0xLX0RPVVRfUEVS SV9TUEkwLCAiZG91dF9wZXJpX3NwaTAiLCAiZ291dF9wZXJpX3NwaTAiLAorCSAgICBDTEtfQ09O X0RJVl9DTEtDTVVfUEVSSV9TUEkwLCAwLCA2KSwKKwlESVYoQ0xLX0RPVVRfUEVSSV9TUEkxLCAi ZG91dF9wZXJpX3NwaTEiLCAiZ291dF9wZXJpX3NwaTEiLAorCSAgICBDTEtfQ09OX0RJVl9DTEtD TVVfUEVSSV9TUEkxLCAwLCA2KSwKKwlESVYoQ0xLX0RPVVRfUEVSSV9VQVJUMCwgImRvdXRfcGVy aV91YXJ0MCIsICJnb3V0X3BlcmlfdWFydDAiLAorCSAgICBDTEtfQ09OX0RJVl9DTEtDTVVfUEVS SV9VQVJUMCwgMCwgNCksCisJRElWKENMS19ET1VUX1BFUklfVUFSVDEsICJkb3V0X3BlcmlfdWFy dDEiLCAiZ291dF9wZXJpX3VhcnQxIiwKKwkgICAgQ0xLX0NPTl9ESVZfQ0xLQ01VX1BFUklfVUFS VDEsIDAsIDQpLAorCURJVihDTEtfRE9VVF9QRVJJX1VBUlQyLCAiZG91dF9wZXJpX3VhcnQyIiwg ImdvdXRfcGVyaV91YXJ0MiIsCisJICAgIENMS19DT05fRElWX0NMS0NNVV9QRVJJX1VBUlQyLCAw LCA0KSwKKwlESVYoQ0xLX0RPVVRfUEVSSV9VU0kwLCAiZG91dF9wZXJpX3VzaTAiLCAiZ291dF9w ZXJpX3VzaTAiLAorCSAgICBDTEtfQ09OX0RJVl9DTEtDTVVfUEVSSV9VU0kwLCAwLCA0KSwKKwlE SVYoQ0xLX0RPVVRfUEVSSV9VU0kxLCAiZG91dF9wZXJpX3VzaTEiLCAiZ291dF9wZXJpX3VzaTEi LAorCSAgICBDTEtfQ09OX0RJVl9DTEtDTVVfUEVSSV9VU0kxLCAwLCA0KSwKKwlESVYoQ0xLX0RP VVRfUEVSSV9VU0kyLCAiZG91dF9wZXJpX3VzaTIiLCAiZ291dF9wZXJpX3VzaTIiLAorCSAgICBD TEtfQ09OX0RJVl9DTEtDTVVfUEVSSV9VU0kyLCAwLCA0KSwKK307CisKK3N0YXRpYyBjb25zdCBz dHJ1Y3Qgc2Ftc3VuZ19nYXRlX2Nsb2NrIHRvcF9nYXRlX2Nsa3NbXSBfX2luaXRjb25zdCA9IHsK KwkvKiBDT1JFICovCisJR0FURShDTEtfR09VVF9DT1JFX0JVUywgImdvdXRfY29yZV9idXMiLCAi bW91dF9jb3JlX2J1cyIsCisJICAgICBDTEtfQ09OX0dBVF9HQVRFX0NMS0NNVV9DT1JFX0JVUywg MjEsIDAsIDApLAorCUdBVEUoQ0xLX0dPVVRfQ09SRV9DQ0ksICJnb3V0X2NvcmVfY2NpIiwgIm1v dXRfY29yZV9jY2kiLAorCSAgICAgQ0xLX0NPTl9HQVRfR0FURV9DTEtDTVVfQ09SRV9DQ0ksIDIx LCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX0NPUkVfRzNELCAiZ291dF9jb3JlX2czZCIsICJtb3V0 X2NvcmVfZzNkIiwKKwkgICAgIENMS19DT05fR0FUX0dBVEVfQ0xLQ01VX0NPUkVfRzNELCAyMSwg MCwgMCksCisKKwkvKiBQRVJJICovCisJR0FURShDTEtfR09VVF9QRVJJX0JVUywgImdvdXRfcGVy aV9idXMiLCAibW91dF9wZXJpX2J1cyIsCisJICAgICBDTEtfQ09OX0dBVF9HQVRFX0NMS0NNVV9Q RVJJX0JVUywgMjEsIDAsIDApLAorCUdBVEUoQ0xLX0dPVVRfUEVSSV9TUEkwLCAiZ291dF9wZXJp X3NwaTAiLCAibW91dF9wZXJpX3NwaTAiLAorCSAgICAgQ0xLX0NPTl9HQVRfR0FURV9DTEtDTVVf UEVSSV9TUEkwLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9QRVJJX1NQSTEsICJnb3V0X3Bl cmlfc3BpMSIsICJtb3V0X3Blcmlfc3BpMSIsCisJICAgICBDTEtfQ09OX0dBVF9HQVRFX0NMS0NN VV9QRVJJX1NQSTEsIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX1BFUklfVUFSVDAsICJnb3V0 X3BlcmlfdWFydDAiLCAibW91dF9wZXJpX3VhcnQwIiwKKwkgICAgIENMS19DT05fR0FUX0dBVEVf Q0xLQ01VX1BFUklfVUFSVDAsIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX1BFUklfVUFSVDEs ICJnb3V0X3BlcmlfdWFydDEiLCAibW91dF9wZXJpX3VhcnQxIiwKKwkgICAgIENMS19DT05fR0FU X0dBVEVfQ0xLQ01VQ19QRVJJX1VBUlQxLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9QRVJJ X1VBUlQyLCAiZ291dF9wZXJpX3VhcnQyIiwgIm1vdXRfcGVyaV91YXJ0MiIsCisJICAgICBDTEtf Q09OX0dBVF9HQVRFX0NMS0NNVV9QRVJJX1VBUlQyLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09V VF9QRVJJX1VTSTAsICJnb3V0X3BlcmlfdXNpMCIsICJtb3V0X3BlcmlfdXNpMCIsCisJICAgICBD TEtfQ09OX0dBVF9HQVRFX0NMS0NNVV9QRVJJX1VTSTAsIDIxLCAwLCAwKSwKKwlHQVRFKENMS19H T1VUX1BFUklfVVNJMSwgImdvdXRfcGVyaV91c2kxIiwgIm1vdXRfcGVyaV91c2kxIiwKKwkgICAg IENMS19DT05fR0FUX0dBVEVfQ0xLQ01VX1BFUklfVVNJMSwgMjEsIDAsIDApLAorCUdBVEUoQ0xL X0dPVVRfUEVSSV9VU0kyLCAiZ291dF9wZXJpX3VzaTIiLCAibW91dF9wZXJpX3VzaTIiLAorCSAg ICAgQ0xLX0NPTl9HQVRfR0FURV9DTEtDTVVfUEVSSV9VU0kyLCAyMSwgMCwgMCksCit9OworCitz dGF0aWMgY29uc3Qgc3RydWN0IHNhbXN1bmdfY211X2luZm8gdG9wX2NtdV9pbmZvIF9faW5pdGNv bnN0ID0geworCS5wbGxfY2xrcwkJPSB0b3BfcGxsX2Nsa3MsCisJLm5yX3BsbF9jbGtzCQk9IEFS UkFZX1NJWkUodG9wX3BsbF9jbGtzKSwKKwkubXV4X2Nsa3MJCT0gdG9wX211eF9jbGtzLAorCS5u cl9tdXhfY2xrcwkJPSBBUlJBWV9TSVpFKHRvcF9tdXhfY2xrcyksCisJLmRpdl9jbGtzCQk9IHRv cF9kaXZfY2xrcywKKwkubnJfZGl2X2Nsa3MJCT0gQVJSQVlfU0laRSh0b3BfZGl2X2Nsa3MpLAor CS5nYXRlX2Nsa3MJCT0gdG9wX2dhdGVfY2xrcywKKwkubnJfZ2F0ZV9jbGtzCQk9IEFSUkFZX1NJ WkUodG9wX2dhdGVfY2xrcyksCisJLm5yX2Nsa19pZHMJCT0gVE9QX05SX0NMSywKKwkuY2xrX3Jl Z3MJCT0gdG9wX2Nsa19yZWdzLAorCS5ucl9jbGtfcmVncwkJPSBBUlJBWV9TSVpFKHRvcF9jbGtf cmVncyksCit9OworCitzdGF0aWMgdm9pZCBfX2luaXQgZXh5bm9zNzg4NV9jbXVfdG9wX2luaXQo c3RydWN0IGRldmljZV9ub2RlICpucCkKK3sKKwlleHlub3NfYXJtNjRfcmVnaXN0ZXJfY211KE5V TEwsIG5wLCAmdG9wX2NtdV9pbmZvKTsKK30KKworLyogUmVnaXN0ZXIgQ01VX1RPUCBlYXJseSwg YXMgaXQncyBhIGRlcGVuZGVuY3kgZm9yIG90aGVyIGVhcmx5IGRvbWFpbnMgKi8KK0NMS19PRl9E RUNMQVJFKGV4eW5vczc4ODVfY211X3RvcCwgInNhbXN1bmcsZXh5bm9zNzg4NS1jbXUtdG9wIiwK KwkgICAgICAgZXh5bm9zNzg4NV9jbXVfdG9wX2luaXQpOworCisvKiAtLS0tIENNVV9QRVJJIC0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LSAqLworCisvKiBSZWdpc3RlciBPZmZzZXQgZGVmaW5pdGlvbnMgZm9yIENNVV9QRVJJICgweDEw MDEwMDAwKSAqLworI2RlZmluZSBQTExfQ09OMF9NVVhfQ0xLQ01VX1BFUklfQlVTX1VTRVIJMHgw MTAwCisjZGVmaW5lIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9TUEkwX1VTRVIJMHgwMTIwCisj ZGVmaW5lIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9TUEkxX1VTRVIJMHgwMTQwCisjZGVmaW5l IFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9VQVJUMF9VU0VSCTB4MDE2MAorI2RlZmluZSBQTExf Q09OMF9NVVhfQ0xLQ01VX1BFUklfVUFSVDFfVVNFUgkweDAxODAKKyNkZWZpbmUgUExMX0NPTjBf TVVYX0NMS0NNVV9QRVJJX1VBUlQyX1VTRVIJMHgwMWEwCisjZGVmaW5lIFBMTF9DT04wX01VWF9D TEtDTVVfUEVSSV9VU0kwX1VTRVIJMHgwMWMwCisjZGVmaW5lIFBMTF9DT04wX01VWF9DTEtDTVVf UEVSSV9VU0kxX1VTRVIJMHgwMWUwCisjZGVmaW5lIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9V U0kyX1VTRVIJMHgwMjAwCisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRfUEVSSV9HUElPX1RPUF9Q Q0xLCTB4MjAyNAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSFNJMkNfMF9QQ0xLCTB4 MjAyOAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSFNJMkNfMV9QQ0xLCTB4MjAyYwor I2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSFNJMkNfMl9QQ0xLCTB4MjAzMAorI2RlZmlu ZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSFNJMkNfM19QQ0xLCTB4MjAzNAorI2RlZmluZSBDTEtf Q09OX0dBVF9HT1VUX1BFUklfSTJDXzBfUENMSwkweDIwMzgKKyNkZWZpbmUgQ0xLX0NPTl9HQVRf R09VVF9QRVJJX0kyQ18xX1BDTEsJMHgyMDNjCisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRfUEVS SV9JMkNfMl9QQ0xLCTB4MjA0MAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzNf UENMSwkweDIwNDQKKyNkZWZpbmUgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX0kyQ180X1BDTEsJMHgy MDQ4CisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRfUEVSSV9JMkNfNV9QQ0xLCTB4MjA0YworI2Rl ZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzZfUENMSwkweDIwNTAKKyNkZWZpbmUgQ0xL X0NPTl9HQVRfR09VVF9QRVJJX0kyQ183X1BDTEsJMHgyMDU0CisjZGVmaW5lIENMS19DT05fR0FU X0dPVVRfUEVSSV9QV01fTU9UT1JfUENMSwkweDIwNTgKKyNkZWZpbmUgQ0xLX0NPTl9HQVRfR09V VF9QRVJJX1NQSV8wX1BDTEsJMHgyMDVjCisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRfUEVSSV9T UElfMF9FWFRfQ0xLCTB4MjA2MAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfU1BJXzFf UENMSwkweDIwNjQKKyNkZWZpbmUgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1NQSV8xX0VYVF9DTEsJ MHgyMDY4CisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRfUEVSSV9VQVJUXzBfRVhUX1VDTEsJMHgy MDZjCisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRfUEVSSV9VQVJUXzBfUENMSwkweDIwNzAKKyNk ZWZpbmUgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VBUlRfMV9FWFRfVUNMSwkweDIwNzQKKyNkZWZp bmUgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VBUlRfMV9QQ0xLCTB4MjA3OAorI2RlZmluZSBDTEtf Q09OX0dBVF9HT1VUX1BFUklfVUFSVF8yX0VYVF9VQ0xLCTB4MjA3YworI2RlZmluZSBDTEtfQ09O X0dBVF9HT1VUX1BFUklfVUFSVF8yX1BDTEsJMHgyMDgwCisjZGVmaW5lIENMS19DT05fR0FUX0dP VVRfUEVSSV9VU0kwX1BDTEsJCTB4MjA4NAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklf VVNJMF9TQ0xLCQkweDIwODgKKyNkZWZpbmUgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VTSTFfUENM SwkJMHgyMDhjCisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRfUEVSSV9VU0kxX1NDTEsJCTB4MjA5 MAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX1BFUklfVVNJMl9QQ0xLCQkweDIwOTQKKyNkZWZp bmUgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VTSTJfU0NMSwkJMHgyMDk4CisjZGVmaW5lIENMS19D T05fR0FUX0dPVVRfUEVSSV9NQ1RfUENMSwkJMHgyMGEwCisjZGVmaW5lIENMS19DT05fR0FUX0dP VVRfUEVSSV9TWVNSRUdfUEVSSV9QQ0xLCTB4MjBiMAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VU X1BFUklfV0RUX0NMVVNURVIwX1BDTEsJMHgyMGI0CisjZGVmaW5lIENMS19DT05fR0FUX0dPVVRf UEVSSV9XRFRfQ0xVU1RFUjFfUENMSwkweDIwYjgKKworc3RhdGljIGNvbnN0IHVuc2lnbmVkIGxv bmcgcGVyaV9jbGtfcmVnc1tdIF9faW5pdGNvbnN0ID0geworCVBMTF9DT04wX01VWF9DTEtDTVVf UEVSSV9CVVNfVVNFUiwKKwlQTExfQ09OMF9NVVhfQ0xLQ01VX1BFUklfU1BJMF9VU0VSLAorCVBM TF9DT04wX01VWF9DTEtDTVVfUEVSSV9TUEkxX1VTRVIsCisJUExMX0NPTjBfTVVYX0NMS0NNVV9Q RVJJX1VBUlQwX1VTRVIsCisJUExMX0NPTjBfTVVYX0NMS0NNVV9QRVJJX1VBUlQxX1VTRVIsCisJ UExMX0NPTjBfTVVYX0NMS0NNVV9QRVJJX1VBUlQyX1VTRVIsCisJUExMX0NPTjBfTVVYX0NMS0NN VV9QRVJJX1VTSTBfVVNFUiwKKwlQTExfQ09OMF9NVVhfQ0xLQ01VX1BFUklfVVNJMV9VU0VSLAor CVBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9VU0kyX1VTRVIsCisJQ0xLX0NPTl9HQVRfR09VVF9Q RVJJX0dQSU9fVE9QX1BDTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX0hTSTJDXzBfUENMSywK KwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfSFNJMkNfMV9QQ0xLLAorCUNMS19DT05fR0FUX0dPVVRf UEVSSV9IU0kyQ18yX1BDTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX0hTSTJDXzNfUENMSywK KwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzBfUENMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BF UklfSTJDXzFfUENMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzJfUENMSywKKwlDTEtf Q09OX0dBVF9HT1VUX1BFUklfSTJDXzNfUENMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJD XzRfUENMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzVfUENMSywKKwlDTEtfQ09OX0dB VF9HT1VUX1BFUklfSTJDXzZfUENMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzdfUENM SywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfUFdNX01PVE9SX1BDTEssCisJQ0xLX0NPTl9HQVRf R09VVF9QRVJJX1NQSV8wX1BDTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1NQSV8wX0VYVF9D TEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1NQSV8xX1BDTEssCisJQ0xLX0NPTl9HQVRfR09V VF9QRVJJX1NQSV8xX0VYVF9DTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VBUlRfMF9FWFRf VUNMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfVUFSVF8wX1BDTEssCisJQ0xLX0NPTl9HQVRf R09VVF9QRVJJX1VBUlRfMV9FWFRfVUNMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfVUFSVF8x X1BDTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VBUlRfMl9FWFRfVUNMSywKKwlDTEtfQ09O X0dBVF9HT1VUX1BFUklfVUFSVF8yX1BDTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VTSTBf UENMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfVVNJMF9TQ0xLLAorCUNMS19DT05fR0FUX0dP VVRfUEVSSV9VU0kxX1BDTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1VTSTFfU0NMSywKKwlD TEtfQ09OX0dBVF9HT1VUX1BFUklfVVNJMl9QQ0xLLAorCUNMS19DT05fR0FUX0dPVVRfUEVSSV9V U0kyX1NDTEssCisJQ0xLX0NPTl9HQVRfR09VVF9QRVJJX01DVF9QQ0xLLAorCUNMS19DT05fR0FU X0dPVVRfUEVSSV9TWVNSRUdfUEVSSV9QQ0xLLAorCUNMS19DT05fR0FUX0dPVVRfUEVSSV9XRFRf Q0xVU1RFUjBfUENMSywKKwlDTEtfQ09OX0dBVF9HT1VUX1BFUklfV0RUX0NMVVNURVIxX1BDTEss Cit9OworCisvKiBMaXN0IG9mIHBhcmVudCBjbG9ja3MgZm9yIE11eGVzIGluIENNVV9QRVJJICov CitQTkFNRShtb3V0X3BlcmlfYnVzX3VzZXJfcCkJPSB7ICJvc2NjbGsiLCAiZG91dF9wZXJpX2J1 cyIgfTsKK1BOQU1FKG1vdXRfcGVyaV9zcGkwX3VzZXJfcCkJPSB7ICJvc2NjbGsiLCAiZG91dF9w ZXJpX3NwaTAiIH07CitQTkFNRShtb3V0X3Blcmlfc3BpMV91c2VyX3ApCT0geyAib3NjY2xrIiwg ImRvdXRfcGVyaV9zcGkxIiB9OworUE5BTUUobW91dF9wZXJpX3VhcnQwX3VzZXJfcCkJPSB7ICJv c2NjbGsiLCAiZG91dF9wZXJpX3VhcnQwIiB9OworUE5BTUUobW91dF9wZXJpX3VhcnQxX3VzZXJf cCkJPSB7ICJvc2NjbGsiLCAiZG91dF9wZXJpX3VhcnQxIiB9OworUE5BTUUobW91dF9wZXJpX3Vh cnQyX3VzZXJfcCkJPSB7ICJvc2NjbGsiLCAiZG91dF9wZXJpX3VhcnQyIiB9OworUE5BTUUobW91 dF9wZXJpX3VzaTBfdXNlcl9wKQk9IHsgIm9zY2NsayIsICJkb3V0X3BlcmlfdXNpMCIgfTsKK1BO QU1FKG1vdXRfcGVyaV91c2kxX3VzZXJfcCkJPSB7ICJvc2NjbGsiLCAiZG91dF9wZXJpX3VzaTEi IH07CitQTkFNRShtb3V0X3BlcmlfdXNpMl91c2VyX3ApCT0geyAib3NjY2xrIiwgImRvdXRfcGVy aV91c2kyIiB9OworCitzdGF0aWMgY29uc3Qgc3RydWN0IHNhbXN1bmdfbXV4X2Nsb2NrIHBlcmlf bXV4X2Nsa3NbXSBfX2luaXRjb25zdCA9IHsKKwlNVVgoQ0xLX01PVVRfUEVSSV9CVVNfVVNFUiwg Im1vdXRfcGVyaV9idXNfdXNlciIsIG1vdXRfcGVyaV9idXNfdXNlcl9wLAorCSAgICBQTExfQ09O MF9NVVhfQ0xLQ01VX1BFUklfQlVTX1VTRVIsIDQsIDEpLAorCU1VWChDTEtfTU9VVF9QRVJJX1NQ STBfVVNFUiwgIm1vdXRfcGVyaV9zcGkwX3VzZXIiLCBtb3V0X3Blcmlfc3BpMF91c2VyX3AsCisJ ICAgIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9TUEkwX1VTRVIsIDQsIDEpLAorCU1VWChDTEtf TU9VVF9QRVJJX1NQSTFfVVNFUiwgIm1vdXRfcGVyaV9zcGkxX3VzZXIiLCBtb3V0X3Blcmlfc3Bp MV91c2VyX3AsCisJICAgIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9TUEkxX1VTRVIsIDQsIDEp LAorCU1VWChDTEtfTU9VVF9QRVJJX1VBUlQwX1VTRVIsICJtb3V0X3BlcmlfdWFydDBfdXNlciIs CisJICAgIG1vdXRfcGVyaV91YXJ0MF91c2VyX3AsIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9V QVJUMF9VU0VSLCA0LCAxKSwKKwlNVVgoQ0xLX01PVVRfUEVSSV9VQVJUMV9VU0VSLCAibW91dF9w ZXJpX3VhcnQxX3VzZXIiLAorCSAgICBtb3V0X3BlcmlfdWFydDFfdXNlcl9wLCBQTExfQ09OMF9N VVhfQ0xLQ01VX1BFUklfVUFSVDFfVVNFUiwgNCwgMSksCisJTVVYKENMS19NT1VUX1BFUklfVUFS VDJfVVNFUiwgIm1vdXRfcGVyaV91YXJ0Ml91c2VyIiwKKwkgICAgbW91dF9wZXJpX3VhcnQyX3Vz ZXJfcCwgUExMX0NPTjBfTVVYX0NMS0NNVV9QRVJJX1VBUlQyX1VTRVIsIDQsIDEpLAorCU1VWChD TEtfTU9VVF9QRVJJX1VTSTBfVVNFUiwgIm1vdXRfcGVyaV91c2kwX3VzZXIiLAorCSAgICBtb3V0 X3BlcmlfdXNpMF91c2VyX3AsIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9VU0kwX1VTRVIsIDQs IDEpLAorCU1VWChDTEtfTU9VVF9QRVJJX1VTSTFfVVNFUiwgIm1vdXRfcGVyaV91c2kxX3VzZXIi LAorCSAgICBtb3V0X3BlcmlfdXNpMV91c2VyX3AsIFBMTF9DT04wX01VWF9DTEtDTVVfUEVSSV9V U0kxX1VTRVIsIDQsIDEpLAorCU1VWChDTEtfTU9VVF9QRVJJX1VTSTJfVVNFUiwgIm1vdXRfcGVy aV91c2kyX3VzZXIiLAorCSAgICBtb3V0X3BlcmlfdXNpMl91c2VyX3AsIFBMTF9DT04wX01VWF9D TEtDTVVfUEVSSV9VU0kyX1VTRVIsIDQsIDEpLAorfTsKKworc3RhdGljIGNvbnN0IHN0cnVjdCBz YW1zdW5nX2dhdGVfY2xvY2sgcGVyaV9nYXRlX2Nsa3NbXSBfX2luaXRjb25zdCA9IHsKKwkvKiBU T0RPOiBTaG91bGQgYmUgZW5hYmxlZCBpbiBHUElPIGRyaXZlciAob3IgbWFkZSBDTEtfSVNfQ1JJ VElDQUwpICovCisJR0FURShDTEtfR09VVF9HUElPX1RPUF9QQ0xLLCAiZ291dF9ncGlvX3RvcF9w Y2xrIiwKKwkgICAgICJtb3V0X3BlcmlfYnVzX3VzZXIiLAorCSAgICAgQ0xLX0NPTl9HQVRfR09V VF9QRVJJX0dQSU9fVE9QX1BDTEssIDIxLCBDTEtfSUdOT1JFX1VOVVNFRCwgMCksCisJR0FURShD TEtfR09VVF9IU0kyQzBfUENMSywgImdvdXRfaHNpMmMwX3BjbGsiLCAibW91dF9wZXJpX2J1c191 c2VyIiwKKwkgICAgIENMS19DT05fR0FUX0dPVVRfUEVSSV9IU0kyQ18wX1BDTEssIDIxLCAwLCAw KSwKKwlHQVRFKENMS19HT1VUX0hTSTJDMV9QQ0xLLCAiZ291dF9oc2kyYzFfcGNsayIsICJtb3V0 X3BlcmlfYnVzX3VzZXIiLAorCSAgICAgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX0hTSTJDXzFfUENM SywgMjEsIDAsIDApLAorCUdBVEUoQ0xLX0dPVVRfSFNJMkMyX1BDTEssICJnb3V0X2hzaTJjMl9w Y2xrIiwgIm1vdXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklf SFNJMkNfMl9QQ0xLLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9IU0kyQzNfUENMSywgImdv dXRfaHNpMmMzX3BjbGsiLCAibW91dF9wZXJpX2J1c191c2VyIiwKKwkgICAgIENMS19DT05fR0FU X0dPVVRfUEVSSV9IU0kyQ18zX1BDTEssIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX0kyQzBf UENMSywgImdvdXRfaTJjMF9wY2xrIiwgIm1vdXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtf Q09OX0dBVF9HT1VUX1BFUklfSTJDXzBfUENMSywgMjEsIDAsIDApLAorCUdBVEUoQ0xLX0dPVVRf STJDMV9QQ0xLLCAiZ291dF9pMmMxX3BjbGsiLCAibW91dF9wZXJpX2J1c191c2VyIiwKKwkgICAg IENMS19DT05fR0FUX0dPVVRfUEVSSV9JMkNfMV9QQ0xLLCAyMSwgMCwgMCksCisJR0FURShDTEtf R09VVF9JMkMyX1BDTEssICJnb3V0X2kyYzJfcGNsayIsICJtb3V0X3BlcmlfYnVzX3VzZXIiLAor CSAgICAgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX0kyQ18yX1BDTEssIDIxLCAwLCAwKSwKKwlHQVRF KENMS19HT1VUX0kyQzNfUENMSywgImdvdXRfaTJjM19wY2xrIiwgIm1vdXRfcGVyaV9idXNfdXNl ciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzNfUENMSywgMjEsIDAsIDApLAor CUdBVEUoQ0xLX0dPVVRfSTJDNF9QQ0xLLCAiZ291dF9pMmM0X3BjbGsiLCAibW91dF9wZXJpX2J1 c191c2VyIiwKKwkgICAgIENMS19DT05fR0FUX0dPVVRfUEVSSV9JMkNfNF9QQ0xLLCAyMSwgMCwg MCksCisJR0FURShDTEtfR09VVF9JMkM1X1BDTEssICJnb3V0X2kyYzVfcGNsayIsICJtb3V0X3Bl cmlfYnVzX3VzZXIiLAorCSAgICAgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX0kyQ181X1BDTEssIDIx LCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX0kyQzZfUENMSywgImdvdXRfaTJjNl9wY2xrIiwgIm1v dXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfSTJDXzZfUENM SywgMjEsIDAsIDApLAorCUdBVEUoQ0xLX0dPVVRfSTJDN19QQ0xLLCAiZ291dF9pMmM3X3BjbGsi LCAibW91dF9wZXJpX2J1c191c2VyIiwKKwkgICAgIENMS19DT05fR0FUX0dPVVRfUEVSSV9JMkNf N19QQ0xLLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9QV01fTU9UT1JfUENMSywgImdvdXRf cHdtX21vdG9yX3BjbGsiLAorCSAgICAgIm1vdXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtf Q09OX0dBVF9HT1VUX1BFUklfUFdNX01PVE9SX1BDTEssIDIxLCAwLCAwKSwKKwlHQVRFKENMS19H T1VUX1NQSTBfUENMSywgImdvdXRfc3BpMF9wY2xrIiwgIm1vdXRfcGVyaV9idXNfdXNlciIsCisJ ICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfU1BJXzBfUENMSywgMjEsIDAsIDApLAorCUdBVEUo Q0xLX0dPVVRfU1BJMF9FWFRfQ0xLLCAiZ291dF9zcGkwX2lwY2xrIiwgIm1vdXRfcGVyaV9zcGkw X3VzZXIiLAorCSAgICAgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1NQSV8wX0VYVF9DTEssIDIxLCAw LCAwKSwKKwlHQVRFKENMS19HT1VUX1NQSTFfUENMSywgImdvdXRfc3BpMV9wY2xrIiwgIm1vdXRf cGVyaV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfU1BJXzFfUENMSywg MjEsIDAsIDApLAorCUdBVEUoQ0xLX0dPVVRfU1BJMV9FWFRfQ0xLLCAiZ291dF9zcGkxX2lwY2xr IiwgIm1vdXRfcGVyaV9zcGkxX3VzZXIiLAorCSAgICAgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1NQ SV8xX0VYVF9DTEssIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX1VBUlQwX0VYVF9VQ0xLLCAi Z291dF91YXJ0MF9leHRfdWNsayIsICJtb3V0X3BlcmlfdWFydDBfdXNlciIsCisJICAgICBDTEtf Q09OX0dBVF9HT1VUX1BFUklfVUFSVF8wX0VYVF9VQ0xLLCAyMSwgMCwgMCksCisJR0FURShDTEtf R09VVF9VQVJUMF9QQ0xLLCAiZ291dF91YXJ0MF9wY2xrIiwgIm1vdXRfcGVyaV9idXNfdXNlciIs CisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfVUFSVF8wX1BDTEssIDIxLCAwLCAwKSwKKwlH QVRFKENMS19HT1VUX1VBUlQxX0VYVF9VQ0xLLCAiZ291dF91YXJ0MV9leHRfdWNsayIsICJtb3V0 X3BlcmlfdWFydDFfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfVUFSVF8xX0VY VF9VQ0xLLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9VQVJUMV9QQ0xLLCAiZ291dF91YXJ0 MV9wY2xrIiwgIm1vdXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BF UklfVUFSVF8xX1BDTEssIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX1VBUlQyX0VYVF9VQ0xL LCAiZ291dF91YXJ0Ml9leHRfdWNsayIsICJtb3V0X3BlcmlfdWFydDJfdXNlciIsCisJICAgICBD TEtfQ09OX0dBVF9HT1VUX1BFUklfVUFSVF8yX0VYVF9VQ0xLLCAyMSwgMCwgMCksCisJR0FURShD TEtfR09VVF9VQVJUMl9QQ0xLLCAiZ291dF91YXJ0Ml9wY2xrIiwgIm1vdXRfcGVyaV9idXNfdXNl ciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfVUFSVF8yX1BDTEssIDIxLCAwLCAwKSwK KwlHQVRFKENMS19HT1VUX1VTSTBfUENMSywgImdvdXRfdXNpMF9wY2xrIiwgIm1vdXRfcGVyaV9i dXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfVVNJMF9QQ0xLLCAyMSwgMCwg MCksCisJR0FURShDTEtfR09VVF9VU0kwX1NDTEssICJnb3V0X3VzaTBfc2NsayIsICJtb3V0X3Bl cmlfdXNpMF91c2VyIiwKKwkgICAgIENMS19DT05fR0FUX0dPVVRfUEVSSV9VU0kwX1NDTEssIDIx LCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX1VTSTFfUENMSywgImdvdXRfdXNpMV9wY2xrIiwgIm1v dXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfVVNJMV9QQ0xL LCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9VU0kxX1NDTEssICJnb3V0X3VzaTFfc2NsayIs ICJtb3V0X3BlcmlfdXNpMV91c2VyIiwKKwkgICAgIENMS19DT05fR0FUX0dPVVRfUEVSSV9VU0kx X1NDTEssIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX1VTSTJfUENMSywgImdvdXRfdXNpMl9w Y2xrIiwgIm1vdXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklf VVNJMl9QQ0xLLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9VU0kyX1NDTEssICJnb3V0X3Vz aTJfc2NsayIsICJtb3V0X3BlcmlfdXNpMl91c2VyIiwKKwkgICAgIENMS19DT05fR0FUX0dPVVRf UEVSSV9VU0kyX1NDTEssIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX01DVF9QQ0xLLCAiZ291 dF9tY3RfcGNsayIsICJtb3V0X3BlcmlfYnVzX3VzZXIiLAorCSAgICAgQ0xLX0NPTl9HQVRfR09V VF9QRVJJX01DVF9QQ0xLLCAyMSwgMCwgMCksCisJR0FURShDTEtfR09VVF9TWVNSRUdfUEVSSV9Q Q0xLLCAiZ291dF9zeXNyZWdfcGVyaV9wY2xrIiwKKwkgICAgICJtb3V0X3BlcmlfYnVzX3VzZXIi LAorCSAgICAgQ0xLX0NPTl9HQVRfR09VVF9QRVJJX1NZU1JFR19QRVJJX1BDTEssIDIxLCAwLCAw KSwKKwlHQVRFKENMS19HT1VUX1dEVDBfUENMSywgImdvdXRfd2R0MF9wY2xrIiwgIm1vdXRfcGVy aV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfV0RUX0NMVVNURVIwX1BD TEssIDIxLCAwLCAwKSwKKwlHQVRFKENMS19HT1VUX1dEVDFfUENMSywgImdvdXRfd2R0MV9wY2xr IiwgIm1vdXRfcGVyaV9idXNfdXNlciIsCisJICAgICBDTEtfQ09OX0dBVF9HT1VUX1BFUklfV0RU X0NMVVNURVIxX1BDTEssIDIxLCAwLCAwKSwKK307CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgc2Ft c3VuZ19jbXVfaW5mbyBwZXJpX2NtdV9pbmZvIF9faW5pdGNvbnN0ID0geworCS5tdXhfY2xrcwkJ PSBwZXJpX211eF9jbGtzLAorCS5ucl9tdXhfY2xrcwkJPSBBUlJBWV9TSVpFKHBlcmlfbXV4X2Ns a3MpLAorCS5nYXRlX2Nsa3MJCT0gcGVyaV9nYXRlX2Nsa3MsCisJLm5yX2dhdGVfY2xrcwkJPSBB UlJBWV9TSVpFKHBlcmlfZ2F0ZV9jbGtzKSwKKwkubnJfY2xrX2lkcwkJPSBQRVJJX05SX0NMSywK KwkuY2xrX3JlZ3MJCT0gcGVyaV9jbGtfcmVncywKKwkubnJfY2xrX3JlZ3MJCT0gQVJSQVlfU0la RShwZXJpX2Nsa19yZWdzKSwKKwkuY2xrX25hbWUJCT0gImRvdXRfcGVyaV9idXMiLAorfTsKKwor c3RhdGljIHZvaWQgX19pbml0IGV4eW5vczc4ODVfY211X3BlcmlfaW5pdChzdHJ1Y3QgZGV2aWNl X25vZGUgKm5wKQoreworCWV4eW5vc19hcm02NF9yZWdpc3Rlcl9jbXUoTlVMTCwgbnAsICZwZXJp X2NtdV9pbmZvKTsKK30KKworLyogUmVnaXN0ZXIgQ01VX1BFUkkgZWFybHksIGFzIGl0J3MgbmVl ZGVkIGZvciBNQ1QgdGltZXIgKi8KK0NMS19PRl9ERUNMQVJFKGV4eW5vczc4ODVfY211X3Blcmks ICJzYW1zdW5nLGV4eW5vczc4ODUtY211LXBlcmkiLAorCSAgICAgICBleHlub3M3ODg1X2NtdV9w ZXJpX2luaXQpOworCisvKiAtLS0tIENNVV9DT1JFIC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLSAqLworCisvKiBSZWdpc3RlciBPZmZz ZXQgZGVmaW5pdGlvbnMgZm9yIENNVV9DT1JFICgweDEyMDAwMDAwKSAqLworI2RlZmluZSBQTExf Q09OMF9NVVhfQ0xLQ01VX0NPUkVfQlVTX1VTRVIJMHgwMTAwCisjZGVmaW5lIFBMTF9DT04wX01V WF9DTEtDTVVfQ09SRV9DQ0lfVVNFUgkweDAxMjAKKyNkZWZpbmUgUExMX0NPTjBfTVVYX0NMS0NN VV9DT1JFX0czRF9VU0VSCTB4MDE0MAorI2RlZmluZSBDTEtfQ09OX01VWF9NVVhfQ0xLX0NPUkVf R0lDCQkweDEwMDAKKyNkZWZpbmUgQ0xLX0NPTl9ESVZfRElWX0NMS19DT1JFX0JVU1AJCTB4MTgw MAorI2RlZmluZSBDTEtfQ09OX0dBVF9HT1VUX0NPUkVfQ0NJXzU1MF9BQ0xLCTB4MjA1NAorI2Rl ZmluZSBDTEtfQ09OX0dBVF9HT1VUX0NPUkVfR0lDNDAwX0NMSwkweDIwNTgKKworc3RhdGljIGNv bnN0IHVuc2lnbmVkIGxvbmcgY29yZV9jbGtfcmVnc1tdIF9faW5pdGNvbnN0ID0geworCVBMTF9D T04wX01VWF9DTEtDTVVfQ09SRV9CVVNfVVNFUiwKKwlQTExfQ09OMF9NVVhfQ0xLQ01VX0NPUkVf Q0NJX1VTRVIsCisJUExMX0NPTjBfTVVYX0NMS0NNVV9DT1JFX0czRF9VU0VSLAorCUNMS19DT05f TVVYX01VWF9DTEtfQ09SRV9HSUMsCisJQ0xLX0NPTl9ESVZfRElWX0NMS19DT1JFX0JVU1AsCisJ Q0xLX0NPTl9HQVRfR09VVF9DT1JFX0NDSV81NTBfQUNMSywKKwlDTEtfQ09OX0dBVF9HT1VUX0NP UkVfR0lDNDAwX0NMSywKK307CisKKy8qIExpc3Qgb2YgcGFyZW50IGNsb2NrcyBmb3IgTXV4ZXMg aW4gQ01VX0NPUkUgKi8KK1BOQU1FKG1vdXRfY29yZV9idXNfdXNlcl9wKQkJPSB7ICJvc2NjbGsi LCAiZG91dF9jb3JlX2J1cyIgfTsKK1BOQU1FKG1vdXRfY29yZV9jY2lfdXNlcl9wKQkJPSB7ICJv c2NjbGsiLCAiZG91dF9jb3JlX2NjaSIgfTsKK1BOQU1FKG1vdXRfY29yZV9nM2RfdXNlcl9wKQkJ PSB7ICJvc2NjbGsiLCAiZG91dF9jb3JlX2czZCIgfTsKK1BOQU1FKG1vdXRfY29yZV9naWNfcCkJ CQk9IHsgImRvdXRfY29yZV9idXNwIiwgIm9zY2NsayIgfTsKKworc3RhdGljIGNvbnN0IHN0cnVj dCBzYW1zdW5nX211eF9jbG9jayBjb3JlX211eF9jbGtzW10gX19pbml0Y29uc3QgPSB7CisJTVVY KENMS19NT1VUX0NPUkVfQlVTX1VTRVIsICJtb3V0X2NvcmVfYnVzX3VzZXIiLCBtb3V0X2NvcmVf YnVzX3VzZXJfcCwKKwkgICAgUExMX0NPTjBfTVVYX0NMS0NNVV9DT1JFX0JVU19VU0VSLCA0LCAx KSwKKwlNVVgoQ0xLX01PVVRfQ09SRV9DQ0lfVVNFUiwgIm1vdXRfY29yZV9jY2lfdXNlciIsIG1v dXRfY29yZV9jY2lfdXNlcl9wLAorCSAgICBQTExfQ09OMF9NVVhfQ0xLQ01VX0NPUkVfQ0NJX1VT RVIsIDQsIDEpLAorCU1VWChDTEtfTU9VVF9DT1JFX0czRF9VU0VSLCAibW91dF9jb3JlX2czZF91 c2VyIiwgbW91dF9jb3JlX2czZF91c2VyX3AsCisJICAgIFBMTF9DT04wX01VWF9DTEtDTVVfQ09S RV9HM0RfVVNFUiwgNCwgMSksCisJTVVYKENMS19NT1VUX0NPUkVfR0lDLCAibW91dF9jb3JlX2dp YyIsIG1vdXRfY29yZV9naWNfcCwKKwkgICAgQ0xLX0NPTl9NVVhfTVVYX0NMS19DT1JFX0dJQywg MCwgMSksCit9OworCitzdGF0aWMgY29uc3Qgc3RydWN0IHNhbXN1bmdfZGl2X2Nsb2NrIGNvcmVf ZGl2X2Nsa3NbXSBfX2luaXRjb25zdCA9IHsKKwlESVYoQ0xLX0RPVVRfQ09SRV9CVVNQLCAiZG91 dF9jb3JlX2J1c3AiLCAibW91dF9jb3JlX2J1c191c2VyIiwKKwkgICAgQ0xLX0NPTl9ESVZfRElW X0NMS19DT1JFX0JVU1AsIDAsIDIpLAorfTsKKworc3RhdGljIGNvbnN0IHN0cnVjdCBzYW1zdW5n X2dhdGVfY2xvY2sgY29yZV9nYXRlX2Nsa3NbXSBfX2luaXRjb25zdCA9IHsKKwkvKiBDQ0kgKGlu dGVyY29ubmVjdCkgY2xvY2sgbXVzdCBiZSBhbHdheXMgcnVubmluZyAqLworCUdBVEUoQ0xLX0dP VVRfQ0NJX0FDTEssICJnb3V0X2NjaV9hY2xrIiwgIm1vdXRfY29yZV9jY2lfdXNlciIsCisJICAg ICBDTEtfQ09OX0dBVF9HT1VUX0NPUkVfQ0NJXzU1MF9BQ0xLLCAyMSwgQ0xLX0lTX0NSSVRJQ0FM LCAwKSwKKwkvKiBHSUMgKGludGVycnVwdCBjb250cm9sbGVyKSBjbG9jayBtdXN0IGJlIGFsd2F5 cyBydW5uaW5nICovCisJR0FURShDTEtfR09VVF9HSUM0MDBfQ0xLLCAiZ291dF9naWM0MDBfY2xr IiwgIm1vdXRfY29yZV9naWMiLAorCSAgICAgQ0xLX0NPTl9HQVRfR09VVF9DT1JFX0dJQzQwMF9D TEssIDIxLCBDTEtfSVNfQ1JJVElDQUwsIDApLAorfTsKKworc3RhdGljIGNvbnN0IHN0cnVjdCBz YW1zdW5nX2NtdV9pbmZvIGNvcmVfY211X2luZm8gX19pbml0Y29uc3QgPSB7CisJLm11eF9jbGtz CQk9IGNvcmVfbXV4X2Nsa3MsCisJLm5yX211eF9jbGtzCQk9IEFSUkFZX1NJWkUoY29yZV9tdXhf Y2xrcyksCisJLmRpdl9jbGtzCQk9IGNvcmVfZGl2X2Nsa3MsCisJLm5yX2Rpdl9jbGtzCQk9IEFS UkFZX1NJWkUoY29yZV9kaXZfY2xrcyksCisJLmdhdGVfY2xrcwkJPSBjb3JlX2dhdGVfY2xrcywK KwkubnJfZ2F0ZV9jbGtzCQk9IEFSUkFZX1NJWkUoY29yZV9nYXRlX2Nsa3MpLAorCS5ucl9jbGtf aWRzCQk9IENPUkVfTlJfQ0xLLAorCS5jbGtfcmVncwkJPSBjb3JlX2Nsa19yZWdzLAorCS5ucl9j bGtfcmVncwkJPSBBUlJBWV9TSVpFKGNvcmVfY2xrX3JlZ3MpLAorCS5jbGtfbmFtZQkJPSAiZG91 dF9jb3JlX2J1cyIsCit9OworCisvKiAtLS0tIHBsYXRmb3JtX2RyaXZlciAtLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLSAqLworCitzdGF0aWMgaW50 IF9faW5pdCBleHlub3M3ODg1X2NtdV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2 KQoreworCWNvbnN0IHN0cnVjdCBzYW1zdW5nX2NtdV9pbmZvICppbmZvOworCXN0cnVjdCBkZXZp Y2UgKmRldiA9ICZwZGV2LT5kZXY7CisKKwlpbmZvID0gb2ZfZGV2aWNlX2dldF9tYXRjaF9kYXRh KGRldik7CisJZXh5bm9zX2FybTY0X3JlZ2lzdGVyX2NtdShkZXYsIGRldi0+b2Zfbm9kZSwgaW5m byk7CisKKwlyZXR1cm4gMDsKK30KKworc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQg ZXh5bm9zNzg4NV9jbXVfb2ZfbWF0Y2hbXSA9IHsKKwl7CisJCS5jb21wYXRpYmxlID0gInNhbXN1 bmcsZXh5bm9zNzg4NS1jbXUtY29yZSIsCisJCS5kYXRhID0gJmNvcmVfY211X2luZm8sCisJfSwg eworCX0sCit9OworCitzdGF0aWMgc3RydWN0IHBsYXRmb3JtX2RyaXZlciBleHlub3M3ODg1X2Nt dV9kcml2ZXIgX19yZWZkYXRhID0geworCS5kcml2ZXIJPSB7CisJCS5uYW1lID0gImV4eW5vczc4 ODUtY211IiwKKwkJLm9mX21hdGNoX3RhYmxlID0gZXh5bm9zNzg4NV9jbXVfb2ZfbWF0Y2gsCisJ CS5zdXBwcmVzc19iaW5kX2F0dHJzID0gdHJ1ZSwKKwl9LAorCS5wcm9iZSA9IGV4eW5vczc4ODVf Y211X3Byb2JlLAorfTsKKworc3RhdGljIGludCBfX2luaXQgZXh5bm9zNzg4NV9jbXVfaW5pdCh2 b2lkKQoreworCXJldHVybiBwbGF0Zm9ybV9kcml2ZXJfcmVnaXN0ZXIoJmV4eW5vczc4ODVfY211 X2RyaXZlcik7Cit9Citjb3JlX2luaXRjYWxsKGV4eW5vczc4ODVfY211X2luaXQpOwotLSAKMi4z NC4xCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlu dXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRl YWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgt YXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD1A4C4332F for ; Mon, 6 Dec 2021 15:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442924AbhLFP4Y (ORCPT ); Mon, 6 Dec 2021 10:56:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390810AbhLFPmv (ORCPT ); Mon, 6 Dec 2021 10:42:51 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7E4AC08E893; Mon, 6 Dec 2021 07:32:45 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id x15so44806482edv.1; Mon, 06 Dec 2021 07:32:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OkDSlzNyccGJm3fGJWjOCT3PITcK8ErGOmoqjaGOv4E=; b=bOfR2lQZ+1DUDnfucrRZE39u3pjOGh4lYttVdY5SAscmopfpo5gQLQ7jnrEEbsuDBE IQShoQmRcvf1WOoPA0LDktYSv12E3jFyuCKV3RYuXvrsAnv4dOymh/nHjVfT2cGAHdQF upZ/CD86kocKjJ8ORSJOEv9GYG0gxuaXbDSG9VJL8R8KmnShHo7vf9w5DLiw6BFySiRq of12NY6tQCOGxdU6P0aQauIrFWJtAZRE6Ay2iTv6sGjez9oxZJoyPfsv+KvhGnlHo9+m SpjhbQ2nol0HkxSpWA14eKLyIOhUJZRPqm5gXdVo8uKuGnILHGKdGnb3mYVLlHSA+vLz y9Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OkDSlzNyccGJm3fGJWjOCT3PITcK8ErGOmoqjaGOv4E=; b=WpYvCcKNshX+la4wYEngf86i7BgVaZkYK5dDCDGRLtnQ1rdjToX5rHdDKTy12yF4ob wCyvJl1LkdU5X+C/ZBzR+Caluh6JytNc9x0o/XSE3vZfdxGyiRJekG8lpfSa92KlNn6U fRNQ3ozZbNTsPDDVQixnXSKCcmO2tAEblZ8ZtWi6JUOj1p+2z/oqQKgmn+YEQqA45i9F y664v8Ivp1RgMS/4C0dcAvBl+AsXEkNi/YrTkCoAYziEcTs1cm93KofszVUeA50TM9Ox v1i4zurJLTWHRHq2vFMnVGDUNzHawzZty8uNnXCJs7y9f/FbREVo4hFNBJD5HibHX08X jRJg== X-Gm-Message-State: AOAM530pyAufomeD+q8j/8bahlVBWvD6f4DBAKtknmBkf+6ORZGxsIKF Gv5sxzkyVT4C4pT/p8WZomU= X-Google-Smtp-Source: ABdhPJyLVMVVJvM4K20sd/2CGbRiBK763KKH1GUkq2okc6AfBkPHUlZobyR0rCpByu0SQLHzuJAChA== X-Received: by 2002:a50:a6ca:: with SMTP id f10mr55015973edc.81.1638804764255; Mon, 06 Dec 2021 07:32:44 -0800 (PST) Received: from localhost.localdomain ([2a02:ab88:368f:2080:eab:126a:947d:3008]) by smtp.googlemail.com with ESMTPSA id d19sm7364688edt.34.2021.12.06.07.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 07:32:43 -0800 (PST) From: David Virag Cc: Sam Protsenko , David Virag , Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 6/7] clk: samsung: Add initial Exynos7885 clock driver Date: Mon, 6 Dec 2021 16:31:20 +0100 Message-Id: <20211206153124.427102-7-virag.david003@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211206153124.427102-1-virag.david003@gmail.com> References: <20211206153124.427102-1-virag.david003@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is an initial implementation adding basic clocks, such as UART, USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which was made by Sam Protsenko, thus the copyright and author lines were kept. Bus clocks are enabled by default as well to avoid hangs while trying to access CMU registers. Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of CMU_CORE, and most of CMU_PERI is implemented as of now. Signed-off-by: David Virag --- Changes in v2: - Use shared code between Exynos850 and 7885 clock drivers - As the code that was from the Exynos850 clock driver was moved to clk-exynos-arm64.c and what remains is mostly SoC specific data, move the Linaro copyright and Sam Protsenko author lines there. Changes in v3: - Nothing Changes in v4: - Fixed missing headers drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos7885.c | 597 +++++++++++++++++++++++++++ 2 files changed, 598 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos7885.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 901e6333c5f0..0df74916a895 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c new file mode 100644 index 000000000000..a7b106302706 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Dávid Virág + * Author: Dávid Virág + * + * Common Clock Framework support for Exynos7885 SoC. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* ---- CMU_TOP ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_TOP (0x12060000) */ +#define PLL_LOCKTIME_PLL_SHARED0 0x0000 +#define PLL_LOCKTIME_PLL_SHARED1 0x0004 +#define PLL_CON0_PLL_SHARED0 0x0100 +#define PLL_CON0_PLL_SHARED1 0x0120 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c +#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c +#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078 +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c +#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820 +#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824 +#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874 +#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878 +#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c +#define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880 +#define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884 +#define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888 +#define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c +#define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890 +#define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894 +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0 +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4 +#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8 +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0 +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4 +#define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c +#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c +#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c +#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098 + +static const unsigned long top_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_CON0_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, + CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, + CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, + CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, + CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, + CLK_CON_DIV_CLKCMU_CORE_BUS, + CLK_CON_DIV_CLKCMU_CORE_CCI, + CLK_CON_DIV_CLKCMU_CORE_G3D, + CLK_CON_DIV_CLKCMU_PERI_BUS, + CLK_CON_DIV_CLKCMU_PERI_SPI0, + CLK_CON_DIV_CLKCMU_PERI_SPI1, + CLK_CON_DIV_CLKCMU_PERI_UART0, + CLK_CON_DIV_CLKCMU_PERI_UART1, + CLK_CON_DIV_CLKCMU_PERI_UART2, + CLK_CON_DIV_CLKCMU_PERI_USI0, + CLK_CON_DIV_CLKCMU_PERI_USI1, + CLK_CON_DIV_CLKCMU_PERI_USI2, + CLK_CON_DIV_PLL_SHARED0_DIV2, + CLK_CON_DIV_PLL_SHARED0_DIV3, + CLK_CON_DIV_PLL_SHARED0_DIV4, + CLK_CON_DIV_PLL_SHARED0_DIV5, + CLK_CON_DIV_PLL_SHARED1_DIV2, + CLK_CON_DIV_PLL_SHARED1_DIV3, + CLK_CON_DIV_PLL_SHARED1_DIV4, + CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, + CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, + CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, + CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, + CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, + CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, + CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, +}; + +static const struct samsung_pll_clock top_pll_clks[] __initconst = { + PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, + NULL), + PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, + NULL), +}; + +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ +PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared0_div3" }; +PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared0_div3" }; +PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared0_div3" }; + +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ +PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; +PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" }; +PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" }; +PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" }; +PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" }; +PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" }; +PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" }; +PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" }; +PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" }; + +static const struct samsung_mux_clock top_mux_clks[] __initconst = { + /* CORE */ + MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), + MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), + MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2), + + /* PERI */ + MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), + MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1), + MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1), + MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1), + MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1), + MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1), + MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1), + MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1), + MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1), +}; + +static const struct samsung_div_clock top_div_clks[] __initconst = { + /* TOP */ + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll", + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll", + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll", + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), + + /* CORE */ + DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3), + DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", + CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3), + DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d", + CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3), + + /* PERI */ + DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", + CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), + DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0", + CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6), + DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1", + CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6), + DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0", + CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4), + DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1", + CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4), + DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2", + CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4), + DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0", + CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4), + DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1", + CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4), + DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2", + CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4), +}; + +static const struct samsung_gate_clock top_gate_clks[] __initconst = { + /* CORE */ + GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), + GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), + GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d", + CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0), + + /* PERI */ + GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), + GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0", + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0), + GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1", + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0), + GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0", + CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0), + GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1", + CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0), + GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2", + CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0), + GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0", + CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0), + GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1", + CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0), + GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2", + CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0), +}; + +static const struct samsung_cmu_info top_cmu_info __initconst = { + .pll_clks = top_pll_clks, + .nr_pll_clks = ARRAY_SIZE(top_pll_clks), + .mux_clks = top_mux_clks, + .nr_mux_clks = ARRAY_SIZE(top_mux_clks), + .div_clks = top_div_clks, + .nr_div_clks = ARRAY_SIZE(top_div_clks), + .gate_clks = top_gate_clks, + .nr_gate_clks = ARRAY_SIZE(top_gate_clks), + .nr_clk_ids = TOP_NR_CLK, + .clk_regs = top_clk_regs, + .nr_clk_regs = ARRAY_SIZE(top_clk_regs), +}; + +static void __init exynos7885_cmu_top_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); +} + +/* Register CMU_TOP early, as it's a dependency for other early domains */ +CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top", + exynos7885_cmu_top_init); + +/* ---- CMU_PERI ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_PERI (0x10010000) */ +#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100 +#define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120 +#define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140 +#define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160 +#define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180 +#define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0 +#define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0 +#define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0 +#define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200 +#define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024 +#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 +#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c +#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030 +#define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034 +#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038 +#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c +#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040 +#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044 +#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048 +#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c +#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054 +#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058 +#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c +#define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060 +#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064 +#define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068 +#define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c +#define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070 +#define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074 +#define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078 +#define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c +#define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080 +#define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084 +#define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088 +#define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c +#define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090 +#define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094 +#define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098 +#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0 +#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0 +#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4 +#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8 + +static const unsigned long peri_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, + PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, + PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, + PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, + PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, + PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, + PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, + PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, + CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, + CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, + CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, + CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, + CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, + CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, + CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, + CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, + CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, + CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, + CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, + CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, + CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, + CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, + CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, + CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, + CLK_CON_GAT_GOUT_PERI_USI0_PCLK, + CLK_CON_GAT_GOUT_PERI_USI0_SCLK, + CLK_CON_GAT_GOUT_PERI_USI1_PCLK, + CLK_CON_GAT_GOUT_PERI_USI1_SCLK, + CLK_CON_GAT_GOUT_PERI_USI2_PCLK, + CLK_CON_GAT_GOUT_PERI_USI2_SCLK, + CLK_CON_GAT_GOUT_PERI_MCT_PCLK, + CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, +}; + +/* List of parent clocks for Muxes in CMU_PERI */ +PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; +PNAME(mout_peri_spi0_user_p) = { "oscclk", "dout_peri_spi0" }; +PNAME(mout_peri_spi1_user_p) = { "oscclk", "dout_peri_spi1" }; +PNAME(mout_peri_uart0_user_p) = { "oscclk", "dout_peri_uart0" }; +PNAME(mout_peri_uart1_user_p) = { "oscclk", "dout_peri_uart1" }; +PNAME(mout_peri_uart2_user_p) = { "oscclk", "dout_peri_uart2" }; +PNAME(mout_peri_usi0_user_p) = { "oscclk", "dout_peri_usi0" }; +PNAME(mout_peri_usi1_user_p) = { "oscclk", "dout_peri_usi1" }; +PNAME(mout_peri_usi2_user_p) = { "oscclk", "dout_peri_usi2" }; + +static const struct samsung_mux_clock peri_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p, + PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1), + MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p, + PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1), + MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user", + mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1), + MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user", + mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1), + MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user", + mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1), + MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user", + mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1), + MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user", + mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1), + MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user", + mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1), +}; + +static const struct samsung_gate_clock peri_gate_clks[] __initconst = { + /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ + GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk", + "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), + GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), + GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), + GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), + GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0), + GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk", + "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user", + CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0), + GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user", + CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0), + GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user", + CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0), + GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0), + GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user", + CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0), + GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0), + GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user", + CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0), + GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0), + GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0), + GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user", + CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0), + GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0), + GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user", + CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0), + GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0), + GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user", + CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0), + GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", + "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), + GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0), + GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info peri_cmu_info __initconst = { + .mux_clks = peri_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), + .gate_clks = peri_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), + .nr_clk_ids = PERI_NR_CLK, + .clk_regs = peri_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), + .clk_name = "dout_peri_bus", +}; + +static void __init exynos7885_cmu_peri_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); +} + +/* Register CMU_PERI early, as it's needed for MCT timer */ +CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri", + exynos7885_cmu_peri_init); + +/* ---- CMU_CORE ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_CORE (0x12000000) */ +#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 +#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 +#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 +#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 +#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 +#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054 +#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058 + +static const unsigned long core_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, + PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, + PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, + CLK_CON_MUX_MUX_CLK_CORE_GIC, + CLK_CON_DIV_DIV_CLK_CORE_BUSP, + CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, + CLK_CON_GAT_GOUT_CORE_GIC400_CLK, +}; + +/* List of parent clocks for Muxes in CMU_CORE */ +PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; +PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; +PNAME(mout_core_g3d_user_p) = { "oscclk", "dout_core_g3d" }; +PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" }; + +static const struct samsung_mux_clock core_mux_clks[] __initconst = { + MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), + MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p, + PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), + MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p, + PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1), + MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p, + CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), +}; + +static const struct samsung_div_clock core_div_clks[] __initconst = { + DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", + CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), +}; + +static const struct samsung_gate_clock core_gate_clks[] __initconst = { + /* CCI (interconnect) clock must be always running */ + GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user", + CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), + /* GIC (interrupt controller) clock must be always running */ + GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic", + CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0), +}; + +static const struct samsung_cmu_info core_cmu_info __initconst = { + .mux_clks = core_mux_clks, + .nr_mux_clks = ARRAY_SIZE(core_mux_clks), + .div_clks = core_div_clks, + .nr_div_clks = ARRAY_SIZE(core_div_clks), + .gate_clks = core_gate_clks, + .nr_gate_clks = ARRAY_SIZE(core_gate_clks), + .nr_clk_ids = CORE_NR_CLK, + .clk_regs = core_clk_regs, + .nr_clk_regs = ARRAY_SIZE(core_clk_regs), + .clk_name = "dout_core_bus", +}; + +/* ---- platform_driver ----------------------------------------------------- */ + +static int __init exynos7885_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id exynos7885_cmu_of_match[] = { + { + .compatible = "samsung,exynos7885-cmu-core", + .data = &core_cmu_info, + }, { + }, +}; + +static struct platform_driver exynos7885_cmu_driver __refdata = { + .driver = { + .name = "exynos7885-cmu", + .of_match_table = exynos7885_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos7885_cmu_probe, +}; + +static int __init exynos7885_cmu_init(void) +{ + return platform_driver_register(&exynos7885_cmu_driver); +} +core_initcall(exynos7885_cmu_init); -- 2.34.1