From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF692C433EF for ; Thu, 9 Dec 2021 19:04:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230165AbhLITIR (ORCPT ); Thu, 9 Dec 2021 14:08:17 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:11178 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230112AbhLITIQ (ORCPT ); Thu, 9 Dec 2021 14:08:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639076683; x=1670612683; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=iz/wXRu33P1x1tyycLT6awGPeINKLjvLTr6sCfJHrCg=; b=IPWA+2zqNKJ4zYVdBLbnJacT8/AY/Dh0waqVKMSfAX6y8Jwk69Uqd1Kr oFSEPSO/AXstmQWHRw6DpfgoDZVVCfBjHscwmoUAmNq45EvIh53Ajr8Ab Y/onXxDtxjrIyUUCRfuzfLEykP+MSIm8h5TKJNOuUlDZOYjriuKA9OJ3x y0G2I+bIoq9jjzyPQIbz/SfLnAu/wrIu2Af0x5sVg59ZjVNwC2lv5r0g/ OruPMoKN+Qjt8vv0PPsr9wz2/IikeESCJr6Zqn/p4VDgei4yZ+Hxi0sA2 8CSFNaTapRYIOs+QJGq1YB4rbZfo4ZGS/FSD556l4YEnTUDnCazWWH3mx Q==; IronPort-SDR: Dr27Q0Aqr1naB51eowebzSme6O07Q5/fWEyx9gJw4gKlCCRfPyHSK8cZUwzVTc+JOK3dFqT4Jt H+ZXjzFzbjqOIbxsVNvoemWtH/hlIjCu6pElXDVRugVZoOLDSPMkSTDbfiReCBuSB8E6pcIgSy a/Div93VlCAWrKLOAKuq438zLm0xUIsW9/uU2Ix1O36VWpmXP0lZO4QIZtSwXebRG/NMAKtW87 Nps+kX1A76FDP7BvKPYTiP0+gjs9uN4fUHCv3iHo+QK3vH1w7JBO94p8RtARELQusdeVe9MLrT iPnzGJjcm+rR/ZfyxbeIliwb X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="141897012" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Dec 2021 12:04:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 9 Dec 2021 12:04:42 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Dec 2021 12:04:39 -0700 From: Tudor Ambarus To: , CC: , , , , , , , , Tudor Ambarus Subject: [PATCH v2 1/2] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Date: Thu, 9 Dec 2021 21:04:35 +0200 Message-ID: <20211209190436.401946-1-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Soft Reset and Rescue Sequence Support is defined in BFPT_DWORD(16) starting with JESD216A. The first version of SFDP, JESD216 (April 2011), defines just the first 9 BFPT DWORDS, thus it does not contain information about the Software Reset and Rescue Support. Since this support can not be discovered by parsing the first SFDP version, introduce a flash_info fixup_flag that will be used either by flashes that define JESD216 (April 2011) or by flashes that do not define SFDP at all. In case a flash defines BFPT_DWORD(16) but with wrong values, one should instead use a post_bfpt() hook and set SNOR_F_SOFT_RESET. Signed-off-by: Tudor Ambarus --- v2: no changes drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 2e21d5ac0e2d..32d80fdaa2a2 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2699,6 +2699,9 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; + + if (fixup_flags & SPI_NOR_SOFT_RESET) + nor->flags |= SNOR_F_SOFT_RESET; } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2afb610853a9..70c6bb7f5f04 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -373,6 +373,8 @@ struct spi_nor_fixups { * memory size above 128Mib. * SPI_NOR_IO_MODE_EN_VOLATILE: flash enables the best available I/O mode * via a volatile bit. + * SPI_NOR_SOFT_RESET: flash supports software reset enable, reset + * sequence. * @mfr_flags: manufacturer private flags. Used in the manufacturer fixup * hooks to differentiate support between flashes of the same * manufacturer. @@ -416,6 +418,7 @@ struct flash_info { u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0) #define SPI_NOR_IO_MODE_EN_VOLATILE BIT(1) +#define SPI_NOR_SOFT_RESET BIT(2) u8 mfr_flags; -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FF12C433F5 for ; Thu, 9 Dec 2021 19:05:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=XWR5N8riOEUWKXwT/I+MGPI6O4EvOCDP2hddQiqjExw=; b=EMLO8quQQWGWSj KE0dqNETvpZ5Vhj0eQa9/au62Tuv10uQliIMhYvO4tX3kUGid8tdoPqdaR4q9quXj+98KvnN6xj0f aivITf3hJXwml3iaXk5VJh72YRTxtAT9TQsiL5sGCNhL/zWGFq5dzd1MuU6I+UQbKwXcAeuW/HrMU qo/i13hN8DHmMSB/QHxCk68Xa36ddzfTNDnJTVtpexbPIjz0LtCdMXNha/H1giReMMNXJnXdFRViI d6hnoh7W5TR7Z+I2wMMA2kpyCTovEau5VuIu9N+S+Ds7QGSXdNraRmoOQDVkEIOLV+ntCOP3GhCqa xpHpYxDwp/0l/RwDRCYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvOim-00HJes-MN; Thu, 09 Dec 2021 19:04:48 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvOij-00HJde-8R for linux-mtd@lists.infradead.org; Thu, 09 Dec 2021 19:04:46 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639076685; x=1670612685; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=iz/wXRu33P1x1tyycLT6awGPeINKLjvLTr6sCfJHrCg=; b=ZXbtv7z2isUMUHIvdVvhfbiST5FIezFT6PdV/CSZjoQaDppeVV1Um7Ek tQnNH0Oh93/Bz7snh3+BUtfPL/LxOo3/eEKdx3hz38Dk2fsnWWMaqJG81 Terk5Ocow64CTDoKVmHjBUT2a8pVADUtOaoOkOQq9tPlaxcEL0O+psuOm GSjasd49f8lq2ReZPi+JeO3fgTjJqI7uCv3LPVTVhk7XXsKcGeNSNulPD Kjt8V0p0OgfrIa2tmkwocNZKBGEAmEKVzP7yrbcZqbRsXMCHZ0W7JvMyX QUdblCTQrpV2Lm2kYEx/3hUzOSPWPQI4UkP3WPzT3WcWcuMp7jjFSnNH3 w==; IronPort-SDR: Dr27Q0Aqr1naB51eowebzSme6O07Q5/fWEyx9gJw4gKlCCRfPyHSK8cZUwzVTc+JOK3dFqT4Jt H+ZXjzFzbjqOIbxsVNvoemWtH/hlIjCu6pElXDVRugVZoOLDSPMkSTDbfiReCBuSB8E6pcIgSy a/Div93VlCAWrKLOAKuq438zLm0xUIsW9/uU2Ix1O36VWpmXP0lZO4QIZtSwXebRG/NMAKtW87 Nps+kX1A76FDP7BvKPYTiP0+gjs9uN4fUHCv3iHo+QK3vH1w7JBO94p8RtARELQusdeVe9MLrT iPnzGJjcm+rR/ZfyxbeIliwb X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="141897012" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Dec 2021 12:04:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 9 Dec 2021 12:04:42 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Dec 2021 12:04:39 -0700 From: Tudor Ambarus To: , CC: , , , , , , , , Tudor Ambarus Subject: [PATCH v2 1/2] mtd: spi-nor: core: Introduce SPI_NOR_SOFT_RESET flash_info fixup_flag Date: Thu, 9 Dec 2021 21:04:35 +0200 Message-ID: <20211209190436.401946-1-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211209_110445_444134_8B900AA6 X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org The Soft Reset and Rescue Sequence Support is defined in BFPT_DWORD(16) starting with JESD216A. The first version of SFDP, JESD216 (April 2011), defines just the first 9 BFPT DWORDS, thus it does not contain information about the Software Reset and Rescue Support. Since this support can not be discovered by parsing the first SFDP version, introduce a flash_info fixup_flag that will be used either by flashes that define JESD216 (April 2011) or by flashes that do not define SFDP at all. In case a flash defines BFPT_DWORD(16) but with wrong values, one should instead use a post_bfpt() hook and set SNOR_F_SOFT_RESET. Signed-off-by: Tudor Ambarus --- v2: no changes drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 2e21d5ac0e2d..32d80fdaa2a2 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2699,6 +2699,9 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE) nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; + + if (fixup_flags & SPI_NOR_SOFT_RESET) + nor->flags |= SNOR_F_SOFT_RESET; } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2afb610853a9..70c6bb7f5f04 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -373,6 +373,8 @@ struct spi_nor_fixups { * memory size above 128Mib. * SPI_NOR_IO_MODE_EN_VOLATILE: flash enables the best available I/O mode * via a volatile bit. + * SPI_NOR_SOFT_RESET: flash supports software reset enable, reset + * sequence. * @mfr_flags: manufacturer private flags. Used in the manufacturer fixup * hooks to differentiate support between flashes of the same * manufacturer. @@ -416,6 +418,7 @@ struct flash_info { u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0) #define SPI_NOR_IO_MODE_EN_VOLATILE BIT(1) +#define SPI_NOR_SOFT_RESET BIT(2) u8 mfr_flags; -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/