From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BBC6C433F5 for ; Sun, 12 Dec 2021 11:23:46 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9245383731; Sun, 12 Dec 2021 12:23:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="m7wXolMD"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3B1A983736; Sun, 12 Dec 2021 12:23:41 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 694EA8373B for ; Sun, 12 Dec 2021 12:23:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E46FAB80CA7; Sun, 12 Dec 2021 11:23:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F0D8C341C6; Sun, 12 Dec 2021 11:23:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639308215; bh=z9a2CWStKEtf0BF6Dl+EyiXR3d9xqZgofOd7I/v0KT8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=m7wXolMDHd3qwpHKNF47XMj5SqVgOrVsDOPbuixc2xdHHiWH1uKC3t2dhwofFRyGX Gazn3VZw3srIw0gTS35XU98eA0lIoJb3hSMAzV1wML5JnZFQLHzxw0tMUQhE6DNeyK RMIhiZ0vCQjJB0PfL/dbaJh9xRmus2uOKsdv93z0YSaC4zjrcrjWy/VbRSuY+h4Fmt st/VvXMjiQ3znfO67ieTsLQI4cr9dcnGY/P9QyGPV7Yphrrg+HfxhkFo44gR+UVKlK da7MoFTW5xQpcCrtUt8Cm30A5H1TUZMPGH1cQLDEZ47KJO+reEzrUKTxn9so6E7YW2 nHz3mMG2yOFZQ== Received: by pali.im (Postfix) id 80C2080E; Sun, 12 Dec 2021 12:23:32 +0100 (CET) Date: Sun, 12 Dec 2021 12:23:32 +0100 From: Pali =?utf-8?B?Um9ow6Fy?= To: Stefan Roese Cc: u-boot@lists.denx.de, Marek =?utf-8?B?QmVow7pu?= , Marek =?utf-8?B?QmVow7pu?= Subject: Re: [PATCH u-boot-marvell 00/10] PCI mvebu and aardvark changes Message-ID: <20211212112332.3nuihwnkh736emog@pali> References: <20211111153549.29111-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211111153549.29111-1-kabel@kernel.org> User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Thursday 11 November 2021 16:35:39 Marek Behún wrote: > From: Marek Behún > > Hello Stefan, > > we have some more fixes for PCI (mvebu and aardvark), and one patch > for Turris MOX board code. > > Marek Hello Stefan, patches 1, 2 and 7 still needs some modifications. But other remaining patches should be OK. Would you merge remaining patches? And then we can focus on issues with link initialization. > Marek Behún (2): > pci: pci_mvebu, pci_aardvark: Fix size of configuration cache > arm: mvebu: turris_mox: Remove extra newline after module topology > > Pali Rohár (8): > pci: pci_mvebu: Wait 100ms for Link Up in mvebu_pcie_probe() > arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c > pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup > pci: pci_mvebu: Replace MBUS_PCI_*_SIZE by resource_size() > pci: pci_mvebu: Do not allow setting ROM BAR on PCI Bridge > pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus > mapping > pci: pci_mvebu: Remove unused DECLARE_GLOBAL_DATA_PTR > arm: a37xx: pci: Do not allow setting ROM BAR on PCI Bridge > > arch/arm/mach-mvebu/include/mach/cpu.h | 4 +- > arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 4 - > .../serdes/a38x/high_speed_env_spec.c | 15 -- > board/CZ.NIC/turris_mox/turris_mox.c | 3 - > drivers/pci/pci-aardvark.c | 54 +++-- > drivers/pci/pci_mvebu.c | 205 ++++++++++++------ > 6 files changed, 175 insertions(+), 110 deletions(-) > > -- > 2.32.0 >