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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com
Cc: svarbanov@mm-sol.com, bjorn.andersson@linaro.org,
	robh@kernel.org, linux-pci@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
Date: Tue, 14 Dec 2021 15:43:19 +0530	[thread overview]
Message-ID: <20211214101319.25258-1-manivannan.sadhasivam@linaro.org> (raw)

The DWC controller used in the Qcom Platforms are capable of addressing the
MSIs generated from 8 different endpoints each with 32 vectors (256 in
total). Currently the driver is using the default value of addressing the
MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
num_vectors field of pcie_port structure.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 1c3d1116bb60..8a4c08d815a5 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1550,6 +1550,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 	pci->dev = dev;
 	pci->ops = &dw_pcie_ops;
 	pp = &pci->pp;
+	pp->num_vectors = MAX_MSI_IRQS;
 
 	pcie->pci = pci;
 
-- 
2.25.1


             reply	other threads:[~2021-12-14 10:13 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-14 10:13 Manivannan Sadhasivam [this message]
2022-02-23 10:01 ` [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Lorenzo Pieralisi
2022-03-14  5:22   ` Manivannan Sadhasivam
2022-03-28 14:20   ` Manivannan Sadhasivam
2022-03-28 14:39     ` Lorenzo Pieralisi
2022-04-08  9:52     ` Lorenzo Pieralisi
2022-02-23 10:03 ` Dmitry Baryshkov
2022-02-23 10:30 ` Stanimir Varbanov
2022-04-08 10:03 ` Lorenzo Pieralisi

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