From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 719D3C4332F for ; Wed, 15 Dec 2021 11:17:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236899AbhLOLRF (ORCPT ); Wed, 15 Dec 2021 06:17:05 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:57640 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237067AbhLOLQ5 (ORCPT ); Wed, 15 Dec 2021 06:16:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1639567016; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=C/kACBPtJZeIuY+3f2e1l9jss5UUWc08/NUCKSY8UVM=; b=XxoSSmuVWTYZl1qMtCj7c54zJUPUbnCGYxMb9OhpJ4O+5ySpSjupX1uaZYER+FPs882MXy Xji7eez1mXQjb3/uez3bYc2GtgyuBxg0HkZxfglFFE1sfdnrzYOsIST2ZOdMgdERHJD8BW SkTFW3vF3sUK0X9rAxVffhNuBqKIczc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-446-8SYL8iBXPgiNrlxaWUUICg-1; Wed, 15 Dec 2021 06:16:53 -0500 X-MC-Unique: 8SYL8iBXPgiNrlxaWUUICg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2AD0381CCB5; Wed, 15 Dec 2021 11:16:49 +0000 (UTC) Received: from localhost (ovpn-12-120.pek2.redhat.com [10.72.12.120]) by smtp.corp.redhat.com (Postfix) with ESMTPS id ED0D17E668; Wed, 15 Dec 2021 11:16:46 +0000 (UTC) Date: Wed, 15 Dec 2021 19:16:43 +0800 From: Baoquan He To: Catalin Marinas Cc: Borislav Petkov , Zhen Lei , Thomas Gleixner , Ingo Molnar , x86@kernel.org, "H . Peter Anvin" , linux-kernel@vger.kernel.org, Dave Young , Vivek Goyal , Eric Biederman , kexec@lists.infradead.org, Will Deacon , linux-arm-kernel@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, Randy Dunlap , Feng Zhou , Kefeng Wang , Chen Zhou Subject: Re: [PATCH v17 02/10] x86: kdump: make the lower bound of crash kernel reservation consistent Message-ID: <20211215111643.GF3023@MiWiFi-R3L-srv> References: <20211210065533.2023-1-thunder.leizhen@huawei.com> <20211210065533.2023-3-thunder.leizhen@huawei.com> <20211215034219.GB10336@MiWiFi-R3L-srv> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/15/21 at 11:01am, Catalin Marinas wrote: > On Wed, Dec 15, 2021 at 11:42:19AM +0800, Baoquan He wrote: > > On 12/14/21 at 07:24pm, Catalin Marinas wrote: > > > On Tue, Dec 14, 2021 at 08:07:58PM +0100, Borislav Petkov wrote: > > > > On Fri, Dec 10, 2021 at 02:55:25PM +0800, Zhen Lei wrote: > > > > > From: Chen Zhou > > > > > > > > > > The lower bounds of crash kernel reservation and crash kernel low > > > > > reservation are different, use the consistent value CRASH_ALIGN. > > > > > > > > A big WHY is missing here to explain why the lower bound of the > > > > allocation range needs to be 16M and why was 0 wrong? > > > > > > I asked the same here: > > > > > > https://lore.kernel.org/r/20210224143547.GB28965@arm.com > > > > > > IIRC Baoquan said that there is a 1MB reserved for x86 anyway in the > > > lower part, so that's equivalent in practice to starting from > > > CRASH_ALIGN. > > > > Yeah, even for i386, there's area reserved by BIOS inside low 1M. > > Considering the existing alignment CRASH_ALIGN which is 16M, we > > definitely have no chance to get memory starting from 0. So starting > > from 16M can skip the useless memblock searching, and make the > > crashkernel low reservation consisten with crashkernel reservation on > > allocation code. > > That's the x86 assumption. Is it valid for other architectures once the > code has been made generic in patch 6? It should be ok for arm64, RAM > tends to start from higher up but other architectures may start using > this common code. Good point. I didn't think of this from generic code side, then let's keep it as 0. > > If you want to keep the same semantics as before, just leave it as 0. > It's not that the additional lower bound makes the search slower. Agree. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9779C433EF for ; Wed, 15 Dec 2021 11:25:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6jCnqRSJPPhGsyn13itEeKwRodeyKNMQqc3rTBteniI=; b=kfI1j0TBaQzrR0 l6saPh48tXhPk2f83PjYPEjEBb8UhyTm2PmEsOeUqqpe/ceD+tvBg3+oKTOMzu8kk3W0OFCOlOPoL NaDwqQGLX9mplIwdhXbj7JBtpGm0xQJDqWTpdvthhMeOmiHPLwB2L33G3drAdSY+v72LL0fCjpwyQ 5nk/QRxaMGhozglyyFRzgyq0WEdR87QaTNliELAM50jSEnXJHaG26kCtVXiQJS4PjZ+VyFByXl4YO rFYiDlY3eFxj/gLFnptRt8nFz3ApnFFFBrOyH7CUxcsQVd3s8Myxzu/a/ORPGkXj1/HVVrdSNE3Zh 0xcQrNnG/VK3ihON9eWA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxSO3-000XO1-FE; Wed, 15 Dec 2021 11:23:56 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxSHJ-000Ttn-Rw for linux-arm-kernel@lists.infradead.org; Wed, 15 Dec 2021 11:17:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1639567016; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=C/kACBPtJZeIuY+3f2e1l9jss5UUWc08/NUCKSY8UVM=; b=XxoSSmuVWTYZl1qMtCj7c54zJUPUbnCGYxMb9OhpJ4O+5ySpSjupX1uaZYER+FPs882MXy Xji7eez1mXQjb3/uez3bYc2GtgyuBxg0HkZxfglFFE1sfdnrzYOsIST2ZOdMgdERHJD8BW SkTFW3vF3sUK0X9rAxVffhNuBqKIczc= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-446-8SYL8iBXPgiNrlxaWUUICg-1; Wed, 15 Dec 2021 06:16:53 -0500 X-MC-Unique: 8SYL8iBXPgiNrlxaWUUICg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2AD0381CCB5; Wed, 15 Dec 2021 11:16:49 +0000 (UTC) Received: from localhost (ovpn-12-120.pek2.redhat.com [10.72.12.120]) by smtp.corp.redhat.com (Postfix) with ESMTPS id ED0D17E668; Wed, 15 Dec 2021 11:16:46 +0000 (UTC) Date: Wed, 15 Dec 2021 19:16:43 +0800 From: Baoquan He To: Catalin Marinas Cc: Borislav Petkov , Zhen Lei , Thomas Gleixner , Ingo Molnar , x86@kernel.org, "H . Peter Anvin" , linux-kernel@vger.kernel.org, Dave Young , Vivek Goyal , Eric Biederman , kexec@lists.infradead.org, Will Deacon , linux-arm-kernel@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, Randy Dunlap , Feng Zhou , Kefeng Wang , Chen Zhou Subject: Re: [PATCH v17 02/10] x86: kdump: make the lower bound of crash kernel reservation consistent Message-ID: <20211215111643.GF3023@MiWiFi-R3L-srv> References: <20211210065533.2023-1-thunder.leizhen@huawei.com> <20211210065533.2023-3-thunder.leizhen@huawei.com> <20211215034219.GB10336@MiWiFi-R3L-srv> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211215_031658_011412_5BD99B8C X-CRM114-Status: GOOD ( 28.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/15/21 at 11:01am, Catalin Marinas wrote: > On Wed, Dec 15, 2021 at 11:42:19AM +0800, Baoquan He wrote: > > On 12/14/21 at 07:24pm, Catalin Marinas wrote: > > > On Tue, Dec 14, 2021 at 08:07:58PM +0100, Borislav Petkov wrote: > > > > On Fri, Dec 10, 2021 at 02:55:25PM +0800, Zhen Lei wrote: > > > > > From: Chen Zhou > > > > > > > > > > The lower bounds of crash kernel reservation and crash kernel low > > > > > reservation are different, use the consistent value CRASH_ALIGN. > > > > > > > > A big WHY is missing here to explain why the lower bound of the > > > > allocation range needs to be 16M and why was 0 wrong? > > > > > > I asked the same here: > > > > > > https://lore.kernel.org/r/20210224143547.GB28965@arm.com > > > > > > IIRC Baoquan said that there is a 1MB reserved for x86 anyway in the > > > lower part, so that's equivalent in practice to starting from > > > CRASH_ALIGN. > > > > Yeah, even for i386, there's area reserved by BIOS inside low 1M. > > Considering the existing alignment CRASH_ALIGN which is 16M, we > > definitely have no chance to get memory starting from 0. So starting > > from 16M can skip the useless memblock searching, and make the > > crashkernel low reservation consisten with crashkernel reservation on > > allocation code. > > That's the x86 assumption. Is it valid for other architectures once the > code has been made generic in patch 6? It should be ok for arm64, RAM > tends to start from higher up but other architectures may start using > this common code. Good point. I didn't think of this from generic code side, then let's keep it as 0. > > If you want to keep the same semantics as before, just leave it as 0. > It's not that the additional lower bound makes the search slower. Agree. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxSHI-000Tsz-44 for kexec@lists.infradead.org; Wed, 15 Dec 2021 11:16:57 +0000 Date: Wed, 15 Dec 2021 19:16:43 +0800 From: Baoquan He Subject: Re: [PATCH v17 02/10] x86: kdump: make the lower bound of crash kernel reservation consistent Message-ID: <20211215111643.GF3023@MiWiFi-R3L-srv> References: <20211210065533.2023-1-thunder.leizhen@huawei.com> <20211210065533.2023-3-thunder.leizhen@huawei.com> <20211215034219.GB10336@MiWiFi-R3L-srv> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kexec" Errors-To: kexec-bounces+dwmw2=infradead.org@lists.infradead.org To: Catalin Marinas Cc: Borislav Petkov , Zhen Lei , Thomas Gleixner , Ingo Molnar , x86@kernel.org, "H . Peter Anvin" , linux-kernel@vger.kernel.org, Dave Young , Vivek Goyal , Eric Biederman , kexec@lists.infradead.org, Will Deacon , linux-arm-kernel@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, Randy Dunlap , Feng Zhou , Kefeng Wang , Chen Zhou On 12/15/21 at 11:01am, Catalin Marinas wrote: > On Wed, Dec 15, 2021 at 11:42:19AM +0800, Baoquan He wrote: > > On 12/14/21 at 07:24pm, Catalin Marinas wrote: > > > On Tue, Dec 14, 2021 at 08:07:58PM +0100, Borislav Petkov wrote: > > > > On Fri, Dec 10, 2021 at 02:55:25PM +0800, Zhen Lei wrote: > > > > > From: Chen Zhou > > > > > > > > > > The lower bounds of crash kernel reservation and crash kernel low > > > > > reservation are different, use the consistent value CRASH_ALIGN. > > > > > > > > A big WHY is missing here to explain why the lower bound of the > > > > allocation range needs to be 16M and why was 0 wrong? > > > > > > I asked the same here: > > > > > > https://lore.kernel.org/r/20210224143547.GB28965@arm.com > > > > > > IIRC Baoquan said that there is a 1MB reserved for x86 anyway in the > > > lower part, so that's equivalent in practice to starting from > > > CRASH_ALIGN. > > > > Yeah, even for i386, there's area reserved by BIOS inside low 1M. > > Considering the existing alignment CRASH_ALIGN which is 16M, we > > definitely have no chance to get memory starting from 0. So starting > > from 16M can skip the useless memblock searching, and make the > > crashkernel low reservation consisten with crashkernel reservation on > > allocation code. > > That's the x86 assumption. Is it valid for other architectures once the > code has been made generic in patch 6? It should be ok for arm64, RAM > tends to start from higher up but other architectures may start using > this common code. Good point. I didn't think of this from generic code side, then let's keep it as 0. > > If you want to keep the same semantics as before, just leave it as 0. > It's not that the additional lower bound makes the search slower. Agree. _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec