From: Stephen Boyd <sboyd@kernel.org>
To: Loic Poulain <loic.poulain@linaro.org>,
agross@kernel.org, bjorn.andersson@linaro.org,
robh+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, shawn.guo@linaro.org,
Loic Poulain <loic.poulain@linaro.org>
Subject: Re: [PATCH v2 1/2] clk: qcom: Add display clock controller driver for QCM2290
Date: Wed, 15 Dec 2021 19:49:07 -0800 [thread overview]
Message-ID: <20211216034909.3EFCBC36AE0@smtp.kernel.org> (raw)
In-Reply-To: <1639058951-12660-1-git-send-email-loic.poulain@linaro.org>
Quoting Loic Poulain (2021-12-09 06:09:10)
> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> new file mode 100644
> index 00000000..8aa5d31
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc-qcm2290.c
> @@ -0,0 +1,602 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2021, Linaro Ltd.
> + */
> +
> +#include <linux/clk.h>
Is this include used?
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "reset.h"
> +#include "gdsc.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_CORE_BI_PLL_TEST_SE,
> + P_DISP_CC_PLL0_OUT_MAIN,
> + P_DSI0_PHY_PLL_OUT_BYTECLK,
> + P_DSI0_PHY_PLL_OUT_DSICLK,
> + P_DSI1_PHY_PLL_OUT_DSICLK,
> + P_GPLL0_OUT_MAIN,
> + P_SLEEP_CLK,
> +};
> +
> +static struct pll_vco spark_vco[] = {
const
> + { 500000000, 1000000000, 2 },
> +};
> +
> +/* 768MHz configuration */
> +static const struct alpha_pll_config disp_cc_pll0_config = {
> + .l = 0x28,
> + .alpha = 0x0,
> + .alpha_en_mask = BIT(24),
> + .vco_val = 0x2 << 20,
> + .vco_mask = GENMASK(21, 20),
> + .main_output_mask = BIT(0),
> + .config_ctl_val = 0x4001055B,
> +};
> +
> +static struct clk_alpha_pll disp_cc_pll0 = {
> + .offset = 0x0,
> + .vco_table = spark_vco,
> + .num_vco = ARRAY_SIZE(spark_vco),
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_pll0",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_0[] = {
> + { P_BI_TCXO, 0 },
> + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
> + { P_CORE_BI_PLL_TEST_SE, 7 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_0[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "dsi0_phy_pll_out_byteclk" },
> + { .fw_name = "core_bi_pll_test_se" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_1[] = {
> + { P_BI_TCXO, 0 },
> + { P_CORE_BI_PLL_TEST_SE, 7 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_1[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "core_bi_pll_test_se" },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_1_ao[] = {
> + { .fw_name = "bi_tcxo_ao" },
> + { .fw_name = "core_bi_pll_test_se" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_2[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 4 },
> + { P_CORE_BI_PLL_TEST_SE, 7 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_2[] = {
> + { .fw_name = "bi_tcxo_ao" },
> + { .fw_name = "gcc_disp_gpll0_div_clk_src" },
> + { .fw_name = "core_bi_pll_test_se" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_3[] = {
> + { P_BI_TCXO, 0 },
> + { P_DISP_CC_PLL0_OUT_MAIN, 1 },
> + { P_GPLL0_OUT_MAIN, 4 },
> + { P_CORE_BI_PLL_TEST_SE, 7 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_3[] = {
> + { .fw_name = "bi_tcxo" },
> + { .hw = &disp_cc_pll0.clkr.hw },
> + { .fw_name = "gcc_disp_gpll0_clk_src" },
> + { .fw_name = "core_bi_pll_test_se" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_4[] = {
> + { P_BI_TCXO, 0 },
> + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
> + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
> + { P_CORE_BI_PLL_TEST_SE, 7 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_4[] = {
> + { .fw_name = "bi_tcxo" },
> + { .fw_name = "dsi0_phy_pll_out_dsiclk" },
> + { .fw_name = "dsi1_phy_pll_out_dsiclk" },
> + { .fw_name = "core_bi_pll_test_se" },
> +};
> +
> +static const struct parent_map disp_cc_parent_map_5[] = {
> + { P_SLEEP_CLK, 0 },
> + { P_CORE_BI_PLL_TEST_SE, 7 },
> +};
> +
> +static const struct clk_parent_data disp_cc_parent_data_5[] = {
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
Please don't add .name to clk_parent_data if this is a new driver.
> + { .fw_name = "core_bi_pll_test_se" },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
> + .cmd_rcgr = 0x20a4,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_0,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte0_clk_src",
> + .parent_data = disp_cc_parent_data_0,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
> + .ops = &clk_byte2_ops,
> + },
> +};
> +
> +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
> + .reg = 0x20bc,
> + .shift = 0,
> + .width = 2,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "disp_cc_mdss_byte0_div_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_byte0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + .ops = &clk_regmap_div_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
> + .cmd_rcgr = 0x2154,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_2,
> + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_ahb_clk_src",
> + .parent_data = disp_cc_parent_data_2,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
> + .cmd_rcgr = 0x20c0,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_0,
> + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_esc0_clk_src",
> + .parent_data = disp_cc_parent_data_0,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
> + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
> + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
> + F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
> + .cmd_rcgr = 0x2074,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_3,
> + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_mdp_clk_src",
> + .parent_data = disp_cc_parent_data_3,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
> + .cmd_rcgr = 0x205c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_pclk0_clk_src",
> + .parent_data = disp_cc_parent_data_4,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
These last two flags are needed for what?
> + .ops = &clk_pixel_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
> + .cmd_rcgr = 0x208c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_1,
> + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_vsync_clk_src",
> + .parent_data = disp_cc_parent_data_1,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
> + F(32764, P_SLEEP_CLK, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 disp_cc_sleep_clk_src = {
> + .cmd_rcgr = 0x6050,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_5,
> + .freq_tbl = ftbl_disp_cc_sleep_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_sleep_clk_src",
> + .parent_data = disp_cc_parent_data_5,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 disp_cc_xo_clk_src = {
> + .cmd_rcgr = 0x6034,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = disp_cc_parent_map_1,
> + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "disp_cc_xo_clk_src",
> + .parent_data = disp_cc_parent_data_1_ao,
> + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_ahb_clk = {
> + .halt_reg = 0x2044,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2044,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_byte0_clk = {
> + .halt_reg = 0x201c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x201c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte0_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_byte0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
> + .halt_reg = 0x2020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2020,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_byte0_intf_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_esc0_clk = {
> + .halt_reg = 0x2024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2024,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_esc0_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_esc0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_mdp_clk = {
> + .halt_reg = 0x2008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_mdp_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_mdp_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
> + .halt_reg = 0x2010,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_mdp_lut_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_mdp_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
> + .halt_reg = 0x4004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x4004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_non_gdsc_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_pclk0_clk = {
> + .halt_reg = 0x2004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_pclk0_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_pclk0_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_mdss_vsync_clk = {
> + .halt_reg = 0x2018,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_mdss_vsync_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_mdss_vsync_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_sleep_clk = {
> + .halt_reg = 0x6068,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x6068,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_sleep_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_sleep_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch disp_cc_xo_clk = {
> + .halt_reg = 0x604c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x604c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "disp_cc_xo_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &disp_cc_xo_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
We need a comment why it's critical. Also I'm not sure why we would ever
turn this clk off or change the rate. Can't we just hit some registers
during probe to make sure it's on and drop this clk?
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
next prev parent reply other threads:[~2021-12-16 3:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-09 14:09 [PATCH v2 1/2] clk: qcom: Add display clock controller driver for QCM2290 Loic Poulain
2021-12-09 14:09 ` [PATCH v2 2/2] dt-bindings: clock: Add qualcomm QCM2290 DISPCC bindings Loic Poulain
2021-12-15 3:41 ` Bjorn Andersson
2021-12-15 18:13 ` Rob Herring
2021-12-15 3:39 ` [PATCH v2 1/2] clk: qcom: Add display clock controller driver for QCM2290 Bjorn Andersson
2021-12-16 3:49 ` Stephen Boyd [this message]
2021-12-16 19:21 ` Loic Poulain
2021-12-17 1:37 ` Stephen Boyd
2021-12-17 1:58 ` Dmitry Baryshkov
2021-12-17 16:16 ` Steev Klimaszewski
2021-12-17 16:54 ` Loic Poulain
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211216034909.3EFCBC36AE0@smtp.kernel.org \
--to=sboyd@kernel.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=loic.poulain@linaro.org \
--cc=robh+dt@kernel.org \
--cc=shawn.guo@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.