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Date:   Fri, 17 Dec 2021 14:22:45 +0530
From:   Pratyush Yadav <p.yadav@ti.com>
To:     Dinh Nguyen <dinguyen@kernel.org>
CC:     <devicetree@vger.kernel.org>, <robh+dt@kernel.org>
Subject: Re: [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document
 "intel,socfpga-qspi"
Message-ID: <20211217085243.bmj45gc4awnmkmp3@ti.com>
References: <20211216224902.374403-1-dinguyen@kernel.org>
 <20211216224902.374403-2-dinguyen@kernel.org>
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On 16/12/21 04:49PM, Dinh Nguyen wrote:
> The QSPI controller on Intel's SoCFPGA platform does not implement the
> CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
> results in a crash.
> 
> Introduce the dts compatible "intel,socfpga-qspi" to differentiate the
> hardware.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Acked-by: Pratyush Yadav <p.yadav@ti.com>

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.