* [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
@ 2021-12-18 20:00 ` Richard Schleich
0 siblings, 0 replies; 8+ messages in thread
From: Richard Schleich @ 2021-12-18 20:00 UTC (permalink / raw)
To: robh+dt, nsaenz, f.fainelli, bcm-kernel-feedback-list,
devicetree, linux-rpi-kernel, linux-arm-kernel
Cc: Richard Schleich
This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.
Signed-off-by: Richard Schleich <rs@noreya.tech>
---
arch/arm/boot/dts/bcm2837.dtsi | 49 ++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 0199ec98cd61..1af1616982bb 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -40,12 +40,26 @@
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
+ * /about-the-l1-memory-system?lang=en
+ *
+ * Source for d/i-cache-size
+ * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
+ */
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@@ -54,6 +68,13 @@
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@@ -62,6 +83,13 @@
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@@ -70,6 +98,27 @@
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ /* Source for cache-line-size + cache-sets
+ * https://developer.arm.com/documentation/ddi0500
+ * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
+ * Source for cache-size
+ * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
+ */
+ compatible = "cache";
+ cache-size = <0x80000>; // 512KiB
+ cache-line-size = <64>; // Fixed line length of 64 bytes
+ cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
+ cache-level = <2>;
};
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
@ 2021-12-18 20:00 ` Richard Schleich
0 siblings, 0 replies; 8+ messages in thread
From: Richard Schleich @ 2021-12-18 20:00 UTC (permalink / raw)
To: robh+dt, nsaenz, f.fainelli, bcm-kernel-feedback-list,
devicetree, linux-rpi-kernel, linux-arm-kernel
Cc: Richard Schleich
This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.
Signed-off-by: Richard Schleich <rs@noreya.tech>
---
arch/arm/boot/dts/bcm2837.dtsi | 49 ++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 0199ec98cd61..1af1616982bb 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -40,12 +40,26 @@
#size-cells = <0>;
enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
+ * /about-the-l1-memory-system?lang=en
+ *
+ * Source for d/i-cache-size
+ * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
+ */
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@@ -54,6 +68,13 @@
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@@ -62,6 +83,13 @@
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@@ -70,6 +98,27 @@
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
+ d-cache-size = <0x8000>; // 32KiB
+ d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>; // 32KiB
+ i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ /* Source for cache-line-size + cache-sets
+ * https://developer.arm.com/documentation/ddi0500
+ * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
+ * Source for cache-size
+ * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
+ */
+ compatible = "cache";
+ cache-size = <0x80000>; // 512KiB
+ cache-line-size = <64>; // Fixed line length of 64 bytes
+ cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
+ cache-level = <2>;
};
};
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
2021-12-18 20:00 ` Richard Schleich
@ 2021-12-28 17:52 ` Stefan Wahren
-1 siblings, 0 replies; 8+ messages in thread
From: Stefan Wahren @ 2021-12-28 17:52 UTC (permalink / raw)
To: Richard Schleich, robh+dt, nsaenz, f.fainelli,
bcm-kernel-feedback-list, devicetree, linux-rpi-kernel,
linux-arm-kernel
Am 18.12.21 um 21:00 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2837 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
I tested the patch with a Raspberry Pi 3 B Plus (arm64/defconfig) and here are
some outputs:
/sys/devices/system/cpu/cpu0/cache
./index2/number_of_sets:512
./index2/ways_of_associativity:16
./index2/shared_cpu_list:0-3
./index2/type:Unified
./index2/size:512K
./index2/level:2
./index2/coherency_line_size:64
./index2/shared_cpu_map:f
./index0/number_of_sets:128
./index0/ways_of_associativity:4
./index0/shared_cpu_list:0
./index0/type:Data
./index0/size:32K
./index0/level:1
./index0/coherency_line_size:64
./index0/shared_cpu_map:1
./index1/number_of_sets:256
./index1/ways_of_associativity:2
./index1/shared_cpu_list:0
./index1/type:Instruction
./index1/size:32K
./index1/level:1
./index1/coherency_line_size:64
./index1/shared_cpu_map:1
lscpu
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: ARM
Model: 4
Model name: Cortex-A53
Stepping: r0p4
CPU max MHz: 1400,0000
CPU min MHz: 600,0000
BogoMIPS: 38.40
L1d cache: 32K
L1i cache: 32K
L2 cache: 512K
NUMA node0 CPU(s): 0-3
Flags: fp asimd evtstrm crc32 cpuid
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
@ 2021-12-28 17:52 ` Stefan Wahren
0 siblings, 0 replies; 8+ messages in thread
From: Stefan Wahren @ 2021-12-28 17:52 UTC (permalink / raw)
To: Richard Schleich, robh+dt, nsaenz, f.fainelli,
bcm-kernel-feedback-list, devicetree, linux-rpi-kernel,
linux-arm-kernel
Am 18.12.21 um 21:00 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2837 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
I tested the patch with a Raspberry Pi 3 B Plus (arm64/defconfig) and here are
some outputs:
/sys/devices/system/cpu/cpu0/cache
./index2/number_of_sets:512
./index2/ways_of_associativity:16
./index2/shared_cpu_list:0-3
./index2/type:Unified
./index2/size:512K
./index2/level:2
./index2/coherency_line_size:64
./index2/shared_cpu_map:f
./index0/number_of_sets:128
./index0/ways_of_associativity:4
./index0/shared_cpu_list:0
./index0/type:Data
./index0/size:32K
./index0/level:1
./index0/coherency_line_size:64
./index0/shared_cpu_map:1
./index1/number_of_sets:256
./index1/ways_of_associativity:2
./index1/shared_cpu_list:0
./index1/type:Instruction
./index1/size:32K
./index1/level:1
./index1/coherency_line_size:64
./index1/shared_cpu_map:1
lscpu
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: ARM
Model: 4
Model name: Cortex-A53
Stepping: r0p4
CPU max MHz: 1400,0000
CPU min MHz: 600,0000
BogoMIPS: 38.40
L1d cache: 32K
L1i cache: 32K
L2 cache: 512K
NUMA node0 CPU(s): 0-3
Flags: fp asimd evtstrm crc32 cpuid
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
2021-12-18 20:00 ` Richard Schleich
@ 2022-02-01 0:24 ` Florian Fainelli
-1 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2022-02-01 0:24 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Richard Schleich, robh+dt, nsaenz,
devicetree, linux-rpi-kernel, linux-arm-kernel
On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs@noreya.tech> wrote:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2837 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
@ 2022-02-01 0:24 ` Florian Fainelli
0 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2022-02-01 0:24 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Richard Schleich, robh+dt, nsaenz,
devicetree, linux-rpi-kernel, linux-arm-kernel
On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs@noreya.tech> wrote:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2837 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
2022-02-01 0:24 ` Florian Fainelli
@ 2022-02-01 0:29 ` Florian Fainelli
-1 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2022-02-01 0:29 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Richard Schleich, robh+dt, nsaenz,
devicetree, linux-rpi-kernel, linux-arm-kernel
On 1/31/2022 4:24 PM, Florian Fainelli wrote:
> On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs@noreya.tech> wrote:
>> This patch fixes the kernel warning
>> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
>> for the bcm2837 on newer kernel versions.
>>
>> Signed-off-by: Richard Schleich <rs@noreya.tech>
>> ---
>
> Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
I did remove the comments that were not helpful for the 'd-cache-size',
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size' since they
are self explanatory.
Thanks!
--
Florian
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
@ 2022-02-01 0:29 ` Florian Fainelli
0 siblings, 0 replies; 8+ messages in thread
From: Florian Fainelli @ 2022-02-01 0:29 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Richard Schleich, robh+dt, nsaenz,
devicetree, linux-rpi-kernel, linux-arm-kernel
On 1/31/2022 4:24 PM, Florian Fainelli wrote:
> On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs@noreya.tech> wrote:
>> This patch fixes the kernel warning
>> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
>> for the bcm2837 on newer kernel versions.
>>
>> Signed-off-by: Richard Schleich <rs@noreya.tech>
>> ---
>
> Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
I did remove the comments that were not helpful for the 'd-cache-size',
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size' since they
are self explanatory.
Thanks!
--
Florian
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-02-01 0:31 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-18 20:00 [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information Richard Schleich
2021-12-18 20:00 ` Richard Schleich
2021-12-28 17:52 ` Stefan Wahren
2021-12-28 17:52 ` Stefan Wahren
2022-02-01 0:24 ` Florian Fainelli
2022-02-01 0:24 ` Florian Fainelli
2022-02-01 0:29 ` Florian Fainelli
2022-02-01 0:29 ` Florian Fainelli
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.