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envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h, fcvt.h.d Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-8-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/translate.c | 2 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 22 ++++++++++++++-------- 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 570c49f365..ef677f9092 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -313,6 +313,7 @@ struct RISCVCPU { bool ext_ifencei; bool ext_icsr; bool ext_zfh; + bool ext_zfhmin; =20 char *priv_spec; char *user_spec; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 93f9ec0c8b..d445954dc7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -74,6 +74,7 @@ typedef struct DisasContext { bool virt_enabled; bool ext_ifencei; bool ext_zfh; + bool ext_zfhmin; bool hlsx; /* vector extension */ bool vill; @@ -644,6 +645,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; ctx->ext_zfh =3D cpu->cfg.ext_zfh; + ctx->ext_zfhmin =3D cpu->cfg.ext_zfhmin; ctx->vlen =3D cpu->cfg.vlen; ctx->mstatus_hs_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS)= ; ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/ins= n_trans/trans_rvzfh.c.inc index 0549e25fb4..5a7cac8958 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -22,13 +22,19 @@ } \ } while (0) =20 +#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ + if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \ + return false; \ + } \ +} while (0) + static bool trans_flh(DisasContext *ctx, arg_flh *a) { TCGv_i64 dest; TCGv t0; =20 REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); =20 t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -50,7 +56,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) TCGv t0; =20 REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); =20 t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -283,7 +289,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_= h *a) static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); @@ -296,7 +302,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcv= t_s_h *a) static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); REQUIRE_EXT(ctx, RVD); =20 gen_set_rm(ctx, a->rm); @@ -311,7 +317,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcv= t_d_h *a) static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); =20 gen_set_rm(ctx, a->rm); gen_helper_fcvt_h_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); @@ -324,7 +330,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcv= t_h_s *a) static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); REQUIRE_EXT(ctx, RVD); =20 gen_set_rm(ctx, a->rm); @@ -441,7 +447,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fc= vt_h_wu *a) static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); =20 @@ -461,7 +467,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_= x_h *a) static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); =20 TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 --=20 2.31.1