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charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis =0D Populate mtval and stval when taking an illegal instruction exception.=0D =0D The RISC-V spec states that "The stval register can optionally also be=0D used to return the faulting instruction bits on an illegal instruction=0D exception...". In this case we are always writing the value on an=0D illegal instruction.=0D =0D This doesn't match all CPUs (some CPUs won't write the data), but in=0D QEMU let's just populate the value on illegal instructions. This won't=0D break any guest software, but will provide more information to guests.=0D =0D Alistair Francis (3):=0D target/riscv: Set the opcode in DisasContext=0D target/riscv: Fixup setting GVA=0D target/riscv: Implement the stval/mtval illegal instruction=0D =0D target/riscv/cpu.h | 2 ++=0D target/riscv/cpu_helper.c | 24 +++++++++---------------=0D target/riscv/translate.c | 5 +++++=0D 3 files changed, 16 insertions(+), 15 deletions(-)=0D =0D -- =0D 2.31.1=0D =0D