From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: git@xen0n.name
Subject: [PATCH v2 00/30] tcg/loongarch64: New tcg backend
Date: Tue, 21 Dec 2021 13:25:58 -0800 [thread overview]
Message-ID: <20211221212558.1835038-1-richard.henderson@linaro.org> (raw)
Version 2: Dropped patch 31, the gitlab-ci change:
Found errors in your .gitlab-ci.yml:
'cross-loongarch64-system' job needs 'loongarch64-cross-container' job
but 'loongarch64-cross-container' is not in any previous stage
'cross-loongarch64-user' job needs 'loongarch64-cross-container' job
but 'loongarch64-cross-container' is not in any previous stage
r~
The following changes since commit 5316e12bb2b4408a1597b283ef4bb4794dd7b4f7:
Merge tag 'dbus-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2021-12-21 08:00:26 -0800)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-loong-20211221-2
for you to fetch changes up to dfcf900ba67040ea9aa839aa38b33b4c091721d8:
configure, meson.build: Mark support for loongarch64 hosts (2021-12-21 13:17:06 -0800)
----------------------------------------------------------------
Initial commit of tcg/loongarch64
----------------------------------------------------------------
WANG Xuerui (30):
elf: Add machine type value for LoongArch
MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer
tcg/loongarch64: Add the tcg-target.h file
tcg/loongarch64: Add generated instruction opcodes and encoding helpers
tcg/loongarch64: Add register names, allocation order and input/output sets
tcg/loongarch64: Define the operand constraints
tcg/loongarch64: Implement necessary relocation operations
tcg/loongarch64: Implement the memory barrier op
tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
tcg/loongarch64: Implement goto_ptr
tcg/loongarch64: Implement sign-/zero-extension ops
tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops
tcg/loongarch64: Implement deposit/extract ops
tcg/loongarch64: Implement bswap{16,32,64} ops
tcg/loongarch64: Implement clz/ctz ops
tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops
tcg/loongarch64: Implement add/sub ops
tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops
tcg/loongarch64: Implement br/brcond ops
tcg/loongarch64: Implement setcond ops
tcg/loongarch64: Implement tcg_out_call
tcg/loongarch64: Implement simple load/store ops
tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops
tcg/loongarch64: Implement tcg_target_qemu_prologue
tcg/loongarch64: Implement exit_tb/goto_tb
tcg/loongarch64: Implement tcg_target_init
tcg/loongarch64: Register the JIT
common-user: Add safe syscall handling for loongarch64 hosts
linux-user: Implement CPU-specific signal handler for loongarch64 hosts
configure, meson.build: Mark support for loongarch64 hosts
configure | 5 +
meson.build | 2 +-
include/elf.h | 2 +
linux-user/host/loongarch64/host-signal.h | 87 ++
tcg/loongarch64/tcg-target-con-set.h | 31 +
tcg/loongarch64/tcg-target-con-str.h | 28 +
tcg/loongarch64/tcg-target.h | 180 +++
tcg/loongarch64/tcg-insn-defs.c.inc | 979 +++++++++++++
tcg/loongarch64/tcg-target.c.inc | 1677 +++++++++++++++++++++++
MAINTAINERS | 5 +
common-user/host/loongarch64/safe-syscall.inc.S | 90 ++
11 files changed, 3085 insertions(+), 1 deletion(-)
create mode 100644 linux-user/host/loongarch64/host-signal.h
create mode 100644 tcg/loongarch64/tcg-target-con-set.h
create mode 100644 tcg/loongarch64/tcg-target-con-str.h
create mode 100644 tcg/loongarch64/tcg-target.h
create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc
create mode 100644 tcg/loongarch64/tcg-target.c.inc
create mode 100644 common-user/host/loongarch64/safe-syscall.inc.S
next reply other threads:[~2021-12-21 21:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 21:25 Richard Henderson [this message]
2021-12-21 22:53 ` [PATCH v2 00/30] tcg/loongarch64: New tcg backend Richard Henderson
2021-12-29 6:44 ` WANG Xuerui
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