From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 544DCC433F5 for ; Fri, 24 Dec 2021 07:25:54 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BC2A683693; Fri, 24 Dec 2021 08:25:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="JdiOBYas"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6FB3E83709; Fri, 24 Dec 2021 08:25:49 +0100 (CET) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4845E83510 for ; Fri, 24 Dec 2021 08:25:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PgP3076074; Fri, 24 Dec 2021 01:25:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1640330742; bh=vx5CaTBgJG9ETWVAxZcMFeAJLiPBPTQTTtXQUbQ1NYA=; h=From:To:CC:Subject:Date; b=JdiOBYasMYOZfsOHQi7CNf9scvikAi/zUPEiuotaxkYjRGBYXDTIA+bRRFbufUMqS 6yA2X/WeJdgGhd2ZcBImgOM2JYFd8nn8DvxjbMgjB4S6Al2KPH1PaJXO/djAwaI6Sv PFGmOXuj+a/WCHOGKeQs9pBV7vLwmFxmKRZ8eFqI= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1BO7Pgjf105633 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 Dec 2021 01:25:42 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 24 Dec 2021 01:25:42 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 24 Dec 2021 01:25:42 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJQ097108; Fri, 24 Dec 2021 01:25:39 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 0/8] ARM: ti: AM64x: Add Ethernet boot support on AM64x SK Date: Fri, 24 Dec 2021 12:55:28 +0530 Message-ID: <20211224072536.270251-1-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This series enables ethernet boot support on AM64x SK. AM64x SoC has CPSW3g IP that supports 2 ext Eth port. ROM supports booting from 2nd port. But currently am65-cpsw-nuss only supports single port (1st port). So the first two patches modify driver to support more than 1 ext port. This is done by breaking up am65-cpsw-nuss into UCLASS_MISC for toplevel NUSS driver and UCLASS_ETH for each of individual ports. Next 4 patches add mach-k3 and board level changes to enable Ethernet and TFTP to work at SPL. Last two patches add dts and config changes need to for Ethernet boot. Tested on AM64x SK with RGMII 1G bootmode at 1G. https://controlc.com/90d555ee Sanity tested TFTP at U-Boot prompt on AM65x and J721e. Vignesh Raghavendra (8): mach-k3: common: Instantiate AM65 CPSW NUSS wrapper net: ti: am65-cpsw: Add support for multi port independent MAC mode board: ti: am64x: Init DRAM size in R5/A53 SPL mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC configs: am64x_evm: set eth1 as boot interface ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot arch/arm/dts/k3-am642-r5-sk.dts | 74 +++++++++++++++++++++++ arch/arm/dts/k3-am642-sk-u-boot.dtsi | 40 +++++++++++- arch/arm/mach-k3/am642_init.c | 7 +++ arch/arm/mach-k3/common.c | 16 +++++ arch/arm/mach-k3/include/mach/am64_spl.h | 1 + board/ti/am64x/evm.c | 3 + configs/am64x_evm_a53_defconfig | 4 ++ configs/am64x_evm_r5_defconfig | 12 ++++ drivers/net/ti/Kconfig | 2 + drivers/net/ti/am65-cpsw-nuss.c | 77 +++++++++++++++--------- include/configs/am64x_evm.h | 5 +- 11 files changed, 212 insertions(+), 29 deletions(-) -- 2.34.1