[PATCH v6 0/4] Add octal DTR support for Macronix flash

[PATCH v6 0/4] Add octal DTR support for Macronix flash

[JaimeLiao]

This series add support for Macronix octal DTR flash, add flag for
Softreset with "INVERT" command extension type on boot and follow
linux kernel to enable 4byte opcode when possible.

v6:
  Parcing SCCR 22nd dword for checking Octal DTR mode support

v5:
  Replace SPI_FLASH_MACRONIX_OCTAL with SPI_FLASH_MACRONIX.
  Remove patch of set_4byte opcode.

v4:
  Add flag SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT to seperate command extension
  types.
  Replace ifdef with CONFIG_IS_ENABLED and modify uncorrect descriptions.

v3:
  Add flag  SPI_NOR_CMD_EXT_INVERT to seperate command extension types.
  replace CONFIG_SPI_FLASH_MACRONIX with SPI_FLASH_MACRONIX_OCTAL for
  spi_nor_macronix_octal_dtr_enable function.
v2:
  add ret checking for write enable in spi_nor_macronix_octal_dtr_enable
  function.

JaimeLiao (4):
  mtd: spi-nor: macronix: add support for Macronix Octal
  mtd: spi-nor-core: Adding different type of command extension in Soft
    Reset
  mtd: spi-nor-core: Add support for Macronix Octal flash
  mtd: spi-nor: Parse SFDP SCCR Map

 drivers/mtd/spi/Kconfig        |   7 ++
 drivers/mtd/spi/spi-nor-core.c | 142 ++++++++++++++++++++++++++++++++-
 drivers/mtd/spi/spi-nor-ids.c  |  22 ++++-
 include/linux/mtd/spi-nor.h    |  13 ++-
 4 files changed, 180 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH v6 1/4] mtd: spi-nor: macronix: add support for Macronix Octal

[JaimeLiao]

Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
Macronix flash in Octal DTR mode.

Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency.
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h    | 12 ++++-
 2 files changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index d5d905fa5a..0a6550984b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
 };
 #endif /* CONFIG_SPI_FLASH_MT35XU */
 
+#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
+/**
+ * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
+ * @nor:	pointer to a 'struct spi_nor'
+ *
+ * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
+ * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	int ret;
+	u8 buf;
+
+	ret = write_enable(nor);
+	if (ret)
+		return ret;
+
+	buf = SPINOR_REG_MXIC_DC_20;
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
+			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
+
+	ret = spi_mem_exec_op(nor->spi, &op);
+	if (ret)
+		return ret;
+
+	ret = spi_nor_wait_till_ready(nor);
+	if (ret)
+		return ret;
+
+	nor->read_dummy = MXIC_MAX_DC;
+	ret = write_enable(nor);
+	if (ret)
+		return ret;
+
+	buf = SPINOR_REG_MXIC_OPI_DTR_EN;
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
+			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
+
+	ret = spi_mem_exec_op(nor->spi, &op);
+	if (ret) {
+		dev_err(nor->dev, "Failed to enable octal DTR mode\n");
+		return ret;
+	}
+	nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+
+	return 0;
+}
+
+static void macronix_octal_default_init(struct spi_nor *nor)
+{
+	nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
+}
+
+static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
+					 struct spi_nor_flash_parameter *params)
+{
+	/*
+	 * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
+	 * SPI_NOR_OCTAL_DTR_READ flag exists.
+	 */
+	if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
+		params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+}
+
+static struct spi_nor_fixups macronix_octal_fixups = {
+	.default_init = macronix_octal_default_init,
+	.post_sfdp = macronix_octal_post_sfdp_fixup,
+};
+#endif /* CONFIG_SPI_FLASH_MACRONIX */
+
 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
  * @nor:                 pointer to a 'struct spi_nor'
  *
@@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
 	if (!strcmp(nor->info->name, "mt35xu512aba"))
 		nor->fixups = &mt35xu512aba_fixups;
 #endif
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
+	nor->fixups = &macronix_octal_fixups;
+#endif /* SPI_FLASH_MACRONIX */
 }
 
 int spi_nor_scan(struct spi_nor *nor)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7ddc4ba2bf..8682368f2f 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -116,8 +116,16 @@
 #define XSR_RDY			BIT(7)	/* Ready */
 
 /* Used for Macronix and Winbond flashes. */
-#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
-#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */
+#define SPINOR_OP_EN4B			0xb7		/* Enter 4-byte mode */
+#define SPINOR_OP_EX4B			0xe9		/* Exit 4-byte mode */
+#define SPINOR_OP_RD_CR2		0x71		/* Read configuration register 2 */
+#define SPINOR_OP_WR_CR2		0x72		/* Write configuration register 2 */
+#define SPINOR_OP_MXIC_DTR_RD		0xee		/* Fast Read opcode in DTR mode */
+#define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
+#define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
+#define SPINOR_REG_MXIC_CR2_DC		0x00000300	/* For setting dummy cycles */
+#define SPINOR_REG_MXIC_DC_20		0x0		/* Setting dummy cycles to 20 */
+#define MXIC_MAX_DC			20		/* Maximum value of dummy cycles */
 
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR		0x17	/* Bank register write */
-- 
2.17.1

[PATCH v6 2/4] mtd: spi-nor-core: Adding different type of command extension in Soft Reset

[JaimeLiao]

Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
in the begging of probe.

Command extension type is not standardized across flash vendors in DTR mode.

For suiting different vendor flash devices, adding a flag to seperate types for
soft reset on boot.

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/Kconfig        | 7 +++++++
 drivers/mtd/spi/spi-nor-core.c | 7 ++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 1b2ef37e92..9b7d195770 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
 	 can support a type of operation in a much more refined way compared
 	 to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
 
+config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
+	bool "Command extension type is INVERT for Software Reset on boot"
+	default n
+	help
+	 Because of SFDP information can not be get before boot.
+	 So define command extension type is INVERT when Software Reset on boot only.
+
 config SPI_FLASH_SOFT_RESET
 	bool "Software Reset support for SPI NOR flashes"
 	default n
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 0a6550984b..2b6947cefc 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3661,7 +3661,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
 	enum spi_nor_cmd_ext ext;
 
 	ext = nor->cmd_ext_type;
-	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+	if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
+		nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
+		nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
+#endif /* SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT */
+	}
 
 	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
 			SPI_MEM_OP_NO_DUMMY,
-- 
2.17.1

[PATCH v6 3/4] mtd: spi-nor-core: Add support for Macronix Octal flash

[JaimeLiao]

Adding Macronix Octal flash for Octal DTR support.

The octaflash series can be divided into the following types:

MX25 series : Serial NOR Flash.
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW series : Support simultaneous Read-while-Write operation in multiple
               bank architecture. Read-while-write feature which means read
               data one bank while another bank is programing or erasing.

MX25LM : 3.0V Octal I/O
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf

MX25UM : 1.8V Octal I/O
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf

MX66LM : 3.0V Octal I/O with stacked die
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf

MX66UM : 1.8V Octal I/O with stacked die
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf

MX25LW : 3.0V Octal I/O with Read-while-Write
MX25UW : 1.8V Octal I/O with Read-while-Write
MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
MX66UW : 1.8V Octal I/O with Read-while-Write and stack die

About LW/UW series, please contact us freely if you have any
questions. For adding Octal NOR Flash IDs, we have validated
each Flash on plateform zynq-picozed.

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index cb3a08872d..5c13ea3a78 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
 	{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
-	{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66lm1g45g",    0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lm51245g",   0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lw51245g",   0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lm25645g",   0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66um1g45g",    0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw1g45g",    0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um51245g",   0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw51245g",   0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw51345g",   0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um25645g",   0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw25645g",   0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um25345g",   0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw25345g",   0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12845g",   0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12a45g",   0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12345g",   0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw6445g",    0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw6345g",    0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
 #endif
 
 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
-- 
2.17.1

[PATCH v6 4/4] mtd: spi-nor: Parse SFDP SCCR Map

[JaimeLiao]

Parse SCCR 22nd dword and check DTR Octal Mode Enable
Volatile bit for Octal DTR enable

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-core.c | 52 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h    |  1 +
 2 files changed, 53 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 2b6947cefc..14c33aea10 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -63,6 +63,10 @@ struct sfdp_parameter_header {
 #define SFDP_SECTOR_MAP_ID	0xff81	/* Sector Map Table */
 #define SFDP_SST_ID		0x01bf	/* Manufacturer specific Table */
 #define SFDP_PROFILE1_ID	0xff05	/* xSPI Profile 1.0 Table */
+#define SFDP_SCCR_MAP_ID	0xff87  /*
+					 * Status, Control and Configuration
+					 * Register Map.
+					 */
 
 #define SFDP_SIGNATURE		0x50444653U
 #define SFDP_JESD216_MAJOR	1
@@ -172,6 +176,9 @@ struct sfdp_header {
 #define PROFILE1_DWORD5_DUMMY_100MHZ		GENMASK(11, 7)
 #define PROFILE1_DUMMY_DEFAULT			20
 
+/* Status, Control and Configuration Register Map(SCCR) */
+#define SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE	BIT(31)
+
 struct sfdp_bfpt {
 	u32	dwords[BFPT_DWORD_MAX];
 };
@@ -2434,6 +2441,45 @@ out:
 	return ret;
 }
 
+/**
+ * spi_nor_parse_sccr() - Parse the Status, Control and Configuration Register
+ *			  Map.
+ * @nor:		  pointer to a 'struct spi_nor'
+ * @sccr_header:	  pointer to the 'struct sfdp_parameter_header' describing
+ * 			  the SCCR Map table length and version.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_parse_sccr(struct spi_nor *nor,
+			      const struct sfdp_parameter_header *sccr_header)
+{
+	u32 *table, opcode, addr;
+	size_t len;
+	int ret, i;
+	u8 dummy;
+
+	len = sccr_header->length * sizeof(*table);
+	table = kmalloc(len, GFP_KERNEL);
+	if (!table)
+		return -ENOMEM;
+
+	addr = SFDP_PARAM_HEADER_PTP(sccr_header);
+	ret = spi_nor_read_sfdp(nor, addr, len, table);
+	if (ret)
+		goto out;
+
+	/* Fix endianness of the table DWORDs. */
+	for (i = 0; i < sccr_header->length; i++)
+		table[i] = le32_to_cpu(table[i]);
+
+	if (FIELD_GET(SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE, table[22]))
+		nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
+
+out:
+	kfree(table);
+	return ret;
+}
+
 /**
  * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  * @nor:		pointer to a 'struct spi_nor'
@@ -2539,6 +2585,9 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
 		case SFDP_PROFILE1_ID:
 			err = spi_nor_parse_profile1(nor, param_header, params);
 			break;
+		case SFDP_SCCR_MAP_ID:
+			err = spi_nor_parse_sccr(nor, param_header);
+			break;
 
 		default:
 			break;
@@ -3584,6 +3633,9 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
 	      nor->write_proto == SNOR_PROTO_8_8_8_DTR))
 		return 0;
 
+	if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
+		return 0;
+
 	ret = nor->octal_dtr_enable(nor);
 	if (ret)
 		return ret;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8682368f2f..10c7b6e4c3 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -287,6 +287,7 @@ enum spi_nor_option_flags {
 	SNOR_F_USE_CLSR		= BIT(5),
 	SNOR_F_BROKEN_RESET	= BIT(6),
 	SNOR_F_SOFT_RESET	= BIT(7),
+	SNOR_F_IO_MODE_EN_VOLATILE = BIT(8),
 };
 
 struct spi_nor;
-- 
2.17.1

Re: [PATCH v6 1/4] mtd: spi-nor: macronix: add support for Macronix Octal

[Miquel Raynal]

Hi Jaime,

You made a typo on Jagan's address, you might need to resend.

The title does not look correct, maybe you miss a word after Octal. And
is it something Macronix specific? I believe this is generic and you
can drop "Macronix" (the second occurrence) from the title.

jaimeliao.tw@gmail.com wrote on Wed, 29 Dec 2021 13:56:17 +0800:

> Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding

When pointing to an upstream commit I think even in U-Boot the style
should be something like:
<12-digit hash> ("title of the commit")
which at least allows to know which commit we are talking about.

> Macronix flash in Octal DTR mode.

This first part of the commit log should be moved below.

> 
> Enable Octal DTR mode with 20 dummy cycles to allow running at the
> maximum supported frequency.
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> 
> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> ---
>  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
>  include/linux/mtd/spi-nor.h    | 12 ++++-
>  2 files changed, 93 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index d5d905fa5a..0a6550984b 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
>  };
>  #endif /* CONFIG_SPI_FLASH_MT35XU */
>  
> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> +/**
> + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.

This is very specific to Macronix I believe? Please just use a generic
description here.

> + * @nor:	pointer to a 'struct spi_nor'
> + *
> + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
> +{
> +	struct spi_mem_op op;
> +	int ret;
> +	u8 buf;
> +
> +	ret = write_enable(nor);
> +	if (ret)
> +		return ret;
> +
> +	buf = SPINOR_REG_MXIC_DC_20;
> +	op = (struct spi_mem_op)
> +		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> +			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> +			   SPI_MEM_OP_NO_DUMMY,
> +			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> +
> +	ret = spi_mem_exec_op(nor->spi, &op);
> +	if (ret)
> +		return ret;
> +
> +	ret = spi_nor_wait_till_ready(nor);
> +	if (ret)
> +		return ret;
> +
> +	nor->read_dummy = MXIC_MAX_DC;
> +	ret = write_enable(nor);
> +	if (ret)
> +		return ret;
> +
> +	buf = SPINOR_REG_MXIC_OPI_DTR_EN;
> +	op = (struct spi_mem_op)
> +		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> +			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
> +			   SPI_MEM_OP_NO_DUMMY,
> +			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> +
> +	ret = spi_mem_exec_op(nor->spi, &op);
> +	if (ret) {
> +		dev_err(nor->dev, "Failed to enable octal DTR mode\n");
> +		return ret;
> +	}
> +	nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
> +
> +	return 0;
> +}
> +
> +static void macronix_octal_default_init(struct spi_nor *nor)
> +{
> +	nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
> +}
> +
> +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
> +					 struct spi_nor_flash_parameter *params)
> +{
> +	/*
> +	 * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
> +	 * SPI_NOR_OCTAL_DTR_READ flag exists.
> +	 */
> +	if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
> +		params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
> +}
> +
> +static struct spi_nor_fixups macronix_octal_fixups = {
> +	.default_init = macronix_octal_default_init,
> +	.post_sfdp = macronix_octal_post_sfdp_fixup,
> +};
> +#endif /* CONFIG_SPI_FLASH_MACRONIX */
> +
>  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
>   * @nor:                 pointer to a 'struct spi_nor'
>   *
> @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
>  	if (!strcmp(nor->info->name, "mt35xu512aba"))
>  		nor->fixups = &mt35xu512aba_fixups;
>  #endif
> +
> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> +	nor->fixups = &macronix_octal_fixups;
> +#endif /* SPI_FLASH_MACRONIX */
>  }
>  
>  int spi_nor_scan(struct spi_nor *nor)
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 7ddc4ba2bf..8682368f2f 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -116,8 +116,16 @@
>  #define XSR_RDY			BIT(7)	/* Ready */
>  
>  /* Used for Macronix and Winbond flashes. */
> -#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
> -#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */
> +#define SPINOR_OP_EN4B			0xb7		/* Enter 4-byte mode */
> +#define SPINOR_OP_EX4B			0xe9		/* Exit 4-byte mode */
> +#define SPINOR_OP_RD_CR2		0x71		/* Read configuration register 2 */
> +#define SPINOR_OP_WR_CR2		0x72		/* Write configuration register 2 */
> +#define SPINOR_OP_MXIC_DTR_RD		0xee		/* Fast Read opcode in DTR mode */
> +#define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
> +#define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
> +#define SPINOR_REG_MXIC_CR2_DC		0x00000300	/* For setting dummy cycles */
> +#define SPINOR_REG_MXIC_DC_20		0x0		/* Setting dummy cycles to 20 */
> +#define MXIC_MAX_DC			20		/* Maximum value of dummy cycles */
>  
>  /* Used for Spansion flashes only. */
>  #define SPINOR_OP_BRWR		0x17	/* Bank register write */


Thanks,
Miquèl

Re: [PATCH v6 1/4] mtd: spi-nor: macronix: add support for Macronix Octal

[Tudor.Ambarus]

Hi,

On 12/29/21 7:56 AM, JaimeLiao wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
> Macronix flash in Octal DTR mode.
> 
> Enable Octal DTR mode with 20 dummy cycles to allow running at the
> maximum supported frequency.
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> 
> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> ---
>  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
>  include/linux/mtd/spi-nor.h    | 12 ++++-
>  2 files changed, 93 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index d5d905fa5a..0a6550984b 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
>  };
>  #endif /* CONFIG_SPI_FLASH_MT35XU */
> 
> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> +/**
> + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
> + * @nor:       pointer to a 'struct spi_nor'
> + *
> + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)

This method should be called just for the flashes that do not define the
JESD216 "Command Sequences to Change to Octal DDR (8D-8D-8D) mode" table.
Or where SFDP is skipped intentionally.

> +{
> +       struct spi_mem_op op;
> +       int ret;
> +       u8 buf;
> +
> +       ret = write_enable(nor);
> +       if (ret)
> +               return ret;
> +
> +       buf = SPINOR_REG_MXIC_DC_20;
> +       op = (struct spi_mem_op)
> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> +                          SPI_MEM_OP_NO_DUMMY,
> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> +
> +       ret = spi_mem_exec_op(nor->spi, &op);
> +       if (ret)
> +               return ret;
> +
> +       ret = spi_nor_wait_till_ready(nor);
> +       if (ret)
> +               return ret;
> +
> +       nor->read_dummy = MXIC_MAX_DC;
> +       ret = write_enable(nor);
> +       if (ret)
> +               return ret;
> +
> +       buf = SPINOR_REG_MXIC_OPI_DTR_EN;
> +       op = (struct spi_mem_op)
> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
> +                          SPI_MEM_OP_NO_DUMMY,
> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> +
> +       ret = spi_mem_exec_op(nor->spi, &op);
> +       if (ret) {
> +               dev_err(nor->dev, "Failed to enable octal DTR mode\n");
> +               return ret;
> +       }
> +       nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
> +
> +       return 0;
> +}
> +
> +static void macronix_octal_default_init(struct spi_nor *nor)

I think we should get rid of the default_init() hook, it messes how
the params are initialized, there's a spaghetti right now, it's very hard to
determine who initializes which params solely by reading the code. I would
advise to follow linux and use a late_init() hook where explicit octal dtr
enable method is required.


> +{
> +       nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
> +}
> +
> +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
> +                                        struct spi_nor_flash_parameter *params)
> +{
> +       /*
> +        * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
> +        * SPI_NOR_OCTAL_DTR_READ flag exists.
> +        */
> +       if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
> +               params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;

This confirms the spaghetti theory. This is not SFDP related, why do you use
the post_sfdp hook?

> +}
> +
> +static struct spi_nor_fixups macronix_octal_fixups = {
> +       .default_init = macronix_octal_default_init,
> +       .post_sfdp = macronix_octal_post_sfdp_fixup,
> +};
> +#endif /* CONFIG_SPI_FLASH_MACRONIX */
> +
>  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
>   * @nor:                 pointer to a 'struct spi_nor'
>   *
> @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
>         if (!strcmp(nor->info->name, "mt35xu512aba"))
>                 nor->fixups = &mt35xu512aba_fixups;
>  #endif
> +
> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
Not related to your patch, but ideally all the macronix code should reside
in a dedicated macronix.c driver.

Cheers,
ta

> +       nor->fixups = &macronix_octal_fixups;
> +#endif /* SPI_FLASH_MACRONIX */
>  }
> 
>  int spi_nor_scan(struct spi_nor *nor)
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 7ddc4ba2bf..8682368f2f 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -116,8 +116,16 @@
>  #define XSR_RDY                        BIT(7)  /* Ready */
> 
>  /* Used for Macronix and Winbond flashes. */
> -#define SPINOR_OP_EN4B         0xb7    /* Enter 4-byte mode */
> -#define SPINOR_OP_EX4B         0xe9    /* Exit 4-byte mode */
> +#define SPINOR_OP_EN4B                 0xb7            /* Enter 4-byte mode */
> +#define SPINOR_OP_EX4B                 0xe9            /* Exit 4-byte mode */
> +#define SPINOR_OP_RD_CR2               0x71            /* Read configuration register 2 */
> +#define SPINOR_OP_WR_CR2               0x72            /* Write configuration register 2 */
> +#define SPINOR_OP_MXIC_DTR_RD          0xee            /* Fast Read opcode in DTR mode */
> +#define SPINOR_REG_MXIC_CR2_MODE       0x00000000      /* For setting octal DTR mode */
> +#define SPINOR_REG_MXIC_OPI_DTR_EN     0x2             /* Enable Octal DTR */
> +#define SPINOR_REG_MXIC_CR2_DC         0x00000300      /* For setting dummy cycles */
> +#define SPINOR_REG_MXIC_DC_20          0x0             /* Setting dummy cycles to 20 */
> +#define MXIC_MAX_DC                    20              /* Maximum value of dummy cycles */
> 
>  /* Used for Spansion flashes only. */
>  #define SPINOR_OP_BRWR         0x17    /* Bank register write */
> --
> 2.17.1
> 

Re: [PATCH v6 3/4] mtd: spi-nor-core: Add support for Macronix Octal flash

[Tudor.Ambarus]

On 12/29/21 7:56 AM, JaimeLiao wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Adding Macronix Octal flash for Octal DTR support.
> 
> The octaflash series can be divided into the following types:
> 
> MX25 series : Serial NOR Flash.
> MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> LW/UW series : Support simultaneous Read-while-Write operation in multiple
>                bank architecture. Read-while-write feature which means read
>                data one bank while another bank is programing or erasing.
> 
> MX25LM : 3.0V Octal I/O
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> 
> MX25UM : 1.8V Octal I/O
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf
> 
> MX66LM : 3.0V Octal I/O with stacked die
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
> 
> MX66UM : 1.8V Octal I/O with stacked die
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
> 
> MX25LW : 3.0V Octal I/O with Read-while-Write
> MX25UW : 1.8V Octal I/O with Read-while-Write
> MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
> MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
> 
> About LW/UW series, please contact us freely if you have any
> questions. For adding Octal NOR Flash IDs, we have validated
> each Flash on plateform zynq-picozed.
> 
> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> ---
>  drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index cb3a08872d..5c13ea3a78 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
>         { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
> -       { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66lm1g45g",    0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25lm51245g",   0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25lw51245g",   0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25lm25645g",   0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66um1g45g",    0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66uw1g45g",    0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25um51245g",   0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw51245g",   0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw51345g",   0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25um25645g",   0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw25645g",   0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25um25345g",   0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw25345g",   0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw12845g",   0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw12a45g",   0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw12345g",   0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw6445g",    0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw6345g",    0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },

You need to at least specify which of these flashes support SFDP (describing the
supported tables) and which not, otherwise this will become a maintenance burden.
Best would be to dump all the SFDP tables for all the flashes.

My general feeling is that we should re-sync u-boot's SPI NOR subsystem with the
one on linux sooner or later, or the code will become harder to maintain.
Volunteers, thoughts? :)

Cheers,
ta

>  #endif
> 
>  #ifdef CONFIG_SPI_FLASH_STMICRO                /* STMICRO */
> --
> 2.17.1
> 

Re: [PATCH v6 1/4] mtd: spi-nor: macronix: add support for Macronix Octal

[liao jaime]

Hi Miquel


>
> Hi Jaime,
>
> You made a typo on Jagan's address, you might need to resend.
Yes your are right, I have re-send the cover letter to Jagan.

>
> The title does not look correct, maybe you miss a word after Octal. And
> is it something Macronix specific? I believe this is generic and you
> can drop "Macronix" (the second occurrence) from the title.
Ok got it.
>
> jaimeliao.tw@gmail.com wrote on Wed, 29 Dec 2021 13:56:17 +0800:
>
> > Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
>
> When pointing to an upstream commit I think even in U-Boot the style
> should be something like:
> <12-digit hash> ("title of the commit")
> which at least allows to know which commit we are talking about.
OK.

>
> > Macronix flash in Octal DTR mode.
>
> This first part of the commit log should be moved below.
>
> >
> > Enable Octal DTR mode with 20 dummy cycles to allow running at the
> > maximum supported frequency.
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> >
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
> >  include/linux/mtd/spi-nor.h    | 12 ++++-
> >  2 files changed, 93 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index d5d905fa5a..0a6550984b 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
> >  };
> >  #endif /* CONFIG_SPI_FLASH_MT35XU */
> >
> > +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > +/**
> > + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
>
> This is very specific to Macronix I believe? Please just use a generic
> description here.
Yes I will modify this part next patch.

>
> > + * @nor:     pointer to a 'struct spi_nor'
> > + *
> > + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> > + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> > + *
> > + * Return: 0 on success, -errno otherwise.
> > + */
> > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
> > +{
> > +     struct spi_mem_op op;
> > +     int ret;
> > +     u8 buf;
> > +
> > +     ret = write_enable(nor);
> > +     if (ret)
> > +             return ret;
> > +
> > +     buf = SPINOR_REG_MXIC_DC_20;
> > +     op = (struct spi_mem_op)
> > +             SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> > +                        SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> > +                        SPI_MEM_OP_NO_DUMMY,
> > +                        SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> > +
> > +     ret = spi_mem_exec_op(nor->spi, &op);
> > +     if (ret)
> > +             return ret;
> > +
> > +     ret = spi_nor_wait_till_ready(nor);
> > +     if (ret)
> > +             return ret;
> > +
> > +     nor->read_dummy = MXIC_MAX_DC;
> > +     ret = write_enable(nor);
> > +     if (ret)
> > +             return ret;
> > +
> > +     buf = SPINOR_REG_MXIC_OPI_DTR_EN;
> > +     op = (struct spi_mem_op)
> > +             SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> > +                        SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
> > +                        SPI_MEM_OP_NO_DUMMY,
> > +                        SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> > +
> > +     ret = spi_mem_exec_op(nor->spi, &op);
> > +     if (ret) {
> > +             dev_err(nor->dev, "Failed to enable octal DTR mode\n");
> > +             return ret;
> > +     }
> > +     nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
> > +
> > +     return 0;
> > +}
> > +
> > +static void macronix_octal_default_init(struct spi_nor *nor)
> > +{
> > +     nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
> > +}
> > +
> > +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
> > +                                      struct spi_nor_flash_parameter *params)
> > +{
> > +     /*
> > +      * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
> > +      * SPI_NOR_OCTAL_DTR_READ flag exists.
> > +      */
> > +     if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
> > +             params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
> > +}
> > +
> > +static struct spi_nor_fixups macronix_octal_fixups = {
> > +     .default_init = macronix_octal_default_init,
> > +     .post_sfdp = macronix_octal_post_sfdp_fixup,
> > +};
> > +#endif /* CONFIG_SPI_FLASH_MACRONIX */
> > +
> >  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
> >   * @nor:                 pointer to a 'struct spi_nor'
> >   *
> > @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
> >       if (!strcmp(nor->info->name, "mt35xu512aba"))
> >               nor->fixups = &mt35xu512aba_fixups;
> >  #endif
> > +
> > +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > +     nor->fixups = &macronix_octal_fixups;
> > +#endif /* SPI_FLASH_MACRONIX */
> >  }
> >
> >  int spi_nor_scan(struct spi_nor *nor)
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index 7ddc4ba2bf..8682368f2f 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -116,8 +116,16 @@
> >  #define XSR_RDY                      BIT(7)  /* Ready */
> >
> >  /* Used for Macronix and Winbond flashes. */
> > -#define SPINOR_OP_EN4B               0xb7    /* Enter 4-byte mode */
> > -#define SPINOR_OP_EX4B               0xe9    /* Exit 4-byte mode */
> > +#define SPINOR_OP_EN4B                       0xb7            /* Enter 4-byte mode */
> > +#define SPINOR_OP_EX4B                       0xe9            /* Exit 4-byte mode */
> > +#define SPINOR_OP_RD_CR2             0x71            /* Read configuration register 2 */
> > +#define SPINOR_OP_WR_CR2             0x72            /* Write configuration register 2 */
> > +#define SPINOR_OP_MXIC_DTR_RD                0xee            /* Fast Read opcode in DTR mode */
> > +#define SPINOR_REG_MXIC_CR2_MODE     0x00000000      /* For setting octal DTR mode */
> > +#define SPINOR_REG_MXIC_OPI_DTR_EN   0x2             /* Enable Octal DTR */
> > +#define SPINOR_REG_MXIC_CR2_DC               0x00000300      /* For setting dummy cycles */
> > +#define SPINOR_REG_MXIC_DC_20                0x0             /* Setting dummy cycles to 20 */
> > +#define MXIC_MAX_DC                  20              /* Maximum value of dummy cycles */
> >
> >  /* Used for Spansion flashes only. */
> >  #define SPINOR_OP_BRWR               0x17    /* Bank register write */
>
>
> Thanks,
> Miquèl

Thanks
Jaime

Re: [PATCH v6 1/4] mtd: spi-nor: macronix: add support for Macronix Octal

[liao jaime]

Hi Tudor


>
> Hi,
>
> On 12/29/21 7:56 AM, JaimeLiao wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
> > Macronix flash in Octal DTR mode.
> >
> > Enable Octal DTR mode with 20 dummy cycles to allow running at the
> > maximum supported frequency.
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> >
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
> >  include/linux/mtd/spi-nor.h    | 12 ++++-
> >  2 files changed, 93 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index d5d905fa5a..0a6550984b 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
> >  };
> >  #endif /* CONFIG_SPI_FLASH_MT35XU */
> >
> > +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > +/**
> > + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
> > + * @nor:       pointer to a 'struct spi_nor'
> > + *
> > + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> > + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> > + *
> > + * Return: 0 on success, -errno otherwise.
> > + */
> > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
>
> This method should be called just for the flashes that do not define the
> JESD216 "Command Sequences to Change to Octal DDR (8D-8D-8D) mode" table.
> Or where SFDP is skipped intentionally.

I think Octal DTR enable method have been defined by manufacturers.
It would be better if the method could be parce from SFDP.
But I prefer to follow the existing rules for adding the flashes which
have been output but not be support in uboot.
>
> > +{
> > +       struct spi_mem_op op;
> > +       int ret;
> > +       u8 buf;
> > +
> > +       ret = write_enable(nor);
> > +       if (ret)
> > +               return ret;
> > +
> > +       buf = SPINOR_REG_MXIC_DC_20;
> > +       op = (struct spi_mem_op)
> > +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> > +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> > +                          SPI_MEM_OP_NO_DUMMY,
> > +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> > +
> > +       ret = spi_mem_exec_op(nor->spi, &op);
> > +       if (ret)
> > +               return ret;
> > +
> > +       ret = spi_nor_wait_till_ready(nor);
> > +       if (ret)
> > +               return ret;
> > +
> > +       nor->read_dummy = MXIC_MAX_DC;
> > +       ret = write_enable(nor);
> > +       if (ret)
> > +               return ret;
> > +
> > +       buf = SPINOR_REG_MXIC_OPI_DTR_EN;
> > +       op = (struct spi_mem_op)
> > +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> > +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
> > +                          SPI_MEM_OP_NO_DUMMY,
> > +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> > +
> > +       ret = spi_mem_exec_op(nor->spi, &op);
> > +       if (ret) {
> > +               dev_err(nor->dev, "Failed to enable octal DTR mode\n");
> > +               return ret;
> > +       }
> > +       nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
> > +
> > +       return 0;
> > +}
> > +
> > +static void macronix_octal_default_init(struct spi_nor *nor)
>
> I think we should get rid of the default_init() hook, it messes how
> the params are initialized, there's a spaghetti right now, it's very hard to
> determine who initializes which params solely by reading the code. I would
> advise to follow linux and use a late_init() hook where explicit octal dtr
> enable method is required.
Sure it is a good idea.
I hope U-boot could have more similar architecture with Linux kernel.
>
>
> > +{
> > +       nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
> > +}
> > +
> > +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
> > +                                        struct spi_nor_flash_parameter *params)
> > +{
> > +       /*
> > +        * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
> > +        * SPI_NOR_OCTAL_DTR_READ flag exists.
> > +        */
> > +       if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
> > +               params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
>
> This confirms the spaghetti theory. This is not SFDP related, why do you use
> the post_sfdp hook?
Because of SPI_NOR_OCTAL_DTR_PP is not existing in U-boot.
I will take other suitable method to enable it next patch.
>
> > +}
> > +
> > +static struct spi_nor_fixups macronix_octal_fixups = {
> > +       .default_init = macronix_octal_default_init,
> > +       .post_sfdp = macronix_octal_post_sfdp_fixup,
> > +};
> > +#endif /* CONFIG_SPI_FLASH_MACRONIX */
> > +
> >  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
> >   * @nor:                 pointer to a 'struct spi_nor'
> >   *
> > @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
> >         if (!strcmp(nor->info->name, "mt35xu512aba"))
> >                 nor->fixups = &mt35xu512aba_fixups;
> >  #endif
> > +
> > +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> Not related to your patch, but ideally all the macronix code should reside
> in a dedicated macronix.c driver.
Sure, but all manufacturer IDs are gather in spi-nor-ids.c now.
>
> Cheers,
> ta
>
> > +       nor->fixups = &macronix_octal_fixups;
> > +#endif /* SPI_FLASH_MACRONIX */
> >  }
> >
> >  int spi_nor_scan(struct spi_nor *nor)
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index 7ddc4ba2bf..8682368f2f 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -116,8 +116,16 @@
> >  #define XSR_RDY                        BIT(7)  /* Ready */
> >
> >  /* Used for Macronix and Winbond flashes. */
> > -#define SPINOR_OP_EN4B         0xb7    /* Enter 4-byte mode */
> > -#define SPINOR_OP_EX4B         0xe9    /* Exit 4-byte mode */
> > +#define SPINOR_OP_EN4B                 0xb7            /* Enter 4-byte mode */
> > +#define SPINOR_OP_EX4B                 0xe9            /* Exit 4-byte mode */
> > +#define SPINOR_OP_RD_CR2               0x71            /* Read configuration register 2 */
> > +#define SPINOR_OP_WR_CR2               0x72            /* Write configuration register 2 */
> > +#define SPINOR_OP_MXIC_DTR_RD          0xee            /* Fast Read opcode in DTR mode */
> > +#define SPINOR_REG_MXIC_CR2_MODE       0x00000000      /* For setting octal DTR mode */
> > +#define SPINOR_REG_MXIC_OPI_DTR_EN     0x2             /* Enable Octal DTR */
> > +#define SPINOR_REG_MXIC_CR2_DC         0x00000300      /* For setting dummy cycles */
> > +#define SPINOR_REG_MXIC_DC_20          0x0             /* Setting dummy cycles to 20 */
> > +#define MXIC_MAX_DC                    20              /* Maximum value of dummy cycles */
> >
> >  /* Used for Spansion flashes only. */
> >  #define SPINOR_OP_BRWR         0x17    /* Bank register write */
> > --
> > 2.17.1
> >
>

Thanks
Jaime

Re: [PATCH v6 1/4] mtd: spi-nor: macronix: add support for Macronix Octal

[Pratyush Yadav]

On 03/01/22 10:38AM, Tudor.Ambarus@microchip.com wrote:
> Hi,
> 
> On 12/29/21 7:56 AM, JaimeLiao wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
> > Macronix flash in Octal DTR mode.
> > 
> > Enable Octal DTR mode with 20 dummy cycles to allow running at the
> > maximum supported frequency.
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> > 
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
> >  include/linux/mtd/spi-nor.h    | 12 ++++-
> >  2 files changed, 93 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index d5d905fa5a..0a6550984b 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
> >  };
> >  #endif /* CONFIG_SPI_FLASH_MT35XU */
> > 
> > +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > +/**
> > + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
> > + * @nor:       pointer to a 'struct spi_nor'
> > + *
> > + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> > + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> > + *
> > + * Return: 0 on success, -errno otherwise.
> > + */
> > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
> 
> This method should be called just for the flashes that do not define the
> JESD216 "Command Sequences to Change to Octal DDR (8D-8D-8D) mode" table.
> Or where SFDP is skipped intentionally.

When adding Octal DTR support to kernel and U-Boot SPI NOR, I did 
consider parsing this table. But I dropped the idea at the time because 
the table guarantees to only use 20 dummy cycles for reads and operation 
at 100 MHz (or higher if supported). But this does not guarantee that we 
can run the flash at the maximum speed possible. For example, for 
Spansion S28 flash we can only go up to 166 MHz with 20 dummy cycles. 
For getting 200 MHz we need at least 23 dummy cycles.

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

Re: [PATCH v6 3/4] mtd: spi-nor-core: Add support for Macronix Octal flash

[Pratyush Yadav]

On 03/01/22 10:47AM, Tudor.Ambarus@microchip.com wrote:
> On 12/29/21 7:56 AM, JaimeLiao wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > Adding Macronix Octal flash for Octal DTR support.
> > 
> > The octaflash series can be divided into the following types:
> > 
> > MX25 series : Serial NOR Flash.
> > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> > LW/UW series : Support simultaneous Read-while-Write operation in multiple
> >                bank architecture. Read-while-write feature which means read
> >                data one bank while another bank is programing or erasing.
> > 
> > MX25LM : 3.0V Octal I/O
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> > 
> > MX25UM : 1.8V Octal I/O
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf
> > 
> > MX66LM : 3.0V Octal I/O with stacked die
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
> > 
> > MX66UM : 1.8V Octal I/O with stacked die
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
> > 
> > MX25LW : 3.0V Octal I/O with Read-while-Write
> > MX25UW : 1.8V Octal I/O with Read-while-Write
> > MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
> > MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
> > 
> > About LW/UW series, please contact us freely if you have any
> > questions. For adding Octal NOR Flash IDs, we have validated
> > each Flash on plateform zynq-picozed.
> > 
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++-
> >  1 file changed, 21 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> > index cb3a08872d..5c13ea3a78 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = {
> >         { INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> >         { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
> >         { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
> > -       { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66lm1g45g",    0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25lm51245g",   0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25lw51245g",   0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25lm25645g",   0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66um1g45g",    0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66uw1g45g",    0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25um51245g",   0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw51245g",   0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw51345g",   0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25um25645g",   0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw25645g",   0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25um25345g",   0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw25345g",   0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw12845g",   0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw12a45g",   0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw12345g",   0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw6445g",    0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw6345g",    0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> 
> You need to at least specify which of these flashes support SFDP (describing the
> supported tables) and which not, otherwise this will become a maintenance burden.
> Best would be to dump all the SFDP tables for all the flashes.
> 
> My general feeling is that we should re-sync u-boot's SPI NOR subsystem with the
> one on linux sooner or later, or the code will become harder to maintain.
> Volunteers, thoughts? :)

I think that would be very nice indeed. But unfortunately I do not have 
any bandwidth to spare right now for this.

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

Re: [PATCH v6 3/4] mtd: spi-nor-core: Add support for Macronix Octal flash

[liao jaime]

Hi Pratyush


>
> On 03/01/22 10:47AM, Tudor.Ambarus@microchip.com wrote:
> > On 12/29/21 7:56 AM, JaimeLiao wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > Adding Macronix Octal flash for Octal DTR support.
> > >
> > > The octaflash series can be divided into the following types:
> > >
> > > MX25 series : Serial NOR Flash.
> > > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> > > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> > > LW/UW series : Support simultaneous Read-while-Write operation in multiple
> > >                bank architecture. Read-while-write feature which means read
> > >                data one bank while another bank is programing or erasing.
> > >
> > > MX25LM : 3.0V Octal I/O
> > >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> > >
> > > MX25UM : 1.8V Octal I/O
> > >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf
> > >
> > > MX66LM : 3.0V Octal I/O with stacked die
> > >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
> > >
> > > MX66UM : 1.8V Octal I/O with stacked die
> > >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
> > >
> > > MX25LW : 3.0V Octal I/O with Read-while-Write
> > > MX25UW : 1.8V Octal I/O with Read-while-Write
> > > MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
> > > MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
> > >
> > > About LW/UW series, please contact us freely if you have any
> > > questions. For adding Octal NOR Flash IDs, we have validated
> > > each Flash on plateform zynq-picozed.
> > >
> > > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > > ---
> > >  drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++-
> > >  1 file changed, 21 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> > > index cb3a08872d..5c13ea3a78 100644
> > > --- a/drivers/mtd/spi/spi-nor-ids.c
> > > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > > @@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = {
> > >         { INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > >         { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
> > >         { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
> > > -       { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx66lm1g45g",    0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25lm51245g",   0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25lw51245g",   0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25lm25645g",   0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx66um1g45g",    0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx66uw1g45g",    0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25um51245g",   0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw51245g",   0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw51345g",   0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25um25645g",   0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw25645g",   0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25um25345g",   0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw25345g",   0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw12845g",   0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw12a45g",   0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw12345g",   0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw6445g",    0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > > +       { INFO("mx25uw6345g",    0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> >
> > You need to at least specify which of these flashes support SFDP (describing the
> > supported tables) and which not, otherwise this will become a maintenance burden.
> > Best would be to dump all the SFDP tables for all the flashes.
> >
> > My general feeling is that we should re-sync u-boot's SPI NOR subsystem with the
> > one on linux sooner or later, or the code will become harder to maintain.
> > Volunteers, thoughts? :)
>
> I think that would be very nice indeed. But unfortunately I do not have
> any bandwidth to spare right now for this.
Following linux kernel, I will add SFDP table in commit log next patch revision.
Can I gather all flash SFDP tables in one commit log?
Because of 22 octal flash IDs should be add in totally.

>
> --
> Regards,
> Pratyush Yadav
> Texas Instruments Inc.

Thanks
Jaime