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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT068.mail.protection.outlook.com (10.13.175.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4867.7 via Frontend Transport; Thu, 6 Jan 2022 16:30:58 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 6 Jan 2022 10:30:57 -0600 From: Mario Limonciello To: Subject: [PATCH v4 3/3] drm/amd/display: Use requested power state to avoid HPD WA during s0ix Date: Thu, 6 Jan 2022 10:30:54 -0600 Message-ID: <20220106163054.13781-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220106163054.13781-1-mario.limonciello@amd.com> References: <20220106163054.13781-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ed221852-31a9-4ab5-6b19-08d9d131ebc3 X-MS-TrafficTypeDiagnostic: MWHPR12MB1680:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(40470700002)(36840700001)(46966006)(47076005)(966005)(508600001)(316002)(2906002)(54906003)(8676002)(6916009)(7696005)(36756003)(36860700001)(82310400004)(426003)(70206006)(86362001)(1076003)(16526019)(83380400001)(26005)(6666004)(40460700001)(356005)(2616005)(336012)(186003)(4326008)(5660300002)(70586007)(8936002)(81166007)(44832011)(32563001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2022 16:30:58.7285 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed221852-31a9-4ab5-6b19-08d9d131ebc3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1680 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qingqing Zhuo , Scott Bruce , Mario Limonciello , Chris Hixon , spasswolf@web.de Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" The WA from commit 5965280abd30 ("drm/amd/display: Apply w/a for hard hang on HPD") causes a regression in s0ix where the system will fail to resume properly. This may be because an HPD was active the last time clocks were updated but clocks didn't get updated again during s0ix. So add an extra call to update clocks as part of the suspend routine: dm_suspend->dc_set_power_state->clk_mgr_optimize_pwr_state In case HPD is set during this time, also check if the call happened during suspend to allow overriding the WA. Cc: Qingqing Zhuo Reported-by: Scott Bruce Reported-by: Chris Hixon Reported-by: spasswolf@web.de Link: https://bugzilla.kernel.org/show_bug.cgi?id=215436 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1821 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1852 Fixes: 5965280abd30 ("drm/amd/display: Apply w/a for hard hang on HPD") Fixes: 1bd3bc745e7f ("drm/amd/display: Extend w/a for hard hang on HPD to dcn20") Signed-off-by: Mario Limonciello --- changes from v3->v4: * Move into new function * Explicitly check that current_state is active for safety * Change metadata from BugLink to Link changes from v2->v3: * stop depending on adev, get value of power state from display core changes from v1->v2: * Add fallthrough statement * Extend case to check if call was explicitly in s0ix since #1852 showed hpd_state can be set at this time too * Adjust commit message and title * Add extra commit and bug fixed to metadata drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 4 ++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 20974829f304..d2e1938555dc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -129,6 +129,10 @@ static bool check_really_safe_to_lower(struct dc *dc, struct dc_state *context) if (display_count > 0) return false; + if (dc->current_state && + dc->current_state->power_state == DC_ACPI_CM_POWER_STATE_D3) + return true; + for (irq_src = DC_IRQ_SOURCE_HPD1; irq_src <= DC_IRQ_SOURCE_HPD5; irq_src++) { hpd_state = dc_get_hpd_state_dcn21(dc->res_pool->irqs, irq_src); if (hpd_state) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8edbb6c70512..716e055a61c9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3302,6 +3302,9 @@ void dc_set_power_state( } break; + case DC_ACPI_CM_POWER_STATE_D3: + clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); + fallthrough; default: ASSERT(dc->current_state->stream_count == 0); /* Zero out the current context so that on resume we start with -- 2.25.1