From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17885C433EF for ; Thu, 6 Jan 2022 17:20:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241690AbiAFRU6 (ORCPT ); Thu, 6 Jan 2022 12:20:58 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:45684 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241633AbiAFRUz (ORCPT ); Thu, 6 Jan 2022 12:20:55 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 8573DCE265F; Thu, 6 Jan 2022 17:20:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA2A7C36AE3; Thu, 6 Jan 2022 17:20:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641489651; bh=6hGkG8sCapfiKE5GsYhVlbIB0Sw85pSQfdIq/VJCMOY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=j90KTY3hiwGxIaKHuOMWXUbepPuhljaZHQEr8eV1Z4BaoMm5W6fMj8WaRMbAcZkmm UO0mz98oaA8ZOqWRE9BH4dlc1gcoMvFJGN4n8qhQT5l9wbr1NvogdQauJKR3FO35HJ FvOQr4FdWSbD7imtIKiKjaKY2Ym6iwABwomYEPCrviGjeFz4C0LIj6+rnKO7URsj2W 2etjKhUdx7sz1b23A9Gr5ku3MRFmJUj0zm2EpDyBBGBpPhSgEOKabx/pg02vq8NESd MpPeEPD2eDjMCfexrPV1s2ymNOwP6qEQPAXoOpWLVj7Mhz0l1zs0BeONKiSbB6rcr9 sdw+mwav3CB5A== Date: Thu, 6 Jan 2022 18:20:44 +0100 From: Marek =?UTF-8?B?QmVow7pu?= To: Marc Zyngier Cc: Pali =?UTF-8?B?Um9ow6Fy?= , Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Message-ID: <20220106182044.3ff0828c@thinkpad> In-Reply-To: <877dbcvngf.wl-maz@kernel.org> References: <20220105150239.9628-1-pali@kernel.org> <20220105150239.9628-11-pali@kernel.org> <87bl0ovq7f.wl-maz@kernel.org> <20220106154447.aie6taiuvav5wu6y@pali> <878rvsvoyo.wl-maz@kernel.org> <20220106162047.vqykmygs75eimfgy@pali> <877dbcvngf.wl-maz@kernel.org> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 06 Jan 2022 16:27:44 +0000 Marc Zyngier wrote: > On Thu, 06 Jan 2022 16:20:47 +0000, > Pali Roh=C3=A1r wrote: > >=20 > > On Thursday 06 January 2022 15:55:11 Marc Zyngier wrote: =20 > > > On Thu, 06 Jan 2022 15:44:47 +0000, > > > Pali Roh=C3=A1r wrote: =20 > > > >=20 > > > > On Thursday 06 January 2022 15:28:20 Marc Zyngier wrote: =20 > > > > > On Wed, 05 Jan 2022 15:02:38 +0000, > > > > > Pali Roh=C3=A1r wrote: =20 > > > > > >=20 > > > > > > This adds support for legacy INTx interrupts received from othe= r PCIe > > > > > > devices and which are reported by a new INTx irq chip. > > > > > >=20 > > > > > > With this change, kernel can distinguish between INTA, INTB, IN= TC and INTD > > > > > > interrupts. > > > > > >=20 > > > > > > Note that for this support, device tree files has to be properl= y adjusted > > > > > > to provide "interrupts" or "interrupts-extended" property with = intx > > > > > > interrupt source, "interrupt-names" property with "intx" string= and also > > > > > > 'interrupt-controller' subnode must be defined. > > > > > >=20 > > > > > > If device tree files do not provide these nodes then driver wou= ld work as > > > > > > before. > > > > > >=20 > > > > > > Signed-off-by: Pali Roh=C3=A1r > > > > > > --- > > > > > > drivers/pci/controller/pci-mvebu.c | 182 +++++++++++++++++++++= ++++++-- > > > > > > 1 file changed, 174 insertions(+), 8 deletions(-) > > > > > >=20 > > > > > > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/c= ontroller/pci-mvebu.c > > > > > > index 1e90ab888075..04bcdd7b7a6d 100644 > > > > > > --- a/drivers/pci/controller/pci-mvebu.c > > > > > > +++ b/drivers/pci/controller/pci-mvebu.c > > > > > > @@ -54,9 +54,10 @@ > > > > > > PCIE_CONF_ADDR_EN) > > > > > > #define PCIE_CONF_DATA_OFF 0x18fc > > > > > > #define PCIE_INT_CAUSE_OFF 0x1900 > > > > > > +#define PCIE_INT_UNMASK_OFF 0x1910 > > > > > > +#define PCIE_INT_INTX(i) BIT(24+i) > > > > > > #define PCIE_INT_PM_PME BIT(28) > > > > > > -#define PCIE_MASK_OFF 0x1910 > > > > > > -#define PCIE_MASK_ENABLE_INTS 0x0f000000 > > > > > > +#define PCIE_INT_ALL_MASK GENMASK(31, 0) > > > > > > #define PCIE_CTRL_OFF 0x1a00 > > > > > > #define PCIE_CTRL_X1_MODE 0x0001 > > > > > > #define PCIE_CTRL_RC_MODE BIT(1) > > > > > > @@ -110,6 +111,10 @@ struct mvebu_pcie_port { > > > > > > struct mvebu_pcie_window iowin; > > > > > > u32 saved_pcie_stat; > > > > > > struct resource regs; > > > > > > + struct irq_domain *intx_irq_domain; > > > > > > + struct irq_chip intx_irq_chip; =20 > > > > >=20 > > > > > Why is this structure per port? It really should be global. Print= ing > > > > > the port number in the name isn't enough of a reason. =20 > > > >=20 > > > > Because each port has its own independent set of INTA-INTD > > > > interrupts. =20 > > >=20 > > > That doesn't warrant a copy of an irq_chip structure that contains the > > > exact same callbacks, and only differs by *a string*. And the use of > > > this string is only to end-up in /proc/interrupts, which is totally > > > pointless. > > > =20 > > > > =20 > > > > > > + raw_spinlock_t irq_lock; > > > > > > + int intx_irq; > > > > > > }; > > > > > > =20 > > > > > > static inline void mvebu_writel(struct mvebu_pcie_port *port, = u32 val, u32 reg) > > > > > > @@ -235,7 +240,7 @@ static void mvebu_pcie_setup_wins(struct mv= ebu_pcie_port *port) > > > > > > =20 > > > > > > static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) > > > > > > { > > > > > > - u32 ctrl, lnkcap, cmd, dev_rev, mask; > > > > > > + u32 ctrl, lnkcap, cmd, dev_rev, unmask; > > > > > > =20 > > > > > > /* Setup PCIe controller to Root Complex mode. */ > > > > > > ctrl =3D mvebu_readl(port, PCIE_CTRL_OFF); > > > > > > @@ -288,10 +293,30 @@ static void mvebu_pcie_setup_hw(struct mv= ebu_pcie_port *port) > > > > > > /* Point PCIe unit MBUS decode windows to DRAM space. */ > > > > > > mvebu_pcie_setup_wins(port); > > > > > > =20 > > > > > > - /* Enable interrupt lines A-D. */ > > > > > > - mask =3D mvebu_readl(port, PCIE_MASK_OFF); > > > > > > - mask |=3D PCIE_MASK_ENABLE_INTS; > > > > > > - mvebu_writel(port, mask, PCIE_MASK_OFF); > > > > > > + /* Mask all interrupt sources. */ > > > > > > + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); > > > > > > + > > > > > > + /* Clear all interrupt causes. */ > > > > > > + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); > > > > > > + > > > > > > + if (port->intx_irq <=3D 0) { > > > > > > + /* > > > > > > + * When neither "summary" interrupt, nor "intx" interrupt was > > > > > > + * specified in DT then unmask all legacy INTx interrupts as= in > > > > > > + * this case driver does not provide a way for masking and > > > > > > + * unmasking of individual legacy INTx interrupts. In this c= ase > > > > > > + * all interrupts, including legacy INTx are reported via one > > > > > > + * shared GIC source and therefore kernel cannot distinguish > > > > > > + * which individual legacy INTx was triggered. These interru= pts > > > > > > + * are shared, so it should not cause any issue. Just > > > > > > + * performance penalty as every PCIe interrupt handler needs= to > > > > > > + * be called when some interrupt is triggered. > > > > > > + */ > > > > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > > > > + unmask |=3D PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | > > > > > > + PCIE_INT_INTX(2) | PCIE_INT_INTX(3); > > > > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); =20 > > > > >=20 > > > > > Maybe worth printing a warning here, so that the user knows they = are > > > > > on thin ice. =20 > > > >=20 > > > > Ok. I can add it here. Anyway, this is default current state without > > > > this patch. > > > > =20 > > > > > > + } > > > > > > } > > > > > > =20 > > > > > > static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mve= bu_pcie *pcie, > > > > > > @@ -924,6 +949,109 @@ static struct pci_ops mvebu_pcie_ops =3D { > > > > > > .write =3D mvebu_pcie_wr_conf, > > > > > > }; > > > > > > =20 > > > > > > +static void mvebu_pcie_intx_irq_mask(struct irq_data *d) > > > > > > +{ > > > > > > + struct mvebu_pcie_port *port =3D d->domain->host_data; > > > > > > + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > > > > > > + unsigned long flags; > > > > > > + u32 unmask; > > > > > > + > > > > > > + raw_spin_lock_irqsave(&port->irq_lock, flags); > > > > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > > > > + unmask &=3D ~PCIE_INT_INTX(hwirq); > > > > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > > > > > > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > > > > > > +} > > > > > > + > > > > > > +static void mvebu_pcie_intx_irq_unmask(struct irq_data *d) > > > > > > +{ > > > > > > + struct mvebu_pcie_port *port =3D d->domain->host_data; > > > > > > + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > > > > > > + unsigned long flags; > > > > > > + u32 unmask; > > > > > > + > > > > > > + raw_spin_lock_irqsave(&port->irq_lock, flags); > > > > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > > > > + unmask |=3D PCIE_INT_INTX(hwirq); > > > > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > > > > > > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > > > > > > +} > > > > > > + > > > > > > +static int mvebu_pcie_intx_irq_map(struct irq_domain *h, > > > > > > + unsigned int virq, irq_hw_number_t hwirq) > > > > > > +{ > > > > > > + struct mvebu_pcie_port *port =3D h->host_data; > > > > > > + > > > > > > + irq_set_status_flags(virq, IRQ_LEVEL); > > > > > > + irq_set_chip_and_handler(virq, &port->intx_irq_chip, handle_l= evel_irq); > > > > > > + irq_set_chip_data(virq, port); > > > > > > + > > > > > > + return 0; > > > > > > +} > > > > > > + > > > > > > +static const struct irq_domain_ops mvebu_pcie_intx_irq_domain_= ops =3D { > > > > > > + .map =3D mvebu_pcie_intx_irq_map, > > > > > > + .xlate =3D irq_domain_xlate_onecell, > > > > > > +}; > > > > > > + > > > > > > +static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *= port) > > > > > > +{ > > > > > > + struct device *dev =3D &port->pcie->pdev->dev; > > > > > > + struct device_node *pcie_intc_node; > > > > > > + > > > > > > + raw_spin_lock_init(&port->irq_lock); > > > > > > + > > > > > > + port->intx_irq_chip.name =3D devm_kasprintf(dev, GFP_KERNEL, > > > > > > + "mvebu-%s-INTx", > > > > > > + port->name); =20 > > > > >=20 > > > > > That's exactly what I really don't want to see. It prevents shari= ng of > > > > > the irq_chip structure, and gets in the way of making it const in= the > > > > > future. Yes, I know that some drivers do that. I can't fix those, > > > > > because /proc/interrupts is ABI. But I really don't want to see m= ore > > > > > of these. =20 > > > >=20 > > > > Well, I do not understand why it should be shared and with who. HW = has N > > > > independent IRQ chips for legacy interrupts. And each one will be > > > > specified in DT per HW layout / design. =20 > > >=20 > > > If you have multiple ports, all the ports can share the irq_chip > > > structure. Actually scratch that. They *MUST* share the structure. The > > > only reason you're not sharing it is to be able to print this useless > > > string in /proc/interrupts. =20 > >=20 > > What is the point of sharing one irq chip if HW has N independent irq > > chips (for legacy interrupts)? I do not catch it yet. And I do not care > > here for /proc/interrupts, so also I have not caught what do you mean be > > last sentence with "the only reason". > >=20 > > And I still do not see how it could even work to have just one irq chip > > and one irq domain as each irq domain needs to know to which port it > > belongs, so it can mask/unmask interrupts from correct port. Also > > initialization of domain is taking DT node and for each port it is > > different. > >=20 > > So I'm somehow confused here... > >=20 > > The improvement in this patch is to be able to mask INTA interrupts on > > port 1 and let INTA interrupts unmasked on port 2 if there drivers are > > interested only for interrupts from device connected to port 2. > >=20 > > And if all interrupts are going to be shared (again) then it does not > > solve any problem. =20 >=20 > You are completely missing my point. I'm talking about data > structures, you're talking about interrupts. You have this: >=20 > struct mvebu_pcie_port { > // Tons of stuff > struct irq_chip intx_chip; > }; >=20 > What I want you to do is: >=20 > struct mvebu_pcie_port { > // Tons of stuff > }; >=20 > static struct irq_chip intx_chip =3D { > .name =3D "INTx", > .irq_mask =3D mvebu_pcie_intx_irq_mask, > .irq_unmask =3D mvebu_pcie_intx_irq_unmask; > }; >=20 > That's it. No more, no less. >=20 > M. >=20 Hmm, but struct irq_chip contains a dynamic member, struct device *parent_device; Isn't that used? Or are you planning to kill it? Marek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 223ECC433EF for ; Thu, 6 Jan 2022 17:22:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9lXXveX7pqHqP1sjIPbyO3cTgyMdLQCV/cVHJ17GaEE=; b=DsLu0YZSaiGAzj gSmJV4ke1KuyajLDhKjVwyapMUkVcU0B7qDhd1CK0+4PtLs4fuo5jnpu8O8O5V2BsVG7VmOJsRiZO O8JJRG92GWS7SdtpEobpOUgvq5vYY3XEd3A8J1xm0HcrJhqGFt2byjgL7JFfPlhL5spXCODmX1lVc y+r7NYFZankIuMqbtBqc+r+AOgJwRc8Ol9DN0CUTyRL6XWQxa8+sqYpIwQ7pRtT+e/DL157KRNlHz UbkNGif7rNC9dx2BKeA4CgWSV0oVSkQdUEx2jPiIQmL4YUVdBf7KkF4+ED1pFwobCM4mbziz6vOXy DpQh+nXk/zLV1nGAYFpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5WRd-000n9h-67; Thu, 06 Jan 2022 17:20:57 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n5WRZ-000n8q-KY for linux-arm-kernel@lists.infradead.org; Thu, 06 Jan 2022 17:20:55 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 71B9661CFB; Thu, 6 Jan 2022 17:20:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA2A7C36AE3; Thu, 6 Jan 2022 17:20:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641489651; bh=6hGkG8sCapfiKE5GsYhVlbIB0Sw85pSQfdIq/VJCMOY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=j90KTY3hiwGxIaKHuOMWXUbepPuhljaZHQEr8eV1Z4BaoMm5W6fMj8WaRMbAcZkmm UO0mz98oaA8ZOqWRE9BH4dlc1gcoMvFJGN4n8qhQT5l9wbr1NvogdQauJKR3FO35HJ FvOQr4FdWSbD7imtIKiKjaKY2Ym6iwABwomYEPCrviGjeFz4C0LIj6+rnKO7URsj2W 2etjKhUdx7sz1b23A9Gr5ku3MRFmJUj0zm2EpDyBBGBpPhSgEOKabx/pg02vq8NESd MpPeEPD2eDjMCfexrPV1s2ymNOwP6qEQPAXoOpWLVj7Mhz0l1zs0BeONKiSbB6rcr9 sdw+mwav3CB5A== Date: Thu, 6 Jan 2022 18:20:44 +0100 From: Marek =?UTF-8?B?QmVow7pu?= To: Marc Zyngier Cc: Pali =?UTF-8?B?Um9ow6Fy?= , Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts Message-ID: <20220106182044.3ff0828c@thinkpad> In-Reply-To: <877dbcvngf.wl-maz@kernel.org> References: <20220105150239.9628-1-pali@kernel.org> <20220105150239.9628-11-pali@kernel.org> <87bl0ovq7f.wl-maz@kernel.org> <20220106154447.aie6taiuvav5wu6y@pali> <878rvsvoyo.wl-maz@kernel.org> <20220106162047.vqykmygs75eimfgy@pali> <877dbcvngf.wl-maz@kernel.org> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220106_092053_807581_4768082F X-CRM114-Status: GOOD ( 61.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCAwNiBKYW4gMjAyMiAxNjoyNzo0NCArMDAwMApNYXJjIFp5bmdpZXIgPG1hekBrZXJu ZWwub3JnPiB3cm90ZToKCj4gT24gVGh1LCAwNiBKYW4gMjAyMiAxNjoyMDo0NyArMDAwMCwKPiBQ YWxpIFJvaMOhciA8cGFsaUBrZXJuZWwub3JnPiB3cm90ZToKPiA+IAo+ID4gT24gVGh1cnNkYXkg MDYgSmFudWFyeSAyMDIyIDE1OjU1OjExIE1hcmMgWnluZ2llciB3cm90ZTogIAo+ID4gPiBPbiBU aHUsIDA2IEphbiAyMDIyIDE1OjQ0OjQ3ICswMDAwLAo+ID4gPiBQYWxpIFJvaMOhciA8cGFsaUBr ZXJuZWwub3JnPiB3cm90ZTogIAo+ID4gPiA+IAo+ID4gPiA+IE9uIFRodXJzZGF5IDA2IEphbnVh cnkgMjAyMiAxNToyODoyMCBNYXJjIFp5bmdpZXIgd3JvdGU6ICAKPiA+ID4gPiA+IE9uIFdlZCwg MDUgSmFuIDIwMjIgMTU6MDI6MzggKzAwMDAsCj4gPiA+ID4gPiBQYWxpIFJvaMOhciA8cGFsaUBr ZXJuZWwub3JnPiB3cm90ZTogIAo+ID4gPiA+ID4gPiAKPiA+ID4gPiA+ID4gVGhpcyBhZGRzIHN1 cHBvcnQgZm9yIGxlZ2FjeSBJTlR4IGludGVycnVwdHMgcmVjZWl2ZWQgZnJvbSBvdGhlciBQQ0ll Cj4gPiA+ID4gPiA+IGRldmljZXMgYW5kIHdoaWNoIGFyZSByZXBvcnRlZCBieSBhIG5ldyBJTlR4 IGlycSBjaGlwLgo+ID4gPiA+ID4gPiAKPiA+ID4gPiA+ID4gV2l0aCB0aGlzIGNoYW5nZSwga2Vy bmVsIGNhbiBkaXN0aW5ndWlzaCBiZXR3ZWVuIElOVEEsIElOVEIsIElOVEMgYW5kIElOVEQKPiA+ ID4gPiA+ID4gaW50ZXJydXB0cy4KPiA+ID4gPiA+ID4gCj4gPiA+ID4gPiA+IE5vdGUgdGhhdCBm b3IgdGhpcyBzdXBwb3J0LCBkZXZpY2UgdHJlZSBmaWxlcyBoYXMgdG8gYmUgcHJvcGVybHkgYWRq dXN0ZWQKPiA+ID4gPiA+ID4gdG8gcHJvdmlkZSAiaW50ZXJydXB0cyIgb3IgImludGVycnVwdHMt ZXh0ZW5kZWQiIHByb3BlcnR5IHdpdGggaW50eAo+ID4gPiA+ID4gPiBpbnRlcnJ1cHQgc291cmNl LCAiaW50ZXJydXB0LW5hbWVzIiBwcm9wZXJ0eSB3aXRoICJpbnR4IiBzdHJpbmcgYW5kIGFsc28K PiA+ID4gPiA+ID4gJ2ludGVycnVwdC1jb250cm9sbGVyJyBzdWJub2RlIG11c3QgYmUgZGVmaW5l ZC4KPiA+ID4gPiA+ID4gCj4gPiA+ID4gPiA+IElmIGRldmljZSB0cmVlIGZpbGVzIGRvIG5vdCBw cm92aWRlIHRoZXNlIG5vZGVzIHRoZW4gZHJpdmVyIHdvdWxkIHdvcmsgYXMKPiA+ID4gPiA+ID4g YmVmb3JlLgo+ID4gPiA+ID4gPiAKPiA+ID4gPiA+ID4gU2lnbmVkLW9mZi1ieTogUGFsaSBSb2jD oXIgPHBhbGlAa2VybmVsLm9yZz4KPiA+ID4gPiA+ID4gLS0tCj4gPiA+ID4gPiA+ICBkcml2ZXJz L3BjaS9jb250cm9sbGVyL3BjaS1tdmVidS5jIHwgMTgyICsrKysrKysrKysrKysrKysrKysrKysr KysrKy0tCj4gPiA+ID4gPiA+ICAxIGZpbGUgY2hhbmdlZCwgMTc0IGluc2VydGlvbnMoKyksIDgg ZGVsZXRpb25zKC0pCj4gPiA+ID4gPiA+IAo+ID4gPiA+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVy cy9wY2kvY29udHJvbGxlci9wY2ktbXZlYnUuYyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNp LW12ZWJ1LmMKPiA+ID4gPiA+ID4gaW5kZXggMWU5MGFiODg4MDc1Li4wNGJjZGQ3YjdhNmQgMTAw NjQ0Cj4gPiA+ID4gPiA+IC0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpLW12ZWJ1LmMK PiA+ID4gPiA+ID4gKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ktbXZlYnUuYwo+ID4g PiA+ID4gPiBAQCAtNTQsOSArNTQsMTAgQEAKPiA+ID4gPiA+ID4gIAkgUENJRV9DT05GX0FERFJf RU4pCj4gPiA+ID4gPiA+ICAjZGVmaW5lIFBDSUVfQ09ORl9EQVRBX09GRgkweDE4ZmMKPiA+ID4g PiA+ID4gICNkZWZpbmUgUENJRV9JTlRfQ0FVU0VfT0ZGCTB4MTkwMAo+ID4gPiA+ID4gPiArI2Rl ZmluZSBQQ0lFX0lOVF9VTk1BU0tfT0ZGCTB4MTkxMAo+ID4gPiA+ID4gPiArI2RlZmluZSAgUENJ RV9JTlRfSU5UWChpKQkJQklUKDI0K2kpCj4gPiA+ID4gPiA+ICAjZGVmaW5lICBQQ0lFX0lOVF9Q TV9QTUUJCUJJVCgyOCkKPiA+ID4gPiA+ID4gLSNkZWZpbmUgUENJRV9NQVNLX09GRgkJMHgxOTEw Cj4gPiA+ID4gPiA+IC0jZGVmaW5lICBQQ0lFX01BU0tfRU5BQkxFX0lOVFMgICAgICAgICAgMHgw ZjAwMDAwMAo+ID4gPiA+ID4gPiArI2RlZmluZSAgUENJRV9JTlRfQUxMX01BU0sJCUdFTk1BU0so MzEsIDApCj4gPiA+ID4gPiA+ICAjZGVmaW5lIFBDSUVfQ1RSTF9PRkYJCTB4MWEwMAo+ID4gPiA+ ID4gPiAgI2RlZmluZSAgUENJRV9DVFJMX1gxX01PREUJCTB4MDAwMQo+ID4gPiA+ID4gPiAgI2Rl ZmluZSAgUENJRV9DVFJMX1JDX01PREUJCUJJVCgxKQo+ID4gPiA+ID4gPiBAQCAtMTEwLDYgKzEx MSwxMCBAQCBzdHJ1Y3QgbXZlYnVfcGNpZV9wb3J0IHsKPiA+ID4gPiA+ID4gIAlzdHJ1Y3QgbXZl YnVfcGNpZV93aW5kb3cgaW93aW47Cj4gPiA+ID4gPiA+ICAJdTMyIHNhdmVkX3BjaWVfc3RhdDsK PiA+ID4gPiA+ID4gIAlzdHJ1Y3QgcmVzb3VyY2UgcmVnczsKPiA+ID4gPiA+ID4gKwlzdHJ1Y3Qg aXJxX2RvbWFpbiAqaW50eF9pcnFfZG9tYWluOwo+ID4gPiA+ID4gPiArCXN0cnVjdCBpcnFfY2hp cCBpbnR4X2lycV9jaGlwOyAgCj4gPiA+ID4gPiAKPiA+ID4gPiA+IFdoeSBpcyB0aGlzIHN0cnVj dHVyZSBwZXIgcG9ydD8gSXQgcmVhbGx5IHNob3VsZCBiZSBnbG9iYWwuIFByaW50aW5nCj4gPiA+ ID4gPiB0aGUgcG9ydCBudW1iZXIgaW4gdGhlIG5hbWUgaXNuJ3QgZW5vdWdoIG9mIGEgcmVhc29u LiAgCj4gPiA+ID4gCj4gPiA+ID4gQmVjYXVzZSBlYWNoIHBvcnQgaGFzIGl0cyBvd24gaW5kZXBl bmRlbnQgc2V0IG9mIElOVEEtSU5URAo+ID4gPiA+IGludGVycnVwdHMuICAKPiA+ID4gCj4gPiA+ IFRoYXQgZG9lc24ndCB3YXJyYW50IGEgY29weSBvZiBhbiBpcnFfY2hpcCBzdHJ1Y3R1cmUgdGhh dCBjb250YWlucyB0aGUKPiA+ID4gZXhhY3Qgc2FtZSBjYWxsYmFja3MsIGFuZCBvbmx5IGRpZmZl cnMgYnkgKmEgc3RyaW5nKi4gQW5kIHRoZSB1c2Ugb2YKPiA+ID4gdGhpcyBzdHJpbmcgaXMgb25s eSB0byBlbmQtdXAgaW4gL3Byb2MvaW50ZXJydXB0cywgd2hpY2ggaXMgdG90YWxseQo+ID4gPiBw b2ludGxlc3MuCj4gPiA+ICAgCj4gPiA+ID4gICAKPiA+ID4gPiA+ID4gKwlyYXdfc3BpbmxvY2tf dCBpcnFfbG9jazsKPiA+ID4gPiA+ID4gKwlpbnQgaW50eF9pcnE7Cj4gPiA+ID4gPiA+ICB9Owo+ ID4gPiA+ID4gPiAgCj4gPiA+ID4gPiA+ICBzdGF0aWMgaW5saW5lIHZvaWQgbXZlYnVfd3JpdGVs KHN0cnVjdCBtdmVidV9wY2llX3BvcnQgKnBvcnQsIHUzMiB2YWwsIHUzMiByZWcpCj4gPiA+ID4g PiA+IEBAIC0yMzUsNyArMjQwLDcgQEAgc3RhdGljIHZvaWQgbXZlYnVfcGNpZV9zZXR1cF93aW5z KHN0cnVjdCBtdmVidV9wY2llX3BvcnQgKnBvcnQpCj4gPiA+ID4gPiA+ICAKPiA+ID4gPiA+ID4g IHN0YXRpYyB2b2lkIG12ZWJ1X3BjaWVfc2V0dXBfaHcoc3RydWN0IG12ZWJ1X3BjaWVfcG9ydCAq cG9ydCkKPiA+ID4gPiA+ID4gIHsKPiA+ID4gPiA+ID4gLQl1MzIgY3RybCwgbG5rY2FwLCBjbWQs IGRldl9yZXYsIG1hc2s7Cj4gPiA+ID4gPiA+ICsJdTMyIGN0cmwsIGxua2NhcCwgY21kLCBkZXZf cmV2LCB1bm1hc2s7Cj4gPiA+ID4gPiA+ICAKPiA+ID4gPiA+ID4gIAkvKiBTZXR1cCBQQ0llIGNv bnRyb2xsZXIgdG8gUm9vdCBDb21wbGV4IG1vZGUuICovCj4gPiA+ID4gPiA+ICAJY3RybCA9IG12 ZWJ1X3JlYWRsKHBvcnQsIFBDSUVfQ1RSTF9PRkYpOwo+ID4gPiA+ID4gPiBAQCAtMjg4LDEwICsy OTMsMzAgQEAgc3RhdGljIHZvaWQgbXZlYnVfcGNpZV9zZXR1cF9odyhzdHJ1Y3QgbXZlYnVfcGNp ZV9wb3J0ICpwb3J0KQo+ID4gPiA+ID4gPiAgCS8qIFBvaW50IFBDSWUgdW5pdCBNQlVTIGRlY29k ZSB3aW5kb3dzIHRvIERSQU0gc3BhY2UuICovCj4gPiA+ID4gPiA+ICAJbXZlYnVfcGNpZV9zZXR1 cF93aW5zKHBvcnQpOwo+ID4gPiA+ID4gPiAgCj4gPiA+ID4gPiA+IC0JLyogRW5hYmxlIGludGVy cnVwdCBsaW5lcyBBLUQuICovCj4gPiA+ID4gPiA+IC0JbWFzayA9IG12ZWJ1X3JlYWRsKHBvcnQs IFBDSUVfTUFTS19PRkYpOwo+ID4gPiA+ID4gPiAtCW1hc2sgfD0gUENJRV9NQVNLX0VOQUJMRV9J TlRTOwo+ID4gPiA+ID4gPiAtCW12ZWJ1X3dyaXRlbChwb3J0LCBtYXNrLCBQQ0lFX01BU0tfT0ZG KTsKPiA+ID4gPiA+ID4gKwkvKiBNYXNrIGFsbCBpbnRlcnJ1cHQgc291cmNlcy4gKi8KPiA+ID4g PiA+ID4gKwltdmVidV93cml0ZWwocG9ydCwgflBDSUVfSU5UX0FMTF9NQVNLLCBQQ0lFX0lOVF9V Tk1BU0tfT0ZGKTsKPiA+ID4gPiA+ID4gKwo+ID4gPiA+ID4gPiArCS8qIENsZWFyIGFsbCBpbnRl cnJ1cHQgY2F1c2VzLiAqLwo+ID4gPiA+ID4gPiArCW12ZWJ1X3dyaXRlbChwb3J0LCB+UENJRV9J TlRfQUxMX01BU0ssIFBDSUVfSU5UX0NBVVNFX09GRik7Cj4gPiA+ID4gPiA+ICsKPiA+ID4gPiA+ ID4gKwlpZiAocG9ydC0+aW50eF9pcnEgPD0gMCkgewo+ID4gPiA+ID4gPiArCQkvKgo+ID4gPiA+ ID4gPiArCQkgKiBXaGVuIG5laXRoZXIgInN1bW1hcnkiIGludGVycnVwdCwgbm9yICJpbnR4IiBp bnRlcnJ1cHQgd2FzCj4gPiA+ID4gPiA+ICsJCSAqIHNwZWNpZmllZCBpbiBEVCB0aGVuIHVubWFz ayBhbGwgbGVnYWN5IElOVHggaW50ZXJydXB0cyBhcyBpbgo+ID4gPiA+ID4gPiArCQkgKiB0aGlz IGNhc2UgZHJpdmVyIGRvZXMgbm90IHByb3ZpZGUgYSB3YXkgZm9yIG1hc2tpbmcgYW5kCj4gPiA+ ID4gPiA+ICsJCSAqIHVubWFza2luZyBvZiBpbmRpdmlkdWFsIGxlZ2FjeSBJTlR4IGludGVycnVw dHMuIEluIHRoaXMgY2FzZQo+ID4gPiA+ID4gPiArCQkgKiBhbGwgaW50ZXJydXB0cywgaW5jbHVk aW5nIGxlZ2FjeSBJTlR4IGFyZSByZXBvcnRlZCB2aWEgb25lCj4gPiA+ID4gPiA+ICsJCSAqIHNo YXJlZCBHSUMgc291cmNlIGFuZCB0aGVyZWZvcmUga2VybmVsIGNhbm5vdCBkaXN0aW5ndWlzaAo+ ID4gPiA+ID4gPiArCQkgKiB3aGljaCBpbmRpdmlkdWFsIGxlZ2FjeSBJTlR4IHdhcyB0cmlnZ2Vy ZWQuIFRoZXNlIGludGVycnVwdHMKPiA+ID4gPiA+ID4gKwkJICogYXJlIHNoYXJlZCwgc28gaXQg c2hvdWxkIG5vdCBjYXVzZSBhbnkgaXNzdWUuIEp1c3QKPiA+ID4gPiA+ID4gKwkJICogcGVyZm9y bWFuY2UgcGVuYWx0eSBhcyBldmVyeSBQQ0llIGludGVycnVwdCBoYW5kbGVyIG5lZWRzIHRvCj4g PiA+ID4gPiA+ICsJCSAqIGJlIGNhbGxlZCB3aGVuIHNvbWUgaW50ZXJydXB0IGlzIHRyaWdnZXJl ZC4KPiA+ID4gPiA+ID4gKwkJICovCj4gPiA+ID4gPiA+ICsJCXVubWFzayA9IG12ZWJ1X3JlYWRs KHBvcnQsIFBDSUVfSU5UX1VOTUFTS19PRkYpOwo+ID4gPiA+ID4gPiArCQl1bm1hc2sgfD0gUENJ RV9JTlRfSU5UWCgwKSB8IFBDSUVfSU5UX0lOVFgoMSkgfAo+ID4gPiA+ID4gPiArCQkJICBQQ0lF X0lOVF9JTlRYKDIpIHwgUENJRV9JTlRfSU5UWCgzKTsKPiA+ID4gPiA+ID4gKwkJbXZlYnVfd3Jp dGVsKHBvcnQsIHVubWFzaywgUENJRV9JTlRfVU5NQVNLX09GRik7ICAKPiA+ID4gPiA+IAo+ID4g PiA+ID4gTWF5YmUgd29ydGggcHJpbnRpbmcgYSB3YXJuaW5nIGhlcmUsIHNvIHRoYXQgdGhlIHVz ZXIga25vd3MgdGhleSBhcmUKPiA+ID4gPiA+IG9uIHRoaW4gaWNlLiAgCj4gPiA+ID4gCj4gPiA+ ID4gT2suIEkgY2FuIGFkZCBpdCBoZXJlLiBBbnl3YXksIHRoaXMgaXMgZGVmYXVsdCBjdXJyZW50 IHN0YXRlIHdpdGhvdXQKPiA+ID4gPiB0aGlzIHBhdGNoLgo+ID4gPiA+ICAgCj4gPiA+ID4gPiA+ ICsJfQo+ID4gPiA+ID4gPiAgfQo+ID4gPiA+ID4gPiAgCj4gPiA+ID4gPiA+ICBzdGF0aWMgc3Ry dWN0IG12ZWJ1X3BjaWVfcG9ydCAqbXZlYnVfcGNpZV9maW5kX3BvcnQoc3RydWN0IG12ZWJ1X3Bj aWUgKnBjaWUsCj4gPiA+ID4gPiA+IEBAIC05MjQsNiArOTQ5LDEwOSBAQCBzdGF0aWMgc3RydWN0 IHBjaV9vcHMgbXZlYnVfcGNpZV9vcHMgPSB7Cj4gPiA+ID4gPiA+ICAJLndyaXRlID0gbXZlYnVf cGNpZV93cl9jb25mLAo+ID4gPiA+ID4gPiAgfTsKPiA+ID4gPiA+ID4gIAo+ID4gPiA+ID4gPiAr c3RhdGljIHZvaWQgbXZlYnVfcGNpZV9pbnR4X2lycV9tYXNrKHN0cnVjdCBpcnFfZGF0YSAqZCkK PiA+ID4gPiA+ID4gK3sKPiA+ID4gPiA+ID4gKwlzdHJ1Y3QgbXZlYnVfcGNpZV9wb3J0ICpwb3J0 ID0gZC0+ZG9tYWluLT5ob3N0X2RhdGE7Cj4gPiA+ID4gPiA+ICsJaXJxX2h3X251bWJlcl90IGh3 aXJxID0gaXJxZF90b19od2lycShkKTsKPiA+ID4gPiA+ID4gKwl1bnNpZ25lZCBsb25nIGZsYWdz Owo+ID4gPiA+ID4gPiArCXUzMiB1bm1hc2s7Cj4gPiA+ID4gPiA+ICsKPiA+ID4gPiA+ID4gKwly YXdfc3Bpbl9sb2NrX2lycXNhdmUoJnBvcnQtPmlycV9sb2NrLCBmbGFncyk7Cj4gPiA+ID4gPiA+ ICsJdW5tYXNrID0gbXZlYnVfcmVhZGwocG9ydCwgUENJRV9JTlRfVU5NQVNLX09GRik7Cj4gPiA+ ID4gPiA+ICsJdW5tYXNrICY9IH5QQ0lFX0lOVF9JTlRYKGh3aXJxKTsKPiA+ID4gPiA+ID4gKwlt dmVidV93cml0ZWwocG9ydCwgdW5tYXNrLCBQQ0lFX0lOVF9VTk1BU0tfT0ZGKTsKPiA+ID4gPiA+ ID4gKwlyYXdfc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmcG9ydC0+aXJxX2xvY2ssIGZsYWdzKTsK PiA+ID4gPiA+ID4gK30KPiA+ID4gPiA+ID4gKwo+ID4gPiA+ID4gPiArc3RhdGljIHZvaWQgbXZl YnVfcGNpZV9pbnR4X2lycV91bm1hc2soc3RydWN0IGlycV9kYXRhICpkKQo+ID4gPiA+ID4gPiAr ewo+ID4gPiA+ID4gPiArCXN0cnVjdCBtdmVidV9wY2llX3BvcnQgKnBvcnQgPSBkLT5kb21haW4t Pmhvc3RfZGF0YTsKPiA+ID4gPiA+ID4gKwlpcnFfaHdfbnVtYmVyX3QgaHdpcnEgPSBpcnFkX3Rv X2h3aXJxKGQpOwo+ID4gPiA+ID4gPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gPiA+ID4gPiA+ ICsJdTMyIHVubWFzazsKPiA+ID4gPiA+ID4gKwo+ID4gPiA+ID4gPiArCXJhd19zcGluX2xvY2tf aXJxc2F2ZSgmcG9ydC0+aXJxX2xvY2ssIGZsYWdzKTsKPiA+ID4gPiA+ID4gKwl1bm1hc2sgPSBt dmVidV9yZWFkbChwb3J0LCBQQ0lFX0lOVF9VTk1BU0tfT0ZGKTsKPiA+ID4gPiA+ID4gKwl1bm1h c2sgfD0gUENJRV9JTlRfSU5UWChod2lycSk7Cj4gPiA+ID4gPiA+ICsJbXZlYnVfd3JpdGVsKHBv cnQsIHVubWFzaywgUENJRV9JTlRfVU5NQVNLX09GRik7Cj4gPiA+ID4gPiA+ICsJcmF3X3NwaW5f dW5sb2NrX2lycXJlc3RvcmUoJnBvcnQtPmlycV9sb2NrLCBmbGFncyk7Cj4gPiA+ID4gPiA+ICt9 Cj4gPiA+ID4gPiA+ICsKPiA+ID4gPiA+ID4gK3N0YXRpYyBpbnQgbXZlYnVfcGNpZV9pbnR4X2ly cV9tYXAoc3RydWN0IGlycV9kb21haW4gKmgsCj4gPiA+ID4gPiA+ICsJCQkJICAgdW5zaWduZWQg aW50IHZpcnEsIGlycV9od19udW1iZXJfdCBod2lycSkKPiA+ID4gPiA+ID4gK3sKPiA+ID4gPiA+ ID4gKwlzdHJ1Y3QgbXZlYnVfcGNpZV9wb3J0ICpwb3J0ID0gaC0+aG9zdF9kYXRhOwo+ID4gPiA+ ID4gPiArCj4gPiA+ID4gPiA+ICsJaXJxX3NldF9zdGF0dXNfZmxhZ3ModmlycSwgSVJRX0xFVkVM KTsKPiA+ID4gPiA+ID4gKwlpcnFfc2V0X2NoaXBfYW5kX2hhbmRsZXIodmlycSwgJnBvcnQtPmlu dHhfaXJxX2NoaXAsIGhhbmRsZV9sZXZlbF9pcnEpOwo+ID4gPiA+ID4gPiArCWlycV9zZXRfY2hp cF9kYXRhKHZpcnEsIHBvcnQpOwo+ID4gPiA+ID4gPiArCj4gPiA+ID4gPiA+ICsJcmV0dXJuIDA7 Cj4gPiA+ID4gPiA+ICt9Cj4gPiA+ID4gPiA+ICsKPiA+ID4gPiA+ID4gK3N0YXRpYyBjb25zdCBz dHJ1Y3QgaXJxX2RvbWFpbl9vcHMgbXZlYnVfcGNpZV9pbnR4X2lycV9kb21haW5fb3BzID0gewo+ ID4gPiA+ID4gPiArCS5tYXAgPSBtdmVidV9wY2llX2ludHhfaXJxX21hcCwKPiA+ID4gPiA+ID4g KwkueGxhdGUgPSBpcnFfZG9tYWluX3hsYXRlX29uZWNlbGwsCj4gPiA+ID4gPiA+ICt9Owo+ID4g PiA+ID4gPiArCj4gPiA+ID4gPiA+ICtzdGF0aWMgaW50IG12ZWJ1X3BjaWVfaW5pdF9pcnFfZG9t YWluKHN0cnVjdCBtdmVidV9wY2llX3BvcnQgKnBvcnQpCj4gPiA+ID4gPiA+ICt7Cj4gPiA+ID4g PiA+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gJnBvcnQtPnBjaWUtPnBkZXYtPmRldjsKPiA+ID4g PiA+ID4gKwlzdHJ1Y3QgZGV2aWNlX25vZGUgKnBjaWVfaW50Y19ub2RlOwo+ID4gPiA+ID4gPiAr Cj4gPiA+ID4gPiA+ICsJcmF3X3NwaW5fbG9ja19pbml0KCZwb3J0LT5pcnFfbG9jayk7Cj4gPiA+ ID4gPiA+ICsKPiA+ID4gPiA+ID4gKwlwb3J0LT5pbnR4X2lycV9jaGlwLm5hbWUgPSBkZXZtX2th c3ByaW50ZihkZXYsIEdGUF9LRVJORUwsCj4gPiA+ID4gPiA+ICsJCQkJCQkgICJtdmVidS0lcy1J TlR4IiwKPiA+ID4gPiA+ID4gKwkJCQkJCSAgcG9ydC0+bmFtZSk7ICAKPiA+ID4gPiA+IAo+ID4g PiA+ID4gVGhhdCdzIGV4YWN0bHkgd2hhdCBJIHJlYWxseSBkb24ndCB3YW50IHRvIHNlZS4gSXQg cHJldmVudHMgc2hhcmluZyBvZgo+ID4gPiA+ID4gdGhlIGlycV9jaGlwIHN0cnVjdHVyZSwgYW5k IGdldHMgaW4gdGhlIHdheSBvZiBtYWtpbmcgaXQgY29uc3QgaW4gdGhlCj4gPiA+ID4gPiBmdXR1 cmUuIFllcywgSSBrbm93IHRoYXQgc29tZSBkcml2ZXJzIGRvIHRoYXQuIEkgY2FuJ3QgZml4IHRo b3NlLAo+ID4gPiA+ID4gYmVjYXVzZSAvcHJvYy9pbnRlcnJ1cHRzIGlzIEFCSS4gQnV0IEkgcmVh bGx5IGRvbid0IHdhbnQgdG8gc2VlIG1vcmUKPiA+ID4gPiA+IG9mIHRoZXNlLiAgCj4gPiA+ID4g Cj4gPiA+ID4gV2VsbCwgSSBkbyBub3QgdW5kZXJzdGFuZCB3aHkgaXQgc2hvdWxkIGJlIHNoYXJl ZCBhbmQgd2l0aCB3aG8uIEhXIGhhcyBOCj4gPiA+ID4gaW5kZXBlbmRlbnQgSVJRIGNoaXBzIGZv ciBsZWdhY3kgaW50ZXJydXB0cy4gQW5kIGVhY2ggb25lIHdpbGwgYmUKPiA+ID4gPiBzcGVjaWZp ZWQgaW4gRFQgcGVyIEhXIGxheW91dCAvIGRlc2lnbi4gIAo+ID4gPiAKPiA+ID4gSWYgeW91IGhh dmUgbXVsdGlwbGUgcG9ydHMsIGFsbCB0aGUgcG9ydHMgY2FuIHNoYXJlIHRoZSBpcnFfY2hpcAo+ ID4gPiBzdHJ1Y3R1cmUuIEFjdHVhbGx5IHNjcmF0Y2ggdGhhdC4gVGhleSAqTVVTVCogc2hhcmUg dGhlIHN0cnVjdHVyZS4gVGhlCj4gPiA+IG9ubHkgcmVhc29uIHlvdSdyZSBub3Qgc2hhcmluZyBp dCBpcyB0byBiZSBhYmxlIHRvIHByaW50IHRoaXMgdXNlbGVzcwo+ID4gPiBzdHJpbmcgaW4gL3By b2MvaW50ZXJydXB0cy4gIAo+ID4gCj4gPiBXaGF0IGlzIHRoZSBwb2ludCBvZiBzaGFyaW5nIG9u ZSBpcnEgY2hpcCBpZiBIVyBoYXMgTiBpbmRlcGVuZGVudCBpcnEKPiA+IGNoaXBzIChmb3IgbGVn YWN5IGludGVycnVwdHMpPyBJIGRvIG5vdCBjYXRjaCBpdCB5ZXQuIEFuZCBJIGRvIG5vdCBjYXJl Cj4gPiBoZXJlIGZvciAvcHJvYy9pbnRlcnJ1cHRzLCBzbyBhbHNvIEkgaGF2ZSBub3QgY2F1Z2h0 IHdoYXQgZG8geW91IG1lYW4gYmUKPiA+IGxhc3Qgc2VudGVuY2Ugd2l0aCAidGhlIG9ubHkgcmVh c29uIi4KPiA+IAo+ID4gQW5kIEkgc3RpbGwgZG8gbm90IHNlZSBob3cgaXQgY291bGQgZXZlbiB3 b3JrIHRvIGhhdmUganVzdCBvbmUgaXJxIGNoaXAKPiA+IGFuZCBvbmUgaXJxIGRvbWFpbiBhcyBl YWNoIGlycSBkb21haW4gbmVlZHMgdG8ga25vdyB0byB3aGljaCBwb3J0IGl0Cj4gPiBiZWxvbmdz LCBzbyBpdCBjYW4gbWFzay91bm1hc2sgaW50ZXJydXB0cyBmcm9tIGNvcnJlY3QgcG9ydC4gQWxz bwo+ID4gaW5pdGlhbGl6YXRpb24gb2YgZG9tYWluIGlzIHRha2luZyBEVCBub2RlIGFuZCBmb3Ig ZWFjaCBwb3J0IGl0IGlzCj4gPiBkaWZmZXJlbnQuCj4gPiAKPiA+IFNvIEknbSBzb21laG93IGNv bmZ1c2VkIGhlcmUuLi4KPiA+IAo+ID4gVGhlIGltcHJvdmVtZW50IGluIHRoaXMgcGF0Y2ggaXMg dG8gYmUgYWJsZSB0byBtYXNrIElOVEEgaW50ZXJydXB0cyBvbgo+ID4gcG9ydCAxIGFuZCBsZXQg SU5UQSBpbnRlcnJ1cHRzIHVubWFza2VkIG9uIHBvcnQgMiBpZiB0aGVyZSBkcml2ZXJzIGFyZQo+ ID4gaW50ZXJlc3RlZCBvbmx5IGZvciBpbnRlcnJ1cHRzIGZyb20gZGV2aWNlIGNvbm5lY3RlZCB0 byBwb3J0IDIuCj4gPiAKPiA+IEFuZCBpZiBhbGwgaW50ZXJydXB0cyBhcmUgZ29pbmcgdG8gYmUg c2hhcmVkIChhZ2FpbikgdGhlbiBpdCBkb2VzIG5vdAo+ID4gc29sdmUgYW55IHByb2JsZW0uICAK PiAKPiBZb3UgYXJlIGNvbXBsZXRlbHkgbWlzc2luZyBteSBwb2ludC4gSSdtIHRhbGtpbmcgYWJv dXQgZGF0YQo+IHN0cnVjdHVyZXMsIHlvdSdyZSB0YWxraW5nIGFib3V0IGludGVycnVwdHMuIFlv dSBoYXZlIHRoaXM6Cj4gCj4gc3RydWN0IG12ZWJ1X3BjaWVfcG9ydCB7Cj4gICAgICAgIC8vIFRv bnMgb2Ygc3R1ZmYKPiAgICAgICAgc3RydWN0IGlycV9jaGlwIGludHhfY2hpcDsKPiB9Owo+IAo+ IFdoYXQgSSB3YW50IHlvdSB0byBkbyBpczoKPiAKPiBzdHJ1Y3QgbXZlYnVfcGNpZV9wb3J0IHsK PiAgICAgICAgLy8gVG9ucyBvZiBzdHVmZgo+IH07Cj4gCj4gc3RhdGljIHN0cnVjdCBpcnFfY2hp cCBpbnR4X2NoaXAgPSB7Cj4gCS5uYW1lCQk9ICJJTlR4IiwKPiAJLmlycV9tYXNrCT0gbXZlYnVf cGNpZV9pbnR4X2lycV9tYXNrLAo+IAkuaXJxX3VubWFzawk9IG12ZWJ1X3BjaWVfaW50eF9pcnFf dW5tYXNrOwo+IH07Cj4gCj4gVGhhdCdzIGl0LiBObyBtb3JlLCBubyBsZXNzLgo+IAo+IAlNLgo+ IAoKSG1tLCBidXQgc3RydWN0IGlycV9jaGlwIGNvbnRhaW5zIGEgZHluYW1pYyBtZW1iZXIsCiAg c3RydWN0IGRldmljZSAqcGFyZW50X2RldmljZTsKSXNuJ3QgdGhhdCB1c2VkPyBPciBhcmUgeW91 IHBsYW5uaW5nIHRvIGtpbGwgaXQ/CgpNYXJlawoKX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgt YXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3Jn L21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=