From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63F60C433FE for ; Fri, 7 Jan 2022 02:24:58 +0000 (UTC) Received: from localhost ([::1]:60768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n5ew5-0006mm-70 for qemu-devel@archiver.kernel.org; Thu, 06 Jan 2022 21:24:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRt-0001gN-6S for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:42 -0500 Received: from [2607:f8b0:4864:20::230] (port=42544 helo=mail-oi1-x230.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRq-0003bN-RI for qemu-devel@nongnu.org; Thu, 06 Jan 2022 19:49:40 -0500 Received: by mail-oi1-x230.google.com with SMTP id w80so6117159oie.9 for ; Thu, 06 Jan 2022 16:49:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3fgFzCI3gythJlZEsU/Ay0AuUtj0QDTQYBmVeLzXkXw=; b=yCT2zxv99wE8i+PlHSkrccCgfBXQ7Ysmo40K4Xk7CIytQZUtzJj/Sfbm7enKSJXVCh y/2NfPdE+RzILi41wQHmxLkAuc3rBLb1LhoEUVgeIARrb41IpIm7olye848GxqF+tA2t TLZyKFavAbJdf5rYuJiGVMacbgQ3K60wikbpOCFN+sk09zzqas7LHoXvjXJ9IUY0xC/6 zK8deB6AoyFbe/RuKw5ZWnzHuGYtjFTMf82Aiwe9NmGpWaWf1qnh1ErJN0pOz1nHNqt+ USlo7tn16eJVeNVV5nBSjX/O1x+ugfof2cvqwtbjayEjSm75GTskPe2X9S+jcHY9ilqu uDpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3fgFzCI3gythJlZEsU/Ay0AuUtj0QDTQYBmVeLzXkXw=; b=F0WGsYe2xeWKPrrSfzPR1V+zlza3/RLOMDXPk4N/K1yOjgPHTuVv3GJglH7GBQP/UG ph4PpkOq1Vw1KP1UuX9BArbqBwhbOlDU0l5x/c2sA2hCs1EoCrRKLCEcbJoksC2rf26L G/NxBjoTNQjVnjKV18KkSOYLbHXlkcaZU9o7Pi/NCHqtG3s6K9Vs9mUJDFv1G7u2Txkf V1yEcTSLTB+AW/ZzVOGYShaSIIy2JKo+7oG6PzfzIul+KL9t3eETnZd/+95gb2sx6XLR iLxlWaFqyHIEQBjW3Azdk/6XGQBvZcqQ9xDPIaAXR1mHvEaK2/Ae43pqtWIrcyRwQzjk gP/g== X-Gm-Message-State: AOAM533zOuDys01qZh/kdb/IPQy9gCCD7qFxXyV/a60+YyfIgNWt63L2 VgF7qvp6mHflUW89Yj2qXInLOk9kTFdXv7ZC X-Google-Smtp-Source: ABdhPJxCvvgD3uy2A12bp/EaBt6Piq84YKxz21faRvR1BHzs4F5xCzYP/mkcHqvwnWOLq8vkicUdvw== X-Received: by 2002:a05:6808:1389:: with SMTP id c9mr8397311oiw.55.1641516577236; Thu, 06 Jan 2022 16:49:37 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:36 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v4 09/11] target/riscv: Simplify counter predicate function Date: Thu, 6 Jan 2022 16:48:44 -0800 Message-Id: <20220107004846.378859-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::230 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:01 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Signed-off-by: Atish Patra --- target/riscv/csr.c | 111 ++++----------------------------------------- 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d3a8bba6a518..feb053eb3f7b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -109,6 +109,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); int ctr_index; + uint64_t ctr_mask; int base_csrno = CSR_CYCLE; bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; @@ -117,122 +118,30 @@ static RISCVException ctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; + ctr_mask = BIT(ctr_index); if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) { goto skip_ext_pmu_check; } - if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & ctr_mask))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } skip_ext_pmu_check: - if (env->priv == PRV_S) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIME: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRET: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIMEH: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRETH: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - } + if ((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) { + return RISCV_EXCP_ILLEGAL_INST; } if (riscv_cpu_virt_enabled(env)) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIME: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRET: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIMEH: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRETH: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } + if (!get_field(env->mcounteren, ctr_mask)) { + /* The bit must be set in mcountern for HS mode access */ + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } else if (!get_field(env->hcounteren, ctr_mask)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } #endif -- 2.30.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1n5em3-0001uz-TB for mharc-qemu-riscv@gnu.org; Thu, 06 Jan 2022 21:14:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n5dRt-0001gM-4y for qemu-riscv@nongnu.org; Thu, 06 Jan 2022 19:49:42 -0500 Received: from [2607:f8b0:4864:20::232] (port=46007 helo=mail-oi1-x232.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n5dRq-0003bG-R4 for qemu-riscv@nongnu.org; Thu, 06 Jan 2022 19:49:40 -0500 Received: by mail-oi1-x232.google.com with SMTP id j124so6094297oih.12 for ; Thu, 06 Jan 2022 16:49:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3fgFzCI3gythJlZEsU/Ay0AuUtj0QDTQYBmVeLzXkXw=; b=yCT2zxv99wE8i+PlHSkrccCgfBXQ7Ysmo40K4Xk7CIytQZUtzJj/Sfbm7enKSJXVCh y/2NfPdE+RzILi41wQHmxLkAuc3rBLb1LhoEUVgeIARrb41IpIm7olye848GxqF+tA2t TLZyKFavAbJdf5rYuJiGVMacbgQ3K60wikbpOCFN+sk09zzqas7LHoXvjXJ9IUY0xC/6 zK8deB6AoyFbe/RuKw5ZWnzHuGYtjFTMf82Aiwe9NmGpWaWf1qnh1ErJN0pOz1nHNqt+ USlo7tn16eJVeNVV5nBSjX/O1x+ugfof2cvqwtbjayEjSm75GTskPe2X9S+jcHY9ilqu uDpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3fgFzCI3gythJlZEsU/Ay0AuUtj0QDTQYBmVeLzXkXw=; b=p6HrYjrpms9qbElcB46IJBztTE7pMM99lnhhDq72NCJykFkOkQeiWMYS6YX0v5wkND KrjhqaSRyPtlA0jrRs6au2gLO+Ba9hQ5PY7E7unaX7PfirAuAn1A6T5pvfsOWUWCZXXB 1vL/BsCkfxJNHMtcwuYmibrXgtSIKfTiFQxWrqfUKF5xff/ngOpaZWd2JsC7sS0nEcSW qDWJbcGHeCzv0FTQHQbE+1d2OqMK7tIL651Vvx0AAAnBI1ejYKzC6C+Qvs5tLGgFI0AF NBViZpCtAAeNblgj93w/El/bWZhn1darLyml2jRNel89fLNJcooWOO3MNUFFz2ZXhlRo vunQ== X-Gm-Message-State: AOAM533FuO1DhF+uaOw4Jwb/Hiow47qBFjK0bhveOdb141CYeJABMeUE YqMOC9XdwRzmxvwFw+vLKK2ORw== X-Google-Smtp-Source: ABdhPJxCvvgD3uy2A12bp/EaBt6Piq84YKxz21faRvR1BHzs4F5xCzYP/mkcHqvwnWOLq8vkicUdvw== X-Received: by 2002:a05:6808:1389:: with SMTP id c9mr8397311oiw.55.1641516577236; Thu, 06 Jan 2022 16:49:37 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id e4sm678441oiy.12.2022.01.06.16.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 16:49:36 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v4 09/11] target/riscv: Simplify counter predicate function Date: Thu, 6 Jan 2022 16:48:44 -0800 Message-Id: <20220107004846.378859-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> References: <20220107004846.378859-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::232 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=atishp@rivosinc.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 06 Jan 2022 21:14:12 -0500 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 07 Jan 2022 00:49:42 -0000 All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Signed-off-by: Atish Patra --- target/riscv/csr.c | 111 ++++----------------------------------------- 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d3a8bba6a518..feb053eb3f7b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -109,6 +109,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); int ctr_index; + uint64_t ctr_mask; int base_csrno = CSR_CYCLE; bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; @@ -117,122 +118,30 @@ static RISCVException ctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; + ctr_mask = BIT(ctr_index); if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) { goto skip_ext_pmu_check; } - if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & ctr_mask))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } skip_ext_pmu_check: - if (env->priv == PRV_S) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIME: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRET: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIMEH: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRETH: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - } + if ((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) { + return RISCV_EXCP_ILLEGAL_INST; } if (riscv_cpu_virt_enabled(env)) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIME: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRET: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIMEH: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRETH: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } + if (!get_field(env->mcounteren, ctr_mask)) { + /* The bit must be set in mcountern for HS mode access */ + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } else if (!get_field(env->hcounteren, ctr_mask)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } #endif -- 2.30.2