From: Robert Hancock <robert.hancock@calian.com>
To: netdev@vger.kernel.org
Cc: radhey.shyam.pandey@xilinx.com, davem@davemloft.net,
kuba@kernel.org, Robert Hancock <robert.hancock@calian.com>
Subject: [PATCH net 0/7] Xilinx axienet fixes
Date: Tue, 11 Jan 2022 15:13:51 -0600 [thread overview]
Message-ID: <20220111211358.2699350-1-robert.hancock@calian.com> (raw)
Various fixes for the Xilinx AXI Ethernet driver.
Robert Hancock (7):
net: axienet: Reset core before accessing MAC and wait for core ready
net: axienet: add missing memory barriers
net: axienet: limit minimum TX ring size
net: axienet: Fix TX ring slot available check
net: axienet: fix number of TX ring slots for available check
net: axienet: fix for TX busy handling
net: axienet: increase default TX ring size to 128
.../net/ethernet/xilinx/xilinx_axienet_main.c | 134 +++++++++++-------
1 file changed, 83 insertions(+), 51 deletions(-)
--
2.31.1
next reply other threads:[~2022-01-11 21:34 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-11 21:13 Robert Hancock [this message]
2022-01-11 21:13 ` [PATCH net 1/7] net: axienet: Reset core before accessing MAC and wait for core ready Robert Hancock
2022-01-12 0:30 ` Robert Hancock
2022-01-12 3:24 ` Jakub Kicinski
2022-01-12 16:46 ` Robert Hancock
2022-01-11 21:13 ` [PATCH net 2/7] net: axienet: add missing memory barriers Robert Hancock
2022-01-11 21:13 ` [PATCH net 3/7] net: axienet: limit minimum TX ring size Robert Hancock
2022-01-11 21:13 ` [PATCH net 4/7] net: axienet: Fix TX ring slot available check Robert Hancock
2022-01-11 21:13 ` [PATCH net 5/7] net: axienet: fix number of TX ring slots for " Robert Hancock
2022-01-11 21:13 ` [PATCH net 6/7] net: axienet: fix for TX busy handling Robert Hancock
2022-01-12 3:49 ` Jakub Kicinski
2022-01-12 16:45 ` Robert Hancock
2022-01-12 17:01 ` Jakub Kicinski
2022-01-12 17:35 ` Robert Hancock
2022-01-11 21:13 ` [PATCH net 7/7] net: axienet: increase default TX ring size to 128 Robert Hancock
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