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[88.130.49.239]) by smtp.gmail.com with ESMTPSA id b2sm257288ejh.221.2022.01.12.13.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jan 2022 13:37:00 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH 3/3] isa/piix4: Resolve global variables Date: Wed, 12 Jan 2022 22:36:28 +0100 Message-Id: <20220112213629.9126-4-shentey@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220112213629.9126-1-shentey@gmail.com> References: <20220112213629.9126-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::542 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::542; envelope-from=shentey@gmail.com; helo=mail-ed1-x542.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 12 Jan 2022 16:56:18 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Bernhard Beschow , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that piix4_set_irq's opaque parameter references own PIIX4State, piix4_dev becomes redundant and pci_irq_levels can be moved into PIIX4State. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 22 +++++++++------------- include/hw/southbridge/piix.h | 2 -- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a31e9714cf..964e09cf7f 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -39,14 +39,14 @@ #include "sysemu/runstate.h" #include "qom/object.h" -PCIDevice *piix4_dev; - struct PIIX4State { PCIDevice dev; qemu_irq cpu_intr; qemu_irq *isa; qemu_irq i8259[ISA_NUM_IRQS]; + int pci_irq_levels[PIIX_NUM_PIRQS]; + RTCState rtc; /* Reset Control Register */ MemoryRegion rcr_mem; @@ -55,24 +55,22 @@ struct PIIX4State { OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) -static int pci_irq_levels[4]; - static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; PIIX4State *s = opaque; - pci_irq_levels[irq_num] = level; + s->pci_irq_levels[irq_num] = level; /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; - if (pic_irq < 16) { + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; + if (pic_irq < ISA_NUM_IRQS) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; - for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { - pic_level |= pci_irq_levels[i]; + for (i = 0; i < PIIX_NUM_PIRQS; i++) { + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { + pic_level |= s->pci_irq_levels[i]; } } qemu_set_irq(s->i8259[pic_irq], pic_level); @@ -223,8 +221,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); - - piix4_dev = dev; } static void piix4_init(Object *obj) @@ -323,7 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4); + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); for (int i = 0; i < ISA_NUM_IRQS; i++) { s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 6387f2b612..f63f83e5c6 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -70,8 +70,6 @@ typedef struct PIIXState PIIX3State; DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) -extern PCIDevice *piix4_dev; - PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus); -- 2.34.1