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* [PATCH v9 0/4] clk: meson: add a sub EMMC clock controller support
@ 2022-01-13 11:57 ` Liang Yang
  0 siblings, 0 replies; 69+ messages in thread
From: Liang Yang @ 2022-01-13 11:57 UTC (permalink / raw)
  To: Neil Armstrong, Jerome Brunet, Kevin Hilman, Michael Turquette,
	Stephen Boyd, Rob Herring, linux-clk
  Cc: Liang Yang, Martin Blumenstingl, Jianxin Pan, Victor Wan,
	XianWei Zhao, Kelvin Zhang, BiChao Zheng, YongHui Yu,
	linux-arm-kernel, linux-amlogic, linux-kernel, devicetree

Changes since v8 [9]
 - use MESON_SCLK_ONE_BASED instead of CLK_DIVIDER_ONE_BASED
 - use struct_size to caculate onecell_data
 - add clk-phase-delay.h
 - define CLK_DELAY_STEP_PS_GX and CLK_DELAY_STEP_PS_AXG

Changes since v7 [8]
 - move meson_clk_get_phase_delay_data() from header to driver
 - CONFIG sclk-div with COMMON_CLK_AMLOGIC instead of COMMON_CLK_AMLOGIC_AUDIO
 - remove onecell date and ID for internal MUX clk
 - use helper for functions for ONE_BASED in sclk-div
 - add ONE_BASED support for duty cycle

Changes since v6 [7]:
 - add one based support for sclk divier
 - alloc sclk in probe for multiple instance
 - fix coding styles

Changes since v5 [6]:
 - remove divider ops with .init and use sclk_div instead
 - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div
 - drop the useless type cast 

Changes since v4 [5]:
 - use struct parm in phase delay driver
 - remove 0 delay releted part in phase delay driver
 - don't rebuild the parent name once again
 - add divider ops with .init

Changes since v3 [4]:
 - separate clk-phase-delay driver
 - replace clk_get_rate() with clk_hw_get_rate()
 - collect Rob's R-Y
 - drop 'meson-' prefix from compatible string

 Changes since v2 [3]:
 - squash dt-binding clock-id patch
 - update license
 - fix alignment
 - construct a clk register helper() function

Changes since v1 [2]:
 - implement phase clock
 - update compatible name
 - adjust file name
 - divider probe() into small functions, and re-use them

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun.lan@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun.lan@amlogic.com
[4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun.lan@amlogic.com
[5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun.lan@amlogic.com
[6] https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com
[7] https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin.pan@amlogic.com
[8] https://lkml.kernel.org/r/1544457877-51301-1-git-send-email-jianxin.pan@amlogic.com
[9] https://lkml.kernel.org/r/1545063850-21504-1-git-send-email-jianxin.pan@amlogic.com
Liang Yang (4):
  clk: meson: add one based divider support for sclk
  clk: meson: add emmc sub clock phase delay driver
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub MMC clock controller driver

 .../bindings/clock/amlogic,mmc-clkc.yaml      |  64 ++++
 drivers/clk/meson/Kconfig                     |  18 ++
 drivers/clk/meson/Makefile                    |   2 +
 drivers/clk/meson/clk-phase-delay.c           |  69 ++++
 drivers/clk/meson/clk-phase-delay.h           |  20 ++
 drivers/clk/meson/mmc-clkc.c                  | 300 ++++++++++++++++++
 drivers/clk/meson/sclk-div.c                  |  61 ++--
 drivers/clk/meson/sclk-div.h                  |   3 +
 include/dt-bindings/clock/amlogic,mmc-clkc.h  |  14 +
 9 files changed, 529 insertions(+), 22 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.yaml
 create mode 100644 drivers/clk/meson/clk-phase-delay.c
 create mode 100644 drivers/clk/meson/clk-phase-delay.h
 create mode 100644 drivers/clk/meson/mmc-clkc.c
 create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h

-- 
2.34.1


^ permalink raw reply	[flat|nested] 69+ messages in thread
* [PATCH RESEND v9 0/4] clk: meson: add a sub EMMC clock controller support
@ 2019-01-08 13:50 Jianxin Pan
  2019-01-08 13:50   ` Jianxin Pan
  0 siblings, 1 reply; 69+ messages in thread
From: Jianxin Pan @ 2019-01-08 13:50 UTC (permalink / raw)
  To: Jerome Brunet, Neil Armstrong
  Cc: Jianxin Pan, Kevin Hilman, Carlo Caione, Michael Turquette,
	Stephen Boyd, Rob Herring, Miquel Raynal, Boris Brezillon,
	Martin Blumenstingl, Yixun Lan, Liang Yang, Jian Hu, Qiufang Dai,
	Hanjie Lin, Victor Wan, linux-clk, linux-amlogic,
	linux-arm-kernel, linux-kernel, devicetree

This driver will add a MMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].

This driver is tested in the S400 board (AXG platform) with NAND driver.


Changes since v8 [9]
 - fix auto build test ERROR with ARCH=i386

Changes since v7 [8]
 - move meson_clk_get_phase_delay_data() from header to driver
 - CONFIG sclk-div with COMMON_CLK_AMLOGIC instead of COMMON_CLK_AMLOGIC_AUDIO
 - remove onecell date and ID for internal MUX clk
 - use helper for functions for ONE_BASED in sclk-div
 - add ONE_BASED support for duty cycle

Changes since v6 [7]:
 - add one based support for sclk divier
 - alloc sclk in probe for multiple instance
 - fix coding styles

Changes since v5 [6]:
 - remove divider ops with .init and use sclk_div instead
 - drop CLK_DIVIDER_ROUND_CLOSEST in mux and div
 - drop the useless type cast 

Changes since v4 [5]:
 - use struct parm in phase delay driver
 - remove 0 delay releted part in phase delay driver
 - don't rebuild the parent name once again
 - add divider ops with .init

Changes since v3 [4]:
 - separate clk-phase-delay driver
 - replace clk_get_rate() with clk_hw_get_rate()
 - collect Rob's R-Y
 - drop 'meson-' prefix from compatible string

 Changes since v2 [3]:
 - squash dt-binding clock-id patch
 - update license
 - fix alignment
 - construct a clk register helper() function

Changes since v1 [2]:
 - implement phase clock
 - update compatible name
 - adjust file name
 - divider probe() into small functions, and re-use them

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun.lan@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun.lan@amlogic.com
[4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun.lan@amlogic.com
[5] https://lkml.kernel.org/r/20180809070724.11935-4-yixun.lan@amlogic.com
[6] https://lkml.kernel.org/r/1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com
[7] https://lkml.kernel.org/r/1541089855-19356-1-git-send-email-jianxin.pan@amlogic.com
[8] https://lkml.kernel.org/r/1544457877-51301-1-git-send-email-jianxin.pan@amlogic.com
[9] https://lkml.kernel.org/r/1545063850-21504-1-git-send-email-jianxin.pan@amlogic.com
Jianxin Pan (1):
  clk: meson: add one based divider support for sclk divider

Yixun Lan (3):
  clk: meson: add emmc sub clock phase delay driver
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub MMC clock controller driver

 .../devicetree/bindings/clock/amlogic,mmc-clkc.txt |  39 +++
 drivers/clk/meson/Kconfig                          |  10 +
 drivers/clk/meson/Makefile                         |   5 +-
 drivers/clk/meson/clk-phase-delay.c                |  73 +++++
 drivers/clk/meson/clkc-audio.h                     |   8 -
 drivers/clk/meson/clkc.h                           |  17 +-
 drivers/clk/meson/mmc-clkc.c                       | 304 +++++++++++++++++++++
 drivers/clk/meson/sclk-div.c                       |  59 ++--
 include/dt-bindings/clock/amlogic,mmc-clkc.h       |  17 ++
 9 files changed, 502 insertions(+), 30 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt
 create mode 100644 drivers/clk/meson/clk-phase-delay.c
 create mode 100644 drivers/clk/meson/mmc-clkc.c
 create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h

-- 
1.9.1


^ permalink raw reply	[flat|nested] 69+ messages in thread

end of thread, other threads:[~2022-01-19  2:57 UTC | newest]

Thread overview: 69+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-13 11:57 [PATCH v9 0/4] clk: meson: add a sub EMMC clock controller support Liang Yang
2022-01-13 11:57 ` Liang Yang
2022-01-13 11:57 ` Liang Yang
2022-01-13 11:57 ` [PATCH v9 1/4] clk: meson: add one based divider support for sclk Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 21:28   ` Stephen Boyd
2022-01-13 21:28     ` Stephen Boyd
2022-01-13 21:28     ` Stephen Boyd
2022-01-14  3:07     ` Liang Yang
2022-01-14  3:07       ` Liang Yang
2022-01-14  3:07       ` Liang Yang
2022-01-13 11:57 ` [PATCH v9 2/4] clk: meson: add emmc sub clock phase delay driver Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 21:29   ` Stephen Boyd
2022-01-13 21:29     ` Stephen Boyd
2022-01-13 21:29     ` Stephen Boyd
2022-01-14  3:08     ` Liang Yang
2022-01-14  3:08       ` Liang Yang
2022-01-14  3:08       ` Liang Yang
2022-01-13 11:57 ` [PATCH v9 3/4] clk: meson: add DT documentation for emmc clock controller Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 21:29   ` Stephen Boyd
2022-01-13 21:29     ` Stephen Boyd
2022-01-13 21:29     ` Stephen Boyd
2022-01-14  3:06     ` Liang Yang
2022-01-14  3:06       ` Liang Yang
2022-01-14  3:06       ` Liang Yang
2022-01-14 22:59       ` Stephen Boyd
2022-01-14 22:59         ` Stephen Boyd
2022-01-14 22:59         ` Stephen Boyd
2022-01-17  2:43         ` Liang Yang
2022-01-17  2:43           ` Liang Yang
2022-01-17  2:43           ` Liang Yang
2022-01-15  0:09       ` Martin Blumenstingl
2022-01-15  0:09         ` Martin Blumenstingl
2022-01-15  0:09         ` Martin Blumenstingl
2022-01-17  7:03         ` Liang Yang
2022-01-17  7:03           ` Liang Yang
2022-01-17  7:03           ` Liang Yang
2022-01-13 11:57 ` [PATCH v9 4/4] clk: meson: add sub MMC clock controller driver Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 11:57   ` Liang Yang
2022-01-13 21:35   ` Stephen Boyd
2022-01-13 21:35     ` Stephen Boyd
2022-01-13 21:35     ` Stephen Boyd
2022-01-14  5:14     ` Liang Yang
2022-01-14  5:14       ` Liang Yang
2022-01-14  5:14       ` Liang Yang
2022-01-14 23:01       ` Stephen Boyd
2022-01-14 23:01         ` Stephen Boyd
2022-01-14 23:01         ` Stephen Boyd
2022-01-17  6:24         ` Liang Yang
2022-01-17  6:24           ` Liang Yang
2022-01-17  6:24           ` Liang Yang
2022-01-19  2:22           ` Stephen Boyd
2022-01-19  2:22             ` Stephen Boyd
2022-01-19  2:22             ` Stephen Boyd
2022-01-19  2:55             ` Liang Yang
2022-01-19  2:55               ` Liang Yang
2022-01-19  2:55               ` Liang Yang
  -- strict thread matches above, loose matches on Subject: below --
2019-01-08 13:50 [PATCH RESEND v9 0/4] clk: meson: add a sub EMMC clock controller support Jianxin Pan
2019-01-08 13:50 ` [PATCH v9 4/4] clk: meson: add sub MMC clock controller driver Jianxin Pan
2019-01-08 13:50   ` Jianxin Pan
2019-01-08 13:50   ` Jianxin Pan
2019-01-22  9:25   ` Jerome Brunet
2019-01-22  9:25     ` Jerome Brunet
2019-01-22  9:25     ` Jerome Brunet

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