From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A9C9C433F5 for ; Fri, 14 Jan 2022 10:58:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FNE3L09Dz3xvl0hDapZcA3O1J7SEfKa6OXwYC12jmw8=; b=3GZHAB275ODd5l 64UtjdhnCH8YxrwYTtlbL82BttGcz/yZT09LoPZLllzqi3sWmtHmjtJoVituka72D+C1qQ8yhcq/K /8BqMg02Kt4CoJaEjFQfnIPaLQOiskBmi2ZlJi2/Bjgt2JAs7TXeM/o6uDue/zL3e1RyPamcae61F e8NR2pgvcRFhITtFqbpizgZdoTTE7rFb0Neuen7+N9pcQWdlbb5TlRCMw1D8PYjxXLaHzG5841Z/Z 4bAoIeWiU5Hh8YG1y5WwWNLqx8L/25ISMg1qByUa5bT2HyvSuehchzBzNq2fkIGbonkiTIFrlyId0 VVP1L/OrOrfcZib9tFGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8KGx-008oCU-Em; Fri, 14 Jan 2022 10:57:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8KGY-008o3R-Fk for linux-arm-kernel@lists.infradead.org; Fri, 14 Jan 2022 10:57:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 94789ED1; Fri, 14 Jan 2022 02:57:05 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 941EA3F766; Fri, 14 Jan 2022 02:57:04 -0800 (PST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, Jaxson.Han@arm.com, mark.rutland@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com Subject: [bootwrapper PATCH v2 02/13] Add bit-field macros Date: Fri, 14 Jan 2022 10:56:42 +0000 Message-Id: <20220114105653.3003399-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220114105653.3003399-1-mark.rutland@arm.com> References: <20220114105653.3003399-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220114_025706_597473_F9862563 X-CRM114-Status: GOOD ( 15.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Arm architectural documentation typically defines bit-fields as `[msb,lsb]` and single-bit fields as `[bit]`. For clarity it would be helpful if we could define fields in the same way. Add helpers so that we can do so, along with helper to extract/insert bit-field values. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland --- include/bits.h | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 include/bits.h diff --git a/include/bits.h b/include/bits.h new file mode 100644 index 0000000..0bf2c67 --- /dev/null +++ b/include/bits.h @@ -0,0 +1,79 @@ +/* + * include/bits.h - helpers for bit-field definitions. + * + * Copyright (C) 2021 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ +#ifndef __BITS_H +#define __BITS_H + +#ifdef __ASSEMBLY__ +#define UL(x) x +#define ULL(x) x +#else +#define UL(x) x##UL +#define ULL(x) x##ULL +#endif + +/* + * Define a contiguous mask of bits with `msb` as the most significant bit and + * `lsb` as the least significant bit. The `msb` value must be greater than or + * equal to `lsb`. + * + * For example: + * - BITS(63, 63) is 0x8000000000000000 + * - BITS(63, 0) is 0xFFFFFFFFFFFFFFFF + * - BITS(0, 0) is 0x0000000000000001 + * - BITS(49, 17) is 0x0001FFFFFFFE0000 + */ +#define BITS(msb, lsb) \ + ((~ULL(0) >> (63 - msb)) & (~ULL(0) << lsb)) + +/* + * Define a mask of a single set bit `b`. + * + * For example: + * - BIT(63) is 0x8000000000000000 + * - BIT(0) is 0x0000000000000001 + * - BIT(32) is 0x0000000100000000 + */ +#define BIT(b) BITS(b, b) + +/* + * Find the least significant set bit in the contiguous set of bits in `mask`. + * + * For example: + * - BITS_LSB(0x0000000000000001) is 0 + * - BITS_LSB(0x000000000000ff00) is 8 + * - BITS_LSB(0x8000000000000000) is 63 + */ +#define BITS_LSB(mask) (__builtin_ffsll(mask) - 1) + +/* + * Extract a bit-field out of `val` described by the contiguous set of bits in + * `mask`. + * + * For example: + * - BITS_EXTRACT(0xABCD, BITS(15, 12)) is 0xA + * - BITS_EXTRACT(0xABCD, BITS(11, 8)) is 0xB + * - BITS_EXTRACT(0xABCD, BIT(7)) is 0x1 + */ +#define BITS_EXTRACT(val, mask) \ + (((val) & (mask)) >> BITS_LSB(mask)) + +/* + * Insert the least significant bits of `val` into the bit-field described by + * the contiguous set of bits in `mask`. + * + * For example: + * - BITS_INSERT(BITS(3, 0), 0xA) is 0x000A + * - BITS_INSERT(BITS(15, 12), 0xA) is 0xA000 + * - BITS_INSERT(BIT(15), 0xF) is 0x1000 + * + */ +#define BITS_INSERT(mask, val) \ + (((val) << BITS_LSB(mask)) & (mask)) + +#endif -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel