From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A0DFC433EF for ; Fri, 14 Jan 2022 15:11:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZnvUE8fgHcNEH2e8uO0D7dZyZ7vxn3nnd+UaVYTECv8=; b=O9Fp4LyL0dJZk1 GOWnI7aqGMTZi0v4NZZjqyLSCGwCiTTMEMo4OOVwJAAULiqLmGFHhP4N87xUmfPqoF1r6YOt/hvID ciJ6fkVe8hugH5AaRHY9ElQTakjOMUtOoOdkpdEIc7oA9sv0KlP7PaYwN+alUJ4S2KoS7uv9XxF+X eQ3GkUBQrTBUud0r2iv2ElH+r9/H2kCzZwBvlxB486OLlzixP0pkajysv7J2VD09QVQTmDkHurlo7 qqFVkZ3N9gTrNFH1MTkhdzW/Rv6JkHvBrXKC1lQKIFlsqraQtcmdDq28fl/UTWyuzT5jZuvxKGvwO U6KwykQCEnSBtHul0HDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8ODN-009WJw-Eq; Fri, 14 Jan 2022 15:10:05 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8ODJ-009WIn-Oe for linux-arm-kernel@lists.infradead.org; Fri, 14 Jan 2022 15:10:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 845B66D; Fri, 14 Jan 2022 07:10:00 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 92CB43F774; Fri, 14 Jan 2022 07:09:59 -0800 (PST) Date: Fri, 14 Jan 2022 15:09:57 +0000 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Jaxson.Han@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com Subject: Re: [bootwrapper PATCH v2 00/13] Cleanups and improvements Message-ID: <20220114150957.6914805f@donnerap.cambridge.arm.com> In-Reply-To: <20220114105653.3003399-1-mark.rutland@arm.com> References: <20220114105653.3003399-1-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220114_071001_944080_C6C1A190 X-CRM114-Status: GOOD ( 30.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 14 Jan 2022 10:56:40 +0000 Mark Rutland wrote: Hi Mark, > This series reworks the aarch64 boot-wrapper, moving a fair amount of > initialization code to C. This has a few benefits: > > 1) This makes the code more legible and easier to maintain. > > Current feature detection and system register configuration is > written in assembly, requiring runs of *almost* identical blocks of > assembly to read ID registers and conditionally initialize register > values. This requires a bunch of labels (which are all named > numerically), and all the magic numbers are hard coded, so this gets > pretty painful to read: > > | mrs x1, id_aa64isar0_el1 > | ubfx x1, x1, #24, #4 > | cbz x1, 1f > | > | orr x0, x0, #(1 << 34) // TME enable > | > | 1: > > In C, it's much easier to add helpers which use mnemonics, which > makes the code much easier to read, and avoids the need to manually > allocate registers, etc: > > | if (mrs_field(ID_AA64ISAR0_EL1, TME)) > | scr |= SCR_EL3_TME; > > This should make it easier to handle new architectural extensions > (and/or architecture variants such as ARMv8-R) in future. > > 2) This allows for better diagnostics. > > Currently a mis-configured boot-wrapper is rather unforgiving, and > provides no indication as to what might have gone wrong. By moving > initialization to C, we can make use to the UART code to log > diagnostic information, and we can more easily add additional error > handling and conditional logic. > > This series adds diagnostic information and error handling that can > be used to identify problems such as the boot-wrapper being launched > at the wrong exception level: > > | Boot-wrapper v0.2 > | Entered at EL2 > | Memory layout: > | [0000000080000000..0000000080001f90] => boot-wrapper > | [000000008000fff8..0000000080010000] => mbox > | [0000000080200000..00000000822af200] => kernel > | [0000000088000000..0000000088002857] => dtb > | > | WARNING: PSCI could not be initialized. Boot may fail > > Originally I had planned for this to be a more expansive set of changes, > unifying some early control-flow, fixing some latent bugs, and making > the boot-wrapper dynamically handle being entered at any of EL{3,2,1} > with automated selection of a suitable DT. As the series has already > become pretty long, I'd like to get this preparatory cleanup out of the > way first, and handle those cases with subsequent patches. > > If there are no objections, I intend to apply these by the end of the > day. Can you hold back with that till the beginning of next week? I got stuck halfway in the series with my review, but am on it now as we speak. Cheers, Andre > > I've pushed the series to the `cleanup` branch in the boot-wrapper repo: > > https://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git/ > git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git > > ... and it should apply cleanup atop the `master` branch. > > Since v1 [1]: > * Add comments for bit-field macros > * Use BIT() for *_RES1 definitions > * Complete start_el3/start_no_el3 cleanup > * Remove extraneous macro definition > > [1] https://lore.kernel.org/r/20220111130653.2331827-1-mark.rutland@arm.com/ > > Thanks, > Mark. > > Mark Rutland (13): > Document entry requirements > Add bit-field macros > aarch64: add system register accessors > aarch32: add coprocessor accessors > aarch64: add mov_64 macro > aarch64: initialize SCTLR_ELx for the boot-wrapper > Rework common init C code > Announce boot-wrapper mode / exception level > aarch64: move the bulk of EL3 initialization to C > aarch32: move the bulk of Secure PL1 initialization to C > Announce locations of memory objects > Rework bootmethod initialization > Unify start_el3 & start_no_el3 > > Makefile.am | 6 +- > arch/aarch32/boot.S | 33 +++--- > arch/aarch32/include/asm/cpu.h | 62 ++++++++--- > arch/aarch32/include/asm/gic-v3.h | 6 +- > arch/aarch32/include/asm/psci.h | 28 +++++ > arch/aarch32/init.c | 42 ++++++++ > arch/aarch32/psci.S | 16 +-- > arch/aarch32/utils.S | 9 -- > arch/aarch64/boot.S | 169 +++++++++++++----------------- > arch/aarch64/common.S | 10 +- > arch/aarch64/include/asm/cpu.h | 102 +++++++++++++++--- > arch/aarch64/include/asm/gic-v3.h | 10 +- > arch/aarch64/include/asm/psci.h | 28 +++++ > arch/aarch64/init.c | 88 ++++++++++++++++ > arch/aarch64/psci.S | 22 +--- > arch/aarch64/spin.S | 6 +- > arch/aarch64/utils.S | 9 -- > common/boot.c | 4 - > common/init.c | 60 +++++++++++ > common/platform.c | 45 +++++--- > common/psci.c | 22 +++- > include/bits.h | 79 ++++++++++++++ > include/boot.h | 2 + > include/platform.h | 20 ++++ > model.lds.S | 20 ++-- > 25 files changed, 668 insertions(+), 230 deletions(-) > create mode 100644 arch/aarch32/include/asm/psci.h > create mode 100644 arch/aarch32/init.c > create mode 100644 arch/aarch64/include/asm/psci.h > create mode 100644 arch/aarch64/init.c > create mode 100644 common/init.c > create mode 100644 include/bits.h > create mode 100644 include/platform.h > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel