From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B50BEC433F5 for ; Fri, 14 Jan 2022 15:33:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2WmfoSH+wkKw9OLhjLHAmtqt9CTaA6+rtqnBhxWEOgE=; b=pcD/RzYcA0TWsx MJuEVeWQ6LMjd5MEoq2/lgA1vWMfaFJWqqzN45vRY09vDz5M9sRkgka5/JCJeXfwal+JETY9uGnNq 0dCX3AnPfupGfiYkDVxzE/GJ8zwy2eP4zNDE6lAUK9kmlOGpF2LSjqmWlEdI2tkM3Lkh8jYly59Wt RYZr7OmtsgOrNpmHWYAnl1ynKquj/h7o9VJGVTzRBTL5A4kshhORGYdOI7pUfO7GDgp2V3K0gEynY WhYZqiS4lrKWZ0FLUkbuh90KF0a7kL1ILQNJeJSExEmwayWDqRBwCzIpCWV85SHOjxuu2oh5HgDK+ UgbLXPyomur7/LUvL98Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8OZ9-009chR-Iu; Fri, 14 Jan 2022 15:32:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n8OZ6-009cgb-5C for linux-arm-kernel@lists.infradead.org; Fri, 14 Jan 2022 15:32:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2003F6D; Fri, 14 Jan 2022 07:32:31 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 291EE3F774; Fri, 14 Jan 2022 07:32:30 -0800 (PST) Date: Fri, 14 Jan 2022 15:32:27 +0000 From: Andre Przywara To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Jaxson.Han@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com Subject: Re: [bootwrapper PATCH v2 03/13] aarch64: add system register accessors Message-ID: <20220114153227.3f2a2d09@donnerap.cambridge.arm.com> In-Reply-To: <20220114105653.3003399-4-mark.rutland@arm.com> References: <20220114105653.3003399-1-mark.rutland@arm.com> <20220114105653.3003399-4-mark.rutland@arm.com> Organization: ARM X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220114_073232_334346_B50D0017 X-CRM114-Status: GOOD ( 19.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 14 Jan 2022 10:56:43 +0000 Mark Rutland wrote: Hi Mark, > We open code the use of mrs/msr for specific registers, which is > somewhat tedious. Add macros to do this generically, along with a helper > to extract a specific register field. Existing C usage is converted to > the new helpers, and register definitions moved to a common location. > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland Stared at and verified the architecture bits used in here: Reviewed-by: Andre Przywara Cheers, Andre > --- > arch/aarch64/include/asm/cpu.h | 41 ++++++++++++++++++++++--------- > arch/aarch64/include/asm/gic-v3.h | 10 +++----- > 2 files changed, 32 insertions(+), 19 deletions(-) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 63eb1c3..1053414 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -9,10 +9,14 @@ > #ifndef __ASM_AARCH64_CPU_H > #define __ASM_AARCH64_CPU_H > > +#include > + > #define MPIDR_ID_BITS 0xff00ffffff > > #define CURRENTEL_EL3 (3 << 2) > > +#define ID_AA64PFR0_EL1_GIC BITS(27, 24) > + > /* > * RES1 bits, little-endian, caches and MMU off, no alignment checking, > * no WXN. > @@ -29,6 +33,12 @@ > > #define CPTR_EL3_EZ (1 << 8) > > +#define ICC_SRE_EL2 S3_4_C12_C9_5 > +#define ICC_SRE_EL3 S3_6_C12_C12_5 > +#define ICC_CTLR_EL1 S3_0_C12_C12_4 > +#define ICC_CTLR_EL3 S3_6_C12_C12_4 > +#define ICC_PMR_EL1 S3_0_C4_C6_0 > + > #define ZCR_EL3 s3_6_c1_c2_0 > #define ZCR_EL3_LEN_MASK 0x1ff > > @@ -50,20 +60,27 @@ > > #define sevl() asm volatile ("sevl\n" : : : "memory") > > -static inline unsigned long read_mpidr(void) > -{ > - unsigned long mpidr; > +#define __str(def) #def > > - asm volatile ("mrs %0, mpidr_el1\n" : "=r" (mpidr)); > - return mpidr & MPIDR_ID_BITS; > -} > +#define mrs(reg) \ > +({ \ > + unsigned long __mrs_val; \ > + asm volatile("mrs %0, " __str(reg) : "=r" (__mrs_val)); \ > + __mrs_val; \ > +}) > > -static inline uint64_t read_id_aa64pfr0(void) > -{ > - uint64_t val; > +#define msr(reg, val) \ > +do { \ > + unsigned long __msr_val = val; \ > + asm volatile("msr " __str(reg) ", %0" : : "r" (__msr_val)); \ > +} while (0) > + > +#define mrs_field(reg, field) \ > + BITS_EXTRACT(mrs(reg), (reg##_##field)) > > - asm volatile ("mrs %0, id_aa64pfr0_el1\n" : "=r" (val)); > - return val; > +static inline unsigned long read_mpidr(void) > +{ > + return mrs(mpidr_el1) & MPIDR_ID_BITS; > } > > static inline void iciallu(void) > @@ -73,7 +90,7 @@ static inline void iciallu(void) > > static inline int has_gicv3_sysreg(void) > { > - return !!((read_id_aa64pfr0() >> 24) & 0xf); > + return !!mrs_field(ID_AA64PFR0_EL1, GIC); > } > > #endif /* !__ASSEMBLY__ */ > diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h > index 5b32380..2447480 100644 > --- a/arch/aarch64/include/asm/gic-v3.h > +++ b/arch/aarch64/include/asm/gic-v3.h > @@ -9,20 +9,16 @@ > #ifndef __ASM_AARCH64_GICV3_H > #define __ASM_AARCH64_GICV3_H > > -#define ICC_SRE_EL2 "S3_4_C12_C9_5" > -#define ICC_SRE_EL3 "S3_6_C12_C12_5" > -#define ICC_CTLR_EL1 "S3_0_C12_C12_4" > -#define ICC_CTLR_EL3 "S3_6_C12_C12_4" > -#define ICC_PMR_EL1 "S3_0_C4_C6_0" > +#include > > static inline void gic_write_icc_sre(uint32_t val) > { > - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); > + msr(ICC_SRE_EL3, val); > } > > static inline void gic_write_icc_ctlr(uint32_t val) > { > - asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); > + msr(ICC_CTLR_EL3, val); > } > > #endif _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel