* [PATCH v4 0/4] support subsets of virtual memory extension
@ 2022-01-16 2:59 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
Specification:
https://github.com/riscv/virtual-memory/tree/main/specs
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v4
To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.
This implementation can pass the riscv-tests for rv64ssvnapot.
v4:
* fix encodings for hinval_vvma and hinval_gvma
* partition inner PTE check into several steps added in first, second and fourth commits
* improve commit messages to describe changes
v3:
* drop "x-" in exposed properties
v2:
* add extension check for svnapot and svpbmt
Weiwei Li (4):
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
target/riscv: add support for svnapot extension
target/riscv: add support for svinval extension
target/riscv: add support for svpbmt extension
target/riscv/cpu.c | 4 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 4 ++
target/riscv/cpu_helper.c | 27 ++++++--
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
7 files changed, 117 insertions(+), 4 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 0/4] support subsets of virtual memory extension
@ 2022-01-16 2:59 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
Specification:
https://github.com/riscv/virtual-memory/tree/main/specs
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v4
To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.
This implementation can pass the riscv-tests for rv64ssvnapot.
v4:
* fix encodings for hinval_vvma and hinval_gvma
* partition inner PTE check into several steps added in first, second and fourth commits
* improve commit messages to describe changes
v3:
* drop "x-" in exposed properties
v2:
* add extension check for svnapot and svpbmt
Weiwei Li (4):
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
target/riscv: add support for svnapot extension
target/riscv: add support for svinval extension
target/riscv: add support for svpbmt extension
target/riscv/cpu.c | 4 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 4 ++
target/riscv/cpu_helper.c | 27 ++++++--
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
7 files changed, 117 insertions(+), 4 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
2022-01-16 2:59 ` Weiwei Li
@ 2022-01-16 2:59 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 434a83e66a..d84cde424d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -626,6 +626,9 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
@ 2022-01-16 2:59 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 434a83e66a..d84cde424d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -626,6 +626,9 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 2/4] target/riscv: add support for svnapot extension
2022-01-16 2:59 ` Weiwei Li
@ 2022-01-16 2:59 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 22 +++++++++++++++++-----
4 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..ff6c86c85b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d63086765..d3d17cde82 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5a6d49aa64..bc23e3b523 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -486,6 +486,7 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_N 0x8000000000000000 /* NAPOT translation */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d84cde424d..832a2dd79c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,14 +619,17 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = pte >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
- if (!(pte & PTE_V)) {
+ RISCVCPU *cpu = env_archcpu(env);
+ if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+ return TRANSLATE_FAIL;
+ } else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U)) {
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
@@ -702,8 +705,17 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
- *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
- (addr & ~TARGET_PAGE_MASK);
+
+ int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
+ if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
+ (napot_bits != 0 && napot_bits != 4)) {
+ return TRANSLATE_FAIL;
+ }
+
+ *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << ptshift) - 1))
+ ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 2/4] target/riscv: add support for svnapot extension
@ 2022-01-16 2:59 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 22 +++++++++++++++++-----
4 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..ff6c86c85b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d63086765..d3d17cde82 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5a6d49aa64..bc23e3b523 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -486,6 +486,7 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_N 0x8000000000000000 /* NAPOT translation */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d84cde424d..832a2dd79c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,14 +619,17 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = pte >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
- if (!(pte & PTE_V)) {
+ RISCVCPU *cpu = env_archcpu(env);
+ if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+ return TRANSLATE_FAIL;
+ } else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U)) {
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
@@ -702,8 +705,17 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
- *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
- (addr & ~TARGET_PAGE_MASK);
+
+ int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
+ if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
+ (napot_bits != 0 && napot_bits != 4)) {
+ return TRANSLATE_FAIL;
+ }
+
+ *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << napot_bits) - 1)) |
+ (vpn & (((target_ulong)1 << ptshift) - 1))
+ ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 3/4] target/riscv: add support for svinval extension
2022-01-16 2:59 ` Weiwei Li
@ 2022-01-16 2:59 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
5 files changed, 85 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ff6c86c85b..45ac98e06b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d3d17cde82..c3d1845ca1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svinval;
bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..1d3ff1efe1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -809,3 +809,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_w_inval 0001100 00000 00000 000 00000 1110011
+sfence_inval_ir 0001100 00001 00000 000 00000 1110011
+hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
+hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 0000000000..1dde665661
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2021 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_SVINVAL(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as sfence.vma currently */
+ REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.vvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.gvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 615048ec87..4e5a9660a4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -838,6 +838,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_svinval.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 3/4] target/riscv: add support for svinval extension
@ 2022-01-16 2:59 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
target/riscv/translate.c | 1 +
5 files changed, 85 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ff6c86c85b..45ac98e06b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d3d17cde82..c3d1845ca1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svinval;
bool ext_svnapot;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..1d3ff1efe1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -809,3 +809,10 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_w_inval 0001100 00000 00000 000 00000 1110011
+sfence_inval_ir 0001100 00001 00000 000 00000 1110011
+hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
+hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 0000000000..1dde665661
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2021 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_SVINVAL(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as sfence.vma currently */
+ REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ REQUIRE_EXT(ctx, RVS);
+ /* Do nothing currently */
+ return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.vvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+ REQUIRE_SVINVAL(ctx);
+ /* Do the same as hfence.gvma currently */
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
+ return true;
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 615048ec87..4e5a9660a4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -838,6 +838,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_svinval.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 4/4] target/riscv: add support for svpbmt extension
2022-01-16 2:59 ` Weiwei Li
@ 2022-01-16 2:59 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bits check for inner PTE
- add reserved bits check for all PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 8 ++++++--
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 45ac98e06b..4f82bd00a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c3d1845ca1..53f314c752 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,7 @@ struct RISCVCPU {
bool ext_icsr;
bool ext_svinval;
bool ext_svnapot;
+ bool ext_svpbmt;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bc23e3b523..ee294c1d0b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -486,7 +486,10 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
+#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
#define PTE_N 0x8000000000000000 /* NAPOT translation */
+#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 832a2dd79c..f90766e026 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,17 +619,21 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
return TRANSLATE_FAIL;
+ } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ return TRANSLATE_FAIL;
+ } else if (pte & PTE_RSVD) {
+ return TRANSLATE_FAIL;
} else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 4/4] target/riscv: add support for svpbmt extension
@ 2022-01-16 2:59 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-16 2:59 UTC (permalink / raw)
To: anup, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bits check for inner PTE
- add reserved bits check for all PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 8 ++++++--
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 45ac98e06b..4f82bd00a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c3d1845ca1..53f314c752 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,7 @@ struct RISCVCPU {
bool ext_icsr;
bool ext_svinval;
bool ext_svnapot;
+ bool ext_svpbmt;
bool ext_zfh;
bool ext_zfhmin;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index bc23e3b523..ee294c1d0b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -486,7 +486,10 @@ typedef enum {
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
+#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
+#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
#define PTE_N 0x8000000000000000 /* NAPOT translation */
+#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 832a2dd79c..f90766e026 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -619,17 +619,21 @@ restart:
return TRANSLATE_FAIL;
}
- hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
return TRANSLATE_FAIL;
+ } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ return TRANSLATE_FAIL;
+ } else if (pte & PTE_RSVD) {
+ return TRANSLATE_FAIL;
} else if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+ if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
return TRANSLATE_FAIL;
}
base = ppn << PGSHIFT;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/4] target/riscv: add support for svnapot extension
2022-01-16 2:59 ` Weiwei Li
@ 2022-01-16 4:29 ` Anup Patel
-1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-16 4:29 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟),
open list:RISC-V, wangjunqiang, Bin Meng, QEMU Developers,
Alistair Francis, Palmer Dabbelt
On Sun, Jan 16, 2022 at 8:31 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - add PTE_N bit
> - add PTE_N bit check for inner PTE
> - update address translation to support 64KiB continuous region (napot_bits = 4)
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 22 +++++++++++++++++-----
> 4 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9bc25d3055..ff6c86c85b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> +
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4d63086765..d3d17cde82 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -327,6 +327,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_svnapot;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5a6d49aa64..bc23e3b523 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,6 +486,7 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_N 0x8000000000000000 /* NAPOT translation */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d84cde424d..832a2dd79c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,14 +619,17 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = pte >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
>
> - if (!(pte & PTE_V)) {
> + RISCVCPU *cpu = env_archcpu(env);
> + if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> + return TRANSLATE_FAIL;
> + } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> - if (pte & (PTE_D | PTE_A | PTE_U)) {
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
> return TRANSLATE_FAIL;
> }
> base = ppn << PGSHIFT;
> @@ -702,8 +705,17 @@ restart:
> /* for superpage mappings, make a fake leaf PTE for the TLB's
> benefit. */
> target_ulong vpn = addr >> PGSHIFT;
> - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> - (addr & ~TARGET_PAGE_MASK);
> +
> + int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
> + if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
> + (napot_bits != 0 && napot_bits != 4)) {
> + return TRANSLATE_FAIL;
> + }
> +
> + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << ptshift) - 1))
> + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
>
> /* set permissions on the TLB entry */
> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/4] target/riscv: add support for svnapot extension
@ 2022-01-16 4:29 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2022-01-16 4:29 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
QEMU Developers, wangjunqiang, Wei Wu (吴伟)
On Sun, Jan 16, 2022 at 8:31 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - add PTE_N bit
> - add PTE_N bit check for inner PTE
> - update address translation to support 64KiB continuous region (napot_bits = 4)
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 22 +++++++++++++++++-----
> 4 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9bc25d3055..ff6c86c85b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -668,6 +668,8 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> +
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 4d63086765..d3d17cde82 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -327,6 +327,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_svnapot;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5a6d49aa64..bc23e3b523 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,6 +486,7 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_N 0x8000000000000000 /* NAPOT translation */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d84cde424d..832a2dd79c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,14 +619,17 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = pte >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
>
> - if (!(pte & PTE_V)) {
> + RISCVCPU *cpu = env_archcpu(env);
> + if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> + return TRANSLATE_FAIL;
> + } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> - if (pte & (PTE_D | PTE_A | PTE_U)) {
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
> return TRANSLATE_FAIL;
> }
> base = ppn << PGSHIFT;
> @@ -702,8 +705,17 @@ restart:
> /* for superpage mappings, make a fake leaf PTE for the TLB's
> benefit. */
> target_ulong vpn = addr >> PGSHIFT;
> - *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
> - (addr & ~TARGET_PAGE_MASK);
> +
> + int napot_bits = ((pte & PTE_N) ? (ctzl(ppn) + 1) : 0);
> + if (((pte & PTE_N) && ((ppn == 0) || (i != (levels - 1)))) ||
> + (napot_bits != 0 && napot_bits != 4)) {
> + return TRANSLATE_FAIL;
> + }
> +
> + *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << napot_bits) - 1)) |
> + (vpn & (((target_ulong)1 << ptshift) - 1))
> + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
>
> /* set permissions on the TLB entry */
> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
2022-01-16 2:59 ` Weiwei Li
@ 2022-01-17 7:18 ` Guo Ren
-1 siblings, 0 replies; 16+ messages in thread
From: Guo Ren @ 2022-01-17 7:18 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟),
open list:RISC-V, Anup Patel, Wang Junqiang, bin.meng,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
> - add PTE_PBMT bits check for inner PTE
> - add reserved bits check for all PTE
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 8 ++++++--
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 45ac98e06b..4f82bd00a3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
>
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c3d1845ca1..53f314c752 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -329,6 +329,7 @@ struct RISCVCPU {
> bool ext_icsr;
> bool ext_svinval;
> bool ext_svnapot;
> + bool ext_svpbmt;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index bc23e3b523..ee294c1d0b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,7 +486,10 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
> #define PTE_N 0x8000000000000000 /* NAPOT translation */
> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 832a2dd79c..f90766e026 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,17 +619,21 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
This would break rv32. Please ref:
https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
>
> RISCVCPU *cpu = env_archcpu(env);
> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> return TRANSLATE_FAIL;
> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
> + return TRANSLATE_FAIL;
> + } else if (pte & PTE_RSVD) {
> + return TRANSLATE_FAIL;
> } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
> return TRANSLATE_FAIL;
> }
> base = ppn << PGSHIFT;
> --
> 2.17.1
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
@ 2022-01-17 7:18 ` Guo Ren
0 siblings, 0 replies; 16+ messages in thread
From: Guo Ren @ 2022-01-17 7:18 UTC (permalink / raw)
To: Weiwei Li
Cc: Anup Patel, Palmer Dabbelt, Alistair Francis, bin.meng,
open list:RISC-V, qemu-devel@nongnu.org Developers,
Wang Junqiang, Wei Wu (吴伟)
On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
> - add PTE_PBMT bits check for inner PTE
> - add reserved bits check for all PTE
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_helper.c | 8 ++++++--
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 45ac98e06b..4f82bd00a3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
>
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c3d1845ca1..53f314c752 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -329,6 +329,7 @@ struct RISCVCPU {
> bool ext_icsr;
> bool ext_svinval;
> bool ext_svnapot;
> + bool ext_svpbmt;
> bool ext_zfh;
> bool ext_zfhmin;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index bc23e3b523..ee294c1d0b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -486,7 +486,10 @@ typedef enum {
> #define PTE_A 0x040 /* Accessed */
> #define PTE_D 0x080 /* Dirty */
> #define PTE_SOFT 0x300 /* Reserved for Software */
> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
> #define PTE_N 0x8000000000000000 /* NAPOT translation */
> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
>
> /* Page table PPN shift amount */
> #define PTE_PPN_SHIFT 10
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 832a2dd79c..f90766e026 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -619,17 +619,21 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
This would break rv32. Please ref:
https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
>
> RISCVCPU *cpu = env_archcpu(env);
> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> return TRANSLATE_FAIL;
> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
> + return TRANSLATE_FAIL;
> + } else if (pte & PTE_RSVD) {
> + return TRANSLATE_FAIL;
> } else if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
> return TRANSLATE_FAIL;
> }
> base = ppn << PGSHIFT;
> --
> 2.17.1
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
2022-01-17 7:18 ` Guo Ren
@ 2022-01-17 8:28 ` Weiwei Li
-1 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-17 8:28 UTC (permalink / raw)
To: Guo Ren
Cc: Wei Wu (吴伟),
open list:RISC-V, Anup Patel, Wang Junqiang, bin.meng,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
在 2022/1/17 下午3:18, Guo Ren 写道:
> On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
>> - add PTE_PBMT bits check for inner PTE
>> - add reserved bits check for all PTE
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> Tested-by: Heiko Stuebner <heiko@sntech.de>
>> Reviewed-by: Anup Patel <anup@brainfault.org>
>> ---
>> target/riscv/cpu.c | 1 +
>> target/riscv/cpu.h | 1 +
>> target/riscv/cpu_bits.h | 3 +++
>> target/riscv/cpu_helper.c | 8 ++++++--
>> 4 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 45ac98e06b..4f82bd00a3 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
>>
>> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
>> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>>
>> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index c3d1845ca1..53f314c752 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -329,6 +329,7 @@ struct RISCVCPU {
>> bool ext_icsr;
>> bool ext_svinval;
>> bool ext_svnapot;
>> + bool ext_svpbmt;
>> bool ext_zfh;
>> bool ext_zfhmin;
>>
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index bc23e3b523..ee294c1d0b 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -486,7 +486,10 @@ typedef enum {
>> #define PTE_A 0x040 /* Accessed */
>> #define PTE_D 0x080 /* Dirty */
>> #define PTE_SOFT 0x300 /* Reserved for Software */
>> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
>> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
>> #define PTE_N 0x8000000000000000 /* NAPOT translation */
>> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
>>
>> /* Page table PPN shift amount */
>> #define PTE_PPN_SHIFT 10
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 832a2dd79c..f90766e026 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -619,17 +619,21 @@ restart:
>> return TRANSLATE_FAIL;
>> }
>>
>> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
>> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
> This would break rv32. Please ref:
> https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
>
Thanks for your comment . I'll merge this into our patchset.
Regards,
Weiwei Li
>> RISCVCPU *cpu = env_archcpu(env);
>> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
>> return TRANSLATE_FAIL;
>> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
>> + return TRANSLATE_FAIL;
>> + } else if (pte & PTE_RSVD) {
>> + return TRANSLATE_FAIL;
>> } else if (!(pte & PTE_V)) {
>> /* Invalid PTE */
>> return TRANSLATE_FAIL;
>> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
>> /* Inner PTE, continue walking */
>> - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
>> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
>> return TRANSLATE_FAIL;
>> }
>> base = ppn << PGSHIFT;
>> --
>> 2.17.1
>>
>>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
@ 2022-01-17 8:28 ` Weiwei Li
0 siblings, 0 replies; 16+ messages in thread
From: Weiwei Li @ 2022-01-17 8:28 UTC (permalink / raw)
To: Guo Ren
Cc: Anup Patel, Palmer Dabbelt, Alistair Francis, bin.meng,
open list:RISC-V, qemu-devel@nongnu.org Developers,
Wang Junqiang, Wei Wu (吴伟)
在 2022/1/17 下午3:18, Guo Ren 写道:
> On Sun, Jan 16, 2022 at 11:08 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
>> - add PTE_PBMT bits check for inner PTE
>> - add reserved bits check for all PTE
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> Tested-by: Heiko Stuebner <heiko@sntech.de>
>> Reviewed-by: Anup Patel <anup@brainfault.org>
>> ---
>> target/riscv/cpu.c | 1 +
>> target/riscv/cpu.h | 1 +
>> target/riscv/cpu_bits.h | 3 +++
>> target/riscv/cpu_helper.c | 8 ++++++--
>> 4 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 45ac98e06b..4f82bd00a3 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -670,6 +670,7 @@ static Property riscv_cpu_properties[] = {
>>
>> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
>> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>>
>> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index c3d1845ca1..53f314c752 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -329,6 +329,7 @@ struct RISCVCPU {
>> bool ext_icsr;
>> bool ext_svinval;
>> bool ext_svnapot;
>> + bool ext_svpbmt;
>> bool ext_zfh;
>> bool ext_zfhmin;
>>
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index bc23e3b523..ee294c1d0b 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -486,7 +486,10 @@ typedef enum {
>> #define PTE_A 0x040 /* Accessed */
>> #define PTE_D 0x080 /* Dirty */
>> #define PTE_SOFT 0x300 /* Reserved for Software */
>> +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */
>> +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */
>> #define PTE_N 0x8000000000000000 /* NAPOT translation */
>> +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */
>>
>> /* Page table PPN shift amount */
>> #define PTE_PPN_SHIFT 10
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 832a2dd79c..f90766e026 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -619,17 +619,21 @@ restart:
>> return TRANSLATE_FAIL;
>> }
>>
>> - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT;
>> + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT;
> This would break rv32. Please ref:
> https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
>
Thanks for your comment . I'll merge this into our patchset.
Regards,
Weiwei Li
>> RISCVCPU *cpu = env_archcpu(env);
>> if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) {
>> return TRANSLATE_FAIL;
>> + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
>> + return TRANSLATE_FAIL;
>> + } else if (pte & PTE_RSVD) {
>> + return TRANSLATE_FAIL;
>> } else if (!(pte & PTE_V)) {
>> /* Invalid PTE */
>> return TRANSLATE_FAIL;
>> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
>> /* Inner PTE, continue walking */
>> - if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
>> + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) {
>> return TRANSLATE_FAIL;
>> }
>> base = ppn << PGSHIFT;
>> --
>> 2.17.1
>>
>>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-01-17 8:32 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-16 2:59 [PATCH v4 0/4] support subsets of virtual memory extension Weiwei Li
2022-01-16 2:59 ` Weiwei Li
2022-01-16 2:59 ` [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li
2022-01-16 2:59 ` Weiwei Li
2022-01-16 2:59 ` [PATCH v4 2/4] target/riscv: add support for svnapot extension Weiwei Li
2022-01-16 2:59 ` Weiwei Li
2022-01-16 4:29 ` Anup Patel
2022-01-16 4:29 ` Anup Patel
2022-01-16 2:59 ` [PATCH v4 3/4] target/riscv: add support for svinval extension Weiwei Li
2022-01-16 2:59 ` Weiwei Li
2022-01-16 2:59 ` [PATCH v4 4/4] target/riscv: add support for svpbmt extension Weiwei Li
2022-01-16 2:59 ` Weiwei Li
2022-01-17 7:18 ` Guo Ren
2022-01-17 7:18 ` Guo Ren
2022-01-17 8:28 ` Weiwei Li
2022-01-17 8:28 ` Weiwei Li
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