* [PATCH v1 00/14] Add mdp support for mt8195
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add a chip independence architecture to make
mt8195 mdp driver compatible with previous soc.
Add dual-pipe feature and memory reconfiguration
to increase mdp performance.
Add below patch to support MDP driver on MT8195
[PATCH v1 1/14] soc: mediatek: mmsys: expand MDP enum for chip independence
architecture
[PATCH v1 2/14] soc: mediatek: mutex: expand parameter for mdp mutex function
[PATCH v1 3/14] soc: mediatek: mmsys: support mt8195 vppsys0/1
[PATCH v1 4/14] soc: mediatek: mutex: support mt8195 vppsys0/1
[PATCH v1 5/14] media: platform: mtk-mdp3: add chip independence architecture
[PATCH v1 6/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP
[PATCH v1 7/14] media: platform: mtk-mdp3: Add platform configuration for MT8195
[PATCH v1 8/14] media: platform: mtk-mdp3: Add engine setting for MT8195
[PATCH v1 9/14] media: platform: mtk-mdp3: Add support MT8195
[PATCH v1 10/14] media: platform: mtk-mdp3: Add dual pipe feature support
[PATCH v1 11/14] media: platform: mtk-mdp3: Revise frame change criteria
[PATCH v1 12/14] media: platform: mtk-mdp3: Reconfigure shared memory
[PATCH v1 13/14] arm64: dts: mt8195: add mdp3 node
[PATCH v1 14/14] dt-bindings: media: mediatek: mdp3: add yaml for new modules added in
mt8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
.../bindings/media/mediatek,mdp3-aal.yaml | 56 +
.../bindings/media/mediatek,mdp3-color.yaml | 56 +
.../bindings/media/mediatek,mdp3-fg.yaml | 55 +
.../bindings/media/mediatek,mdp3-hdr.yaml | 55 +
.../bindings/media/mediatek,mdp3-merge.yaml | 54 +
.../bindings/media/mediatek,mdp3-ovl.yaml | 53 +
.../bindings/media/mediatek,mdp3-pad.yaml | 56 +
.../bindings/media/mediatek,mdp3-rdma.yaml | 28 +
.../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
.../bindings/media/mediatek,mdp3-split.yaml | 58 +
.../bindings/media/mediatek,mdp3-stitch.yaml | 53 +
.../bindings/media/mediatek,mdp3-tcc.yaml | 54 +
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +
.../bindings/media/mediatek,mdp3-wrot.yaml | 3 +
.../bindings/soc/mediatek/mediatek,mutex.yaml | 6 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 633 +++++++
drivers/media/platform/mtk-mdp3/mdp_reg_aal.h | 24 +
.../media/platform/mtk-mdp3/mdp_reg_color.h | 29 +
drivers/media/platform/mtk-mdp3/mdp_reg_fg.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h | 31 +
.../media/platform/mtk-mdp3/mdp_reg_merge.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h | 24 +
drivers/media/platform/mtk-mdp3/mdp_reg_pad.h | 20 +
.../media/platform/mtk-mdp3/mdp_reg_rdma.h | 31 +
drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 2 +
.../media/platform/mtk-mdp3/mdp_reg_tdshp.h | 116 ++
.../media/platform/mtk-mdp3/mdp_reg_wrot.h | 18 +
drivers/media/platform/mtk-mdp3/mt8183_mdp.h | 411 +++++
drivers/media/platform/mtk-mdp3/mt8195_mdp.h | 683 ++++++++
drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 219 ++-
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 782 +++++++--
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 4 +
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1453 +++++++++++++++--
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 90 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 118 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 42 +-
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 27 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 356 ++--
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 292 ++--
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 106 +-
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 9 +
drivers/soc/mediatek/mt8195-mmsys.h | 23 +
drivers/soc/mediatek/mtk-mmsys.c | 22 +
drivers/soc/mediatek/mtk-mmsys.h | 3 +
drivers/soc/mediatek/mtk-mutex.c | 79 +-
include/linux/soc/mediatek/mtk-mmsys.h | 92 +-
include/linux/soc/mediatek/mtk-mutex.h | 2 +-
48 files changed, 5648 insertions(+), 791 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_color.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mt8183_mdp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mt8195_mdp.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 00/14] Add mdp support for mt8195
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add a chip independence architecture to make
mt8195 mdp driver compatible with previous soc.
Add dual-pipe feature and memory reconfiguration
to increase mdp performance.
Add below patch to support MDP driver on MT8195
[PATCH v1 1/14] soc: mediatek: mmsys: expand MDP enum for chip independence
architecture
[PATCH v1 2/14] soc: mediatek: mutex: expand parameter for mdp mutex function
[PATCH v1 3/14] soc: mediatek: mmsys: support mt8195 vppsys0/1
[PATCH v1 4/14] soc: mediatek: mutex: support mt8195 vppsys0/1
[PATCH v1 5/14] media: platform: mtk-mdp3: add chip independence architecture
[PATCH v1 6/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP
[PATCH v1 7/14] media: platform: mtk-mdp3: Add platform configuration for MT8195
[PATCH v1 8/14] media: platform: mtk-mdp3: Add engine setting for MT8195
[PATCH v1 9/14] media: platform: mtk-mdp3: Add support MT8195
[PATCH v1 10/14] media: platform: mtk-mdp3: Add dual pipe feature support
[PATCH v1 11/14] media: platform: mtk-mdp3: Revise frame change criteria
[PATCH v1 12/14] media: platform: mtk-mdp3: Reconfigure shared memory
[PATCH v1 13/14] arm64: dts: mt8195: add mdp3 node
[PATCH v1 14/14] dt-bindings: media: mediatek: mdp3: add yaml for new modules added in
mt8195
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
.../bindings/media/mediatek,mdp3-aal.yaml | 56 +
.../bindings/media/mediatek,mdp3-color.yaml | 56 +
.../bindings/media/mediatek,mdp3-fg.yaml | 55 +
.../bindings/media/mediatek,mdp3-hdr.yaml | 55 +
.../bindings/media/mediatek,mdp3-merge.yaml | 54 +
.../bindings/media/mediatek,mdp3-ovl.yaml | 53 +
.../bindings/media/mediatek,mdp3-pad.yaml | 56 +
.../bindings/media/mediatek,mdp3-rdma.yaml | 28 +
.../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
.../bindings/media/mediatek,mdp3-split.yaml | 58 +
.../bindings/media/mediatek,mdp3-stitch.yaml | 53 +
.../bindings/media/mediatek,mdp3-tcc.yaml | 54 +
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +
.../bindings/media/mediatek,mdp3-wrot.yaml | 3 +
.../bindings/soc/mediatek/mediatek,mutex.yaml | 6 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 633 +++++++
drivers/media/platform/mtk-mdp3/mdp_reg_aal.h | 24 +
.../media/platform/mtk-mdp3/mdp_reg_color.h | 29 +
drivers/media/platform/mtk-mdp3/mdp_reg_fg.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h | 31 +
.../media/platform/mtk-mdp3/mdp_reg_merge.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h | 24 +
drivers/media/platform/mtk-mdp3/mdp_reg_pad.h | 20 +
.../media/platform/mtk-mdp3/mdp_reg_rdma.h | 31 +
drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 2 +
.../media/platform/mtk-mdp3/mdp_reg_tdshp.h | 116 ++
.../media/platform/mtk-mdp3/mdp_reg_wrot.h | 18 +
drivers/media/platform/mtk-mdp3/mt8183_mdp.h | 411 +++++
drivers/media/platform/mtk-mdp3/mt8195_mdp.h | 683 ++++++++
drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 219 ++-
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 782 +++++++--
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 4 +
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1453 +++++++++++++++--
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 90 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 118 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 42 +-
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 27 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 356 ++--
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 292 ++--
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 106 +-
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 9 +
drivers/soc/mediatek/mt8195-mmsys.h | 23 +
drivers/soc/mediatek/mtk-mmsys.c | 22 +
drivers/soc/mediatek/mtk-mmsys.h | 3 +
drivers/soc/mediatek/mtk-mutex.c | 79 +-
include/linux/soc/mediatek/mtk-mmsys.h | 92 +-
include/linux/soc/mediatek/mtk-mutex.h | 2 +-
48 files changed, 5648 insertions(+), 791 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_color.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mt8183_mdp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mt8195_mdp.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v1 01/14] soc: mediatek: mmsys: expand MDP enum for chip independence architecture
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Expand mdp related enum for chip independence architecture
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
This patch is base on [1]
[1] soc: mediatek: mmsys: add support for ISP control
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220104091712.25670-3-moudy.ho@mediatek.com/
---
include/linux/soc/mediatek/mtk-mmsys.h | 88 ++++++++++++++++++++------
1 file changed, 70 insertions(+), 18 deletions(-)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index c0ba22ad7229..a772e53af9b5 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -79,33 +79,85 @@ enum mtk_mdp_comp_id {
/* MDP */
MDP_COMP_CAMIN, /* 9 */
MDP_COMP_CAMIN2, /* 10 */
- MDP_COMP_RDMA0, /* 11 */
- MDP_COMP_AAL0, /* 12 */
- MDP_COMP_CCORR0, /* 13 */
- MDP_COMP_RSZ0, /* 14 */
- MDP_COMP_RSZ1, /* 15 */
- MDP_COMP_TDSHP0, /* 16 */
- MDP_COMP_COLOR0, /* 17 */
- MDP_COMP_PATH0_SOUT, /* 18 */
- MDP_COMP_PATH1_SOUT, /* 19 */
- MDP_COMP_WROT0, /* 20 */
- MDP_COMP_WDMA, /* 21 */
-
- /* Dummy Engine */
- MDP_COMP_RDMA1, /* 22 */
- MDP_COMP_RSZ2, /* 23 */
- MDP_COMP_TDSHP1, /* 24 */
- MDP_COMP_WROT1, /* 25 */
+ MDP_COMP_SPLIT, /* 11 */
+ MDP_COMP_SPLIT2, /* 12 */
+ MDP_COMP_RDMA0, /* 13 */
+ MDP_COMP_RDMA1, /* 14 */
+ MDP_COMP_RDMA2, /* 15 */
+ MDP_COMP_RDMA3, /* 16 */
+ MDP_COMP_STITCH, /* 17 */
+ MDP_COMP_FG0, /* 18 */
+ MDP_COMP_FG1, /* 19 */
+ MDP_COMP_FG2, /* 20 */
+ MDP_COMP_FG3, /* 21 */
+ MDP_COMP_TO_SVPP2MOUT, /* 22 */
+ MDP_COMP_TO_SVPP3MOUT, /* 23 */
+ MDP_COMP_TO_WARP0MOUT, /* 24 */
+ MDP_COMP_TO_WARP1MOUT, /* 25 */
+ MDP_COMP_VPP0_SOUT, /* 26 */
+ MDP_COMP_VPP1_SOUT, /* 27 */
+ MDP_COMP_PQ0_SOUT, /* 28 */
+ MDP_COMP_PQ1_SOUT, /* 29 */
+ MDP_COMP_HDR0, /* 30 */
+ MDP_COMP_HDR1, /* 31 */
+ MDP_COMP_HDR2, /* 32 */
+ MDP_COMP_HDR3, /* 33 */
+ MDP_COMP_AAL0, /* 34 */
+ MDP_COMP_AAL1, /* 35 */
+ MDP_COMP_AAL2, /* 36 */
+ MDP_COMP_AAL3, /* 37 */
+ MDP_COMP_CCORR0, /* 38 */
+ MDP_COMP_RSZ0, /* 39 */
+ MDP_COMP_RSZ1, /* 40 */
+ MDP_COMP_RSZ2, /* 41 */
+ MDP_COMP_RSZ3, /* 42 */
+ MDP_COMP_TDSHP0, /* 43 */
+ MDP_COMP_TDSHP1, /* 44 */
+ MDP_COMP_TDSHP2, /* 45 */
+ MDP_COMP_TDSHP3, /* 46 */
+ MDP_COMP_COLOR0, /* 47 */
+ MDP_COMP_COLOR1, /* 48 */
+ MDP_COMP_COLOR2, /* 49 */
+ MDP_COMP_COLOR3, /* 50 */
+ MDP_COMP_OVL0, /* 51 */
+ MDP_COMP_OVL1, /* 52 */
+ MDP_COMP_PAD0, /* 53 */
+ MDP_COMP_PAD1, /* 54 */
+ MDP_COMP_PAD2, /* 55 */
+ MDP_COMP_PAD3, /* 56 */
+ MDP_COMP_TCC0, /* 57 */
+ MDP_COMP_TCC1, /* 58 */
+ MDP_COMP_WROT0, /* 59 */
+ MDP_COMP_WROT1, /* 60 */
+ MDP_COMP_WROT2, /* 61 */
+ MDP_COMP_WROT3, /* 62 */
+ MDP_COMP_WDMA, /* 63 */
+ MDP_COMP_MERGE2, /* 64 */
+ MDP_COMP_MERGE3, /* 65 */
+ MDP_COMP_PATH0_SOUT, /* 66 */
+ MDP_COMP_PATH1_SOUT, /* 67 */
+ MDP_COMP_VDO0DL0, /* 68 */
+ MDP_COMP_VDO1DL0, /* 69 */
+ MDP_COMP_VDO0DL1, /* 70 */
+ MDP_COMP_VDO1DL1, /* 71 */
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
enum mtk_mdp_pipe_id {
+ MDP_PIPE_NONE = -1,
MDP_PIPE_RDMA0,
MDP_PIPE_IMGI,
MDP_PIPE_WPEI,
MDP_PIPE_WPEI2,
- MDP_PIPE_MAX
+ MDP_PIPE_RDMA1,
+ MDP_PIPE_RDMA2,
+ MDP_PIPE_RDMA3,
+ MDP_PIPE_SPLIT,
+ MDP_PIPE_SPLIT2,
+ MDP_PIPE_VPP0_SOUT,
+ MDP_PIPE_VPP1_SOUT,
+ MDP_PIPE_MAX,
};
enum mtk_isp_ctrl {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 01/14] soc: mediatek: mmsys: expand MDP enum for chip independence architecture
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Expand mdp related enum for chip independence architecture
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
This patch is base on [1]
[1] soc: mediatek: mmsys: add support for ISP control
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220104091712.25670-3-moudy.ho@mediatek.com/
---
include/linux/soc/mediatek/mtk-mmsys.h | 88 ++++++++++++++++++++------
1 file changed, 70 insertions(+), 18 deletions(-)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index c0ba22ad7229..a772e53af9b5 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -79,33 +79,85 @@ enum mtk_mdp_comp_id {
/* MDP */
MDP_COMP_CAMIN, /* 9 */
MDP_COMP_CAMIN2, /* 10 */
- MDP_COMP_RDMA0, /* 11 */
- MDP_COMP_AAL0, /* 12 */
- MDP_COMP_CCORR0, /* 13 */
- MDP_COMP_RSZ0, /* 14 */
- MDP_COMP_RSZ1, /* 15 */
- MDP_COMP_TDSHP0, /* 16 */
- MDP_COMP_COLOR0, /* 17 */
- MDP_COMP_PATH0_SOUT, /* 18 */
- MDP_COMP_PATH1_SOUT, /* 19 */
- MDP_COMP_WROT0, /* 20 */
- MDP_COMP_WDMA, /* 21 */
-
- /* Dummy Engine */
- MDP_COMP_RDMA1, /* 22 */
- MDP_COMP_RSZ2, /* 23 */
- MDP_COMP_TDSHP1, /* 24 */
- MDP_COMP_WROT1, /* 25 */
+ MDP_COMP_SPLIT, /* 11 */
+ MDP_COMP_SPLIT2, /* 12 */
+ MDP_COMP_RDMA0, /* 13 */
+ MDP_COMP_RDMA1, /* 14 */
+ MDP_COMP_RDMA2, /* 15 */
+ MDP_COMP_RDMA3, /* 16 */
+ MDP_COMP_STITCH, /* 17 */
+ MDP_COMP_FG0, /* 18 */
+ MDP_COMP_FG1, /* 19 */
+ MDP_COMP_FG2, /* 20 */
+ MDP_COMP_FG3, /* 21 */
+ MDP_COMP_TO_SVPP2MOUT, /* 22 */
+ MDP_COMP_TO_SVPP3MOUT, /* 23 */
+ MDP_COMP_TO_WARP0MOUT, /* 24 */
+ MDP_COMP_TO_WARP1MOUT, /* 25 */
+ MDP_COMP_VPP0_SOUT, /* 26 */
+ MDP_COMP_VPP1_SOUT, /* 27 */
+ MDP_COMP_PQ0_SOUT, /* 28 */
+ MDP_COMP_PQ1_SOUT, /* 29 */
+ MDP_COMP_HDR0, /* 30 */
+ MDP_COMP_HDR1, /* 31 */
+ MDP_COMP_HDR2, /* 32 */
+ MDP_COMP_HDR3, /* 33 */
+ MDP_COMP_AAL0, /* 34 */
+ MDP_COMP_AAL1, /* 35 */
+ MDP_COMP_AAL2, /* 36 */
+ MDP_COMP_AAL3, /* 37 */
+ MDP_COMP_CCORR0, /* 38 */
+ MDP_COMP_RSZ0, /* 39 */
+ MDP_COMP_RSZ1, /* 40 */
+ MDP_COMP_RSZ2, /* 41 */
+ MDP_COMP_RSZ3, /* 42 */
+ MDP_COMP_TDSHP0, /* 43 */
+ MDP_COMP_TDSHP1, /* 44 */
+ MDP_COMP_TDSHP2, /* 45 */
+ MDP_COMP_TDSHP3, /* 46 */
+ MDP_COMP_COLOR0, /* 47 */
+ MDP_COMP_COLOR1, /* 48 */
+ MDP_COMP_COLOR2, /* 49 */
+ MDP_COMP_COLOR3, /* 50 */
+ MDP_COMP_OVL0, /* 51 */
+ MDP_COMP_OVL1, /* 52 */
+ MDP_COMP_PAD0, /* 53 */
+ MDP_COMP_PAD1, /* 54 */
+ MDP_COMP_PAD2, /* 55 */
+ MDP_COMP_PAD3, /* 56 */
+ MDP_COMP_TCC0, /* 57 */
+ MDP_COMP_TCC1, /* 58 */
+ MDP_COMP_WROT0, /* 59 */
+ MDP_COMP_WROT1, /* 60 */
+ MDP_COMP_WROT2, /* 61 */
+ MDP_COMP_WROT3, /* 62 */
+ MDP_COMP_WDMA, /* 63 */
+ MDP_COMP_MERGE2, /* 64 */
+ MDP_COMP_MERGE3, /* 65 */
+ MDP_COMP_PATH0_SOUT, /* 66 */
+ MDP_COMP_PATH1_SOUT, /* 67 */
+ MDP_COMP_VDO0DL0, /* 68 */
+ MDP_COMP_VDO1DL0, /* 69 */
+ MDP_COMP_VDO0DL1, /* 70 */
+ MDP_COMP_VDO1DL1, /* 71 */
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
enum mtk_mdp_pipe_id {
+ MDP_PIPE_NONE = -1,
MDP_PIPE_RDMA0,
MDP_PIPE_IMGI,
MDP_PIPE_WPEI,
MDP_PIPE_WPEI2,
- MDP_PIPE_MAX
+ MDP_PIPE_RDMA1,
+ MDP_PIPE_RDMA2,
+ MDP_PIPE_RDMA3,
+ MDP_PIPE_SPLIT,
+ MDP_PIPE_SPLIT2,
+ MDP_PIPE_VPP0_SOUT,
+ MDP_PIPE_VPP1_SOUT,
+ MDP_PIPE_MAX,
};
enum mtk_isp_ctrl {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 02/14] soc: mediatek: mutex: expand parameter for mdp mutex function
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Expand parameter for mdp mutex function
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
This patch is base on [1][2]
[1] soc: mediatek: mutex: add functions that operate registers by CMDQ
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220104091712.25670-5-moudy.ho@mediatek.com/
[2] media: platform: mtk-mdp3: add Mediatek MDP3 driver
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220105093758.6850-4-moudy.ho@mediatek.com/
---
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 3 ++-
drivers/soc/mediatek/mtk-mutex.c | 26 +++++++++++++------
include/linux/soc/mediatek/mtk-mutex.h | 2 +-
3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index 4a08502952d6..87751f0e2513 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -101,7 +101,8 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
}
if (subfrm->mutex_mod)
- mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod, cmd);
+ mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
+ 0, 0, cmd);
/* Set SOF */
for (index = 0; index < config->num_components; index++) {
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 89daab7e6863..7da0f44b6f9a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -27,8 +27,9 @@
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
-#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
-#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4)
+#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) ((mutex_sof_reg) + 0x20 * (n))
#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
@@ -180,6 +181,11 @@
#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
+#define MT8183_MDP_PIPE_IMGI MT8183_MUTEX_MDP_START
+#define MT8183_MDP_PIPE_RDMA0 (MT8183_MUTEX_MDP_START + 1)
+#define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
+#define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -364,10 +370,10 @@ static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
/* indicate which mutex is used by each pipepline */
static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
- [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
- [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
- [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
- [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+ [MDP_PIPE_IMGI] = MT8183_MDP_PIPE_IMGI,
+ [MDP_PIPE_RDMA0] = MT8183_MDP_PIPE_RDMA0,
+ [MDP_PIPE_WPEI] = MT8183_MDP_PIPE_WPEI,
+ [MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2,
};
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -606,7 +612,7 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
- struct mmsys_cmdq_cmd *cmd)
+ u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
mutex[mutex->id]);
@@ -618,9 +624,13 @@ void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
mod, mtx->data->mutex_mdp_mod_mask);
+ offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ mod1, mtx->data->mutex_mdp_mod_mask);
+
offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
- 0, mtx->data->mutex_mdp_sof_mask);
+ sof, mtx->data->mutex_mdp_sof_mask);
}
EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 05de7ad4a124..dbb7324c12d9 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -18,7 +18,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
- struct mmsys_cmdq_cmd *cmd);
+ u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
struct mmsys_cmdq_cmd *cmd);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 02/14] soc: mediatek: mutex: expand parameter for mdp mutex function
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Expand parameter for mdp mutex function
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
This patch is base on [1][2]
[1] soc: mediatek: mutex: add functions that operate registers by CMDQ
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220104091712.25670-5-moudy.ho@mediatek.com/
[2] media: platform: mtk-mdp3: add Mediatek MDP3 driver
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220105093758.6850-4-moudy.ho@mediatek.com/
---
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 3 ++-
drivers/soc/mediatek/mtk-mutex.c | 26 +++++++++++++------
include/linux/soc/mediatek/mtk-mutex.h | 2 +-
3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index 4a08502952d6..87751f0e2513 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -101,7 +101,8 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
}
if (subfrm->mutex_mod)
- mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod, cmd);
+ mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
+ 0, 0, cmd);
/* Set SOF */
for (index = 0; index < config->num_components; index++) {
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 89daab7e6863..7da0f44b6f9a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -27,8 +27,9 @@
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
-#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
-#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4)
+#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) ((mutex_sof_reg) + 0x20 * (n))
#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
@@ -180,6 +181,11 @@
#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
+#define MT8183_MDP_PIPE_IMGI MT8183_MUTEX_MDP_START
+#define MT8183_MDP_PIPE_RDMA0 (MT8183_MUTEX_MDP_START + 1)
+#define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
+#define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -364,10 +370,10 @@ static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
/* indicate which mutex is used by each pipepline */
static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
- [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
- [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
- [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
- [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+ [MDP_PIPE_IMGI] = MT8183_MDP_PIPE_IMGI,
+ [MDP_PIPE_RDMA0] = MT8183_MDP_PIPE_RDMA0,
+ [MDP_PIPE_WPEI] = MT8183_MDP_PIPE_WPEI,
+ [MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2,
};
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -606,7 +612,7 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id)
EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
- struct mmsys_cmdq_cmd *cmd)
+ u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
mutex[mutex->id]);
@@ -618,9 +624,13 @@ void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
mod, mtx->data->mutex_mdp_mod_mask);
+ offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
+ mod1, mtx->data->mutex_mdp_mod_mask);
+
offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr + offset,
- 0, mtx->data->mutex_mdp_sof_mask);
+ sof, mtx->data->mutex_mdp_sof_mask);
}
EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 05de7ad4a124..dbb7324c12d9 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -18,7 +18,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
- struct mmsys_cmdq_cmd *cmd);
+ u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
struct mmsys_cmdq_cmd *cmd);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 03/14] soc: mediatek: mmsys: support mt8195 vppsys0/1
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mt8195 vppsys driver data
Add interface for mdp to set config table
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 23 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 22 ++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 3 +++
include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
4 files changed, 52 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index e04cabdfa2dc..460d55e3ef86 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -165,6 +165,18 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 BIT(17)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (BIT(17) | BIT(16))
+/* VPPSYS0 */
+#define VPPSYS0_HW_DCM_1ST_DIS0 0x050
+
+/* VPPSYS1 */
+#define VPPSYS1_HW_DCM_1ST_DIS0 0x150
+#define VPPSYS1_HW_DCM_1ST_DIS1 0x160
+#define VPPSYS1_HW_DCM_2ND_DIS0 0x1a0
+#define VPPSYS1_HW_DCM_2ND_DIS1 0x1b0
+#define VPP0_DL_IRELAY_WR 0x920
+#define SVPP2_BUF_BF_RSZ_SWITCH 0xf48
+#define SVPP3_BUF_BF_RSZ_SWITCH 0xf74
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -217,4 +229,15 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = {
+ VPPSYS0_HW_DCM_1ST_DIS0,
+ VPP0_DL_IRELAY_WR,
+ VPPSYS1_HW_DCM_1ST_DIS0,
+ VPPSYS1_HW_DCM_1ST_DIS1,
+ VPPSYS1_HW_DCM_2ND_DIS0,
+ VPPSYS1_HW_DCM_2ND_DIS1,
+ SVPP2_BUF_BF_RSZ_SWITCH,
+ SVPP3_BUF_BF_RSZ_SWITCH,
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a6ae10946eb6..c7beaa61ad64 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -79,10 +79,16 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
.clk_driver = "clk-mt8195-vpp0",
+ .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+ .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+ .vppsys = true,
};
static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
.clk_driver = "clk-mt8195-vpp1",
+ .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+ .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+ .vppsys = true,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -137,6 +143,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_mdp_write_config(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const u32 *configs = mmsys->data->mdp_mmsys_configs;
+
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
+ mmsys->addr + configs[alias_id], value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_write_config);
+
void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
struct mmsys_cmdq_cmd *cmd,
u32 offset, u32 value, u32 mask)
@@ -367,6 +385,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
if (IS_ERR(clks))
return PTR_ERR(clks);
+ if (mmsys->data->vppsys)
+ goto EXIT;
+
drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(drm)) {
@@ -374,6 +395,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return PTR_ERR(drm);
}
+EXIT:
return 0;
}
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index ad8b92389b54..909713a28c14 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -94,6 +94,9 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
bool has_gce_client_reg;
const unsigned int *mdp_isp_ctrl;
+ const u32 *mdp_mmsys_configs;
+ const unsigned int mdp_num_mmsys_configs;
+ bool vppsys;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index a772e53af9b5..946d161c8937 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -194,4 +194,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
enum mtk_mdp_comp_id id,
u32 camin_w, u32 camin_h);
+void mtk_mmsys_mdp_write_config(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 03/14] soc: mediatek: mmsys: support mt8195 vppsys0/1
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mt8195 vppsys driver data
Add interface for mdp to set config table
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 23 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 22 ++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 3 +++
include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
4 files changed, 52 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index e04cabdfa2dc..460d55e3ef86 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -165,6 +165,18 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 BIT(17)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (BIT(17) | BIT(16))
+/* VPPSYS0 */
+#define VPPSYS0_HW_DCM_1ST_DIS0 0x050
+
+/* VPPSYS1 */
+#define VPPSYS1_HW_DCM_1ST_DIS0 0x150
+#define VPPSYS1_HW_DCM_1ST_DIS1 0x160
+#define VPPSYS1_HW_DCM_2ND_DIS0 0x1a0
+#define VPPSYS1_HW_DCM_2ND_DIS1 0x1b0
+#define VPP0_DL_IRELAY_WR 0x920
+#define SVPP2_BUF_BF_RSZ_SWITCH 0xf48
+#define SVPP3_BUF_BF_RSZ_SWITCH 0xf74
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -217,4 +229,15 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = {
+ VPPSYS0_HW_DCM_1ST_DIS0,
+ VPP0_DL_IRELAY_WR,
+ VPPSYS1_HW_DCM_1ST_DIS0,
+ VPPSYS1_HW_DCM_1ST_DIS1,
+ VPPSYS1_HW_DCM_2ND_DIS0,
+ VPPSYS1_HW_DCM_2ND_DIS1,
+ SVPP2_BUF_BF_RSZ_SWITCH,
+ SVPP3_BUF_BF_RSZ_SWITCH,
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a6ae10946eb6..c7beaa61ad64 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -79,10 +79,16 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
.clk_driver = "clk-mt8195-vpp0",
+ .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+ .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+ .vppsys = true,
};
static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
.clk_driver = "clk-mt8195-vpp1",
+ .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+ .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+ .vppsys = true,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -137,6 +143,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_mdp_write_config(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const u32 *configs = mmsys->data->mdp_mmsys_configs;
+
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
+ mmsys->addr + configs[alias_id], value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_write_config);
+
void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
struct mmsys_cmdq_cmd *cmd,
u32 offset, u32 value, u32 mask)
@@ -367,6 +385,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
if (IS_ERR(clks))
return PTR_ERR(clks);
+ if (mmsys->data->vppsys)
+ goto EXIT;
+
drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(drm)) {
@@ -374,6 +395,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return PTR_ERR(drm);
}
+EXIT:
return 0;
}
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index ad8b92389b54..909713a28c14 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -94,6 +94,9 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
bool has_gce_client_reg;
const unsigned int *mdp_isp_ctrl;
+ const u32 *mdp_mmsys_configs;
+ const unsigned int mdp_num_mmsys_configs;
+ bool vppsys;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index a772e53af9b5..946d161c8937 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -194,4 +194,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
enum mtk_mdp_comp_id id,
u32 camin_w, u32 camin_h);
+void mtk_mmsys_mdp_write_config(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 04/14] soc: mediatek: mutex: support mt8195 vppsys0/1
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mt8195 mdp mutex info to driver data of mtk-mutex
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 53 ++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 7da0f44b6f9a..dd6ef45b582a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -186,6 +186,23 @@
#define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
#define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
+#define MT8195_MUTEX_MDP_MOD_MASK 0xFFFFFFFF
+#define MT8195_MUTEX_MDP_MOD1_MASK 0x000000FF
+#define MT8195_MUTEX_MDP_SOF_MASK 0x00000007
+
+#define MT8195_MDP_PIPE_WPEI 0
+#define MT8195_MDP_PIPE_WPEI2 1
+#define MT8195_MDP_PIPE_RDMA0 2
+#define MT8195_MDP_PIPE_VPP1_SOUT 3
+
+#define MT8195_MDP_PIPE_RDMA1 1
+#define MT8195_MDP_PIPE_RDMA2 2
+#define MT8195_MDP_PIPE_RDMA3 3
+
+#define MT8195_MDP_PIPE_SPLIT 2
+#define MT8195_MDP_PIPE_SPLIT2 3
+#define MT8195_MDP_PIPE_VPP0_SOUT 4
+
struct mtk_mutex {
int id;
bool claimed;
@@ -388,6 +405,22 @@ static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
};
+static const unsigned int mt8195_mutex_vpp0_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_WPEI] = MT8195_MDP_PIPE_WPEI,
+ [MDP_PIPE_WPEI2] = MT8195_MDP_PIPE_WPEI2,
+ [MDP_PIPE_RDMA0] = MT8195_MDP_PIPE_RDMA0,
+ [MDP_PIPE_VPP1_SOUT] = MT8195_MDP_PIPE_VPP1_SOUT,
+};
+
+static const unsigned int mt8195_mutex_vpp1_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_SPLIT] = MT8195_MDP_PIPE_SPLIT,
+ [MDP_PIPE_SPLIT2] = MT8195_MDP_PIPE_SPLIT2,
+ [MDP_PIPE_RDMA1] = MT8195_MDP_PIPE_RDMA1,
+ [MDP_PIPE_RDMA2] = MT8195_MDP_PIPE_RDMA2,
+ [MDP_PIPE_RDMA3] = MT8195_MDP_PIPE_RDMA3,
+ [MDP_PIPE_VPP0_SOUT] = MT8195_MDP_PIPE_SPLIT,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -444,6 +477,22 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = {
.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
};
+static const struct mtk_mutex_data mt8195_vpp0_mutex_driver_data = {
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+ .mutex_mdp_offset = mt8195_mutex_vpp0_offset,
+ .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK,
+};
+
+static const struct mtk_mutex_data mt8195_vpp1_mutex_driver_data = {
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+ .mutex_mdp_offset = mt8195_mutex_vpp1_offset,
+ .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -777,6 +826,10 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8192_mutex_driver_data},
{ .compatible = "mediatek,mt8195-disp-mutex",
.data = &mt8195_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-vpp0-mutex",
+ .data = &mt8195_vpp0_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-vpp1-mutex",
+ .data = &mt8195_vpp1_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 04/14] soc: mediatek: mutex: support mt8195 vppsys0/1
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mt8195 mdp mutex info to driver data of mtk-mutex
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 53 ++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 7da0f44b6f9a..dd6ef45b582a 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -186,6 +186,23 @@
#define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
#define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
+#define MT8195_MUTEX_MDP_MOD_MASK 0xFFFFFFFF
+#define MT8195_MUTEX_MDP_MOD1_MASK 0x000000FF
+#define MT8195_MUTEX_MDP_SOF_MASK 0x00000007
+
+#define MT8195_MDP_PIPE_WPEI 0
+#define MT8195_MDP_PIPE_WPEI2 1
+#define MT8195_MDP_PIPE_RDMA0 2
+#define MT8195_MDP_PIPE_VPP1_SOUT 3
+
+#define MT8195_MDP_PIPE_RDMA1 1
+#define MT8195_MDP_PIPE_RDMA2 2
+#define MT8195_MDP_PIPE_RDMA3 3
+
+#define MT8195_MDP_PIPE_SPLIT 2
+#define MT8195_MDP_PIPE_SPLIT2 3
+#define MT8195_MDP_PIPE_VPP0_SOUT 4
+
struct mtk_mutex {
int id;
bool claimed;
@@ -388,6 +405,22 @@ static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
};
+static const unsigned int mt8195_mutex_vpp0_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_WPEI] = MT8195_MDP_PIPE_WPEI,
+ [MDP_PIPE_WPEI2] = MT8195_MDP_PIPE_WPEI2,
+ [MDP_PIPE_RDMA0] = MT8195_MDP_PIPE_RDMA0,
+ [MDP_PIPE_VPP1_SOUT] = MT8195_MDP_PIPE_VPP1_SOUT,
+};
+
+static const unsigned int mt8195_mutex_vpp1_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_SPLIT] = MT8195_MDP_PIPE_SPLIT,
+ [MDP_PIPE_SPLIT2] = MT8195_MDP_PIPE_SPLIT2,
+ [MDP_PIPE_RDMA1] = MT8195_MDP_PIPE_RDMA1,
+ [MDP_PIPE_RDMA2] = MT8195_MDP_PIPE_RDMA2,
+ [MDP_PIPE_RDMA3] = MT8195_MDP_PIPE_RDMA3,
+ [MDP_PIPE_VPP0_SOUT] = MT8195_MDP_PIPE_SPLIT,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -444,6 +477,22 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = {
.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
};
+static const struct mtk_mutex_data mt8195_vpp0_mutex_driver_data = {
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+ .mutex_mdp_offset = mt8195_mutex_vpp0_offset,
+ .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK,
+};
+
+static const struct mtk_mutex_data mt8195_vpp1_mutex_driver_data = {
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+ .mutex_mdp_offset = mt8195_mutex_vpp1_offset,
+ .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -777,6 +826,10 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8192_mutex_driver_data},
{ .compatible = "mediatek,mt8195-disp-mutex",
.data = &mt8195_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-vpp0-mutex",
+ .data = &mt8195_vpp0_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-vpp1-mutex",
+ .data = &mt8195_vpp1_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 05/14] media: platform: mtk-mdp3: add chip independence architecture
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add chip independence architecture
- Add hal architecture for mt8183
- Add driver data to adapt other soc
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mt8183_mdp.h | 411 ++++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 174 +++++---
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 265 +++++------
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 79 +++-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 33 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 16 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 2 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 233 +---------
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 262 +++++------
9 files changed, 905 insertions(+), 570 deletions(-)
create mode 100644 drivers/media/platform/mtk-mdp3/mt8183_mdp.h
diff --git a/drivers/media/platform/mtk-mdp3/mt8183_mdp.h b/drivers/media/platform/mtk-mdp3/mt8183_mdp.h
new file mode 100644
index 000000000000..9d30d87f5773
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mt8183_mdp.h
@@ -0,0 +1,411 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MT8183_MDP_H__
+#define __MT8183_MDP_H__
+
+static const struct mdp_platform_config mt8183_plat_cfg = {
+ .rdma_support_10bit = true,
+ .rdma_rsz1_sram_sharing = true,
+ .rdma_upsample_repeat_only = true,
+ .rsz_disable_dcm_small_sample = false,
+ .wrot_filter_constraint = false,
+ .gce_event_offset = 2,
+};
+
+enum mt8183_mdp_comp_id {
+ /* MT8183 Comp id */
+ /* ISP */
+ MT8183_MDP_COMP_WPEI = 0,
+ MT8183_MDP_COMP_WPEO, /* 1 */
+ MT8183_MDP_COMP_WPEI2, /* 2 */
+ MT8183_MDP_COMP_WPEO2, /* 3 */
+ MT8183_MDP_COMP_ISP_IMGI, /* 4 */
+ MT8183_MDP_COMP_ISP_IMGO, /* 5 */
+ MT8183_MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MT8183_MDP_COMP_IPUI, /* 7 */
+ MT8183_MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MT8183_MDP_COMP_CAMIN, /* 9 */
+ MT8183_MDP_COMP_CAMIN2, /* 10 */
+ MT8183_MDP_COMP_RDMA0, /* 11 */
+ MT8183_MDP_COMP_AAL0, /* 12 */
+ MT8183_MDP_COMP_CCORR0, /* 13 */
+ MT8183_MDP_COMP_RSZ0, /* 14 */
+ MT8183_MDP_COMP_RSZ1, /* 15 */
+ MT8183_MDP_COMP_TDSHP0, /* 16 */
+ MT8183_MDP_COMP_COLOR0, /* 17 */
+ MT8183_MDP_COMP_PATH0_SOUT, /* 18 */
+ MT8183_MDP_COMP_PATH1_SOUT, /* 19 */
+ MT8183_MDP_COMP_WROT0, /* 20 */
+ MT8183_MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MT8183_MDP_COMP_RDMA1, /* 22 */
+ MT8183_MDP_COMP_RSZ2, /* 23 */
+ MT8183_MDP_COMP_TDSHP1, /* 24 */
+ MT8183_MDP_COMP_WROT1, /* 25 */
+};
+
+static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_WPEI] = {
+ {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEO] = {
+ {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEI2] = {
+ {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEO2] = {
+ {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2},
+ {0, 0, 0},
+ {0, 0, 0},
+ },
+ [MDP_COMP_ISP_IMGI] = {
+ {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI},
+ {0, 0, 4},
+ {0, 0, 0}
+ },
+ [MDP_COMP_ISP_IMGO] = {
+ {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO},
+ {0, 0, 4},
+ {0, 0, 0}
+ },
+ [MDP_COMP_ISP_IMG2O] = {
+ {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN] = {
+ {MDP_COMP_TYPE_DL_PATH1, 0, MT8183_MDP_COMP_CAMIN},
+ {2, 2, 1},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN2] = {
+ {MDP_COMP_TYPE_DL_PATH2, 1, MT8183_MDP_COMP_CAMIN2},
+ {2, 4, 1},
+ {0, 0, 0}
+ },
+ [MDP_COMP_RDMA0] = {
+ {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0},
+ {2, 0, 0},
+ {0, BIT(2), 0},
+ },
+ [MDP_COMP_AAL0] = {
+ {MDP_COMP_TYPE_AAL, 0, MT8183_MDP_COMP_AAL0},
+ {0, 0, 0},
+ {0, BIT(23), 0},
+ },
+ [MDP_COMP_CCORR0] = {
+ {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0},
+ {1, 0, 0},
+ {0, BIT(24), 0}
+ },
+ [MDP_COMP_RSZ0] = {
+ {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0},
+ {1, 0, 0},
+ {0, BIT(4), 0}
+ },
+ [MDP_COMP_RSZ1] = {
+ {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1},
+ {1, 0, 0},
+ {0, BIT(5), 0}
+ },
+ [MDP_COMP_TDSHP0] = {
+ {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0},
+ {0, 0, 0},
+ {0, BIT(6), 0}
+ },
+ [MDP_COMP_PATH0_SOUT] = {
+ {MDP_COMP_TYPE_PATH1, 0, MT8183_MDP_COMP_PATH0_SOUT},
+ {0, 0, 2},
+ {0, 0, 0}
+ },
+ [MDP_COMP_PATH1_SOUT] = {
+ {MDP_COMP_TYPE_PATH2, 1, MT8183_MDP_COMP_PATH1_SOUT},
+ {0, 0, 3},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WROT0] = {
+ {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0},
+ {1, 0, 0},
+ {0, BIT(7), 0}
+ },
+ [MDP_COMP_WDMA] = {
+ {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA},
+ {1, 0, 0},
+ {0, BIT(8), 0}
+ },
+};
+
+static const enum mdp_comp_event mt8183_mdp_event[] = {
+ RDMA0_SOF,
+ RDMA0_DONE,
+ RSZ0_SOF,
+ RSZ1_SOF,
+ TDSHP0_SOF,
+ WROT0_SOF,
+ WROT0_DONE,
+ WDMA0_SOF,
+ WDMA0_DONE,
+ ISP_P2_0_DONE,
+ ISP_P2_1_DONE,
+ ISP_P2_2_DONE,
+ ISP_P2_3_DONE,
+ ISP_P2_4_DONE,
+ ISP_P2_5_DONE,
+ ISP_P2_6_DONE,
+ ISP_P2_7_DONE,
+ ISP_P2_8_DONE,
+ ISP_P2_9_DONE,
+ ISP_P2_10_DONE,
+ ISP_P2_11_DONE,
+ ISP_P2_12_DONE,
+ ISP_P2_13_DONE,
+ ISP_P2_14_DONE,
+ WPE_DONE,
+ WPE_B_DONE
+};
+
+static const struct mdp_pipe_info mt8183_pipe_info[] = {
+ {MDP_PIPE_IMGI, 0, 0},
+ {MDP_PIPE_RDMA0, 0, 1},
+ {MDP_PIPE_WPEI, 0, 2},
+ {MDP_PIPE_WPEI2, 0, 3}
+};
+
+static const struct mdp_format mt8183_formats[] = {
+ {
+ .pixelformat = V4L2_PIX_FMT_GREY,
+ .mdp_color = MDP_COLOR_GREY,
+ .depth = { 8 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565X,
+ .mdp_color = MDP_COLOR_RGB565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565,
+ .mdp_color = MDP_COLOR_BGR565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB24,
+ .mdp_color = MDP_COLOR_RGB888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_BGR24,
+ .mdp_color = MDP_COLOR_BGR888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ABGR32,
+ .mdp_color = MDP_COLOR_BGRA8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ARGB32,
+ .mdp_color = MDP_COLOR_ARGB8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_UYVY,
+ .mdp_color = MDP_COLOR_UYVY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_VYUY,
+ .mdp_color = MDP_COLOR_VYUY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .mdp_color = MDP_COLOR_YUYV,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVYU,
+ .mdp_color = MDP_COLOR_YVYU,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV24,
+ .mdp_color = MDP_COLOR_NV24,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV42,
+ .mdp_color = MDP_COLOR_NV42,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MT21C,
+ .mdp_color = MDP_COLOR_420_BLKP_UFO,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MM21,
+ .mdp_color = MDP_COLOR_420_BLKP,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12M,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21M,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16M,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61M,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420M,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420M,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }
+};
+
+#endif // __MT8183_MDP_H__
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index 87751f0e2513..879a120f78d9 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -42,86 +42,116 @@ static bool is_output_disable(const struct img_compparam *param, u32 count)
true;
}
+static int mdp_get_mutex_idx(const struct mtk_mdp_driver_data *data,
+ enum mtk_mdp_pipe_id pipe_id)
+{
+ int i = 0;
+
+ for (i = 0; i < data->pipe_info_len; i++) {
+ if (pipe_id == data->pipe_info[i].pipe_id)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event)
+{
+ int i = 0;
+
+ for (i = 0; i < mdp->mdp_data->event_len; i++) {
+ if (event == mdp->mdp_data->event[i])
+ return i;
+ }
+
+ return -ENODEV;
+}
+
static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
const struct mdp_path *path,
struct mmsys_cmdq_cmd *cmd, u32 count)
{
const struct img_config *config = path->config;
const struct mdp_comp_ctx *ctx;
+ const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
s32 mutex_id = -1;
- u32 mutex_bit = 0;
- int index, id;
+ u32 mutex_sof = 0;
+ int index, j;
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
/* Default value */
memset(subfrm, 0, sizeof(*subfrm));
- /* Decide which mutex to use based on the current pipeline */
- switch (path->comps[0].comp->id) {
- case MDP_COMP_RDMA0:
- mutex_id = MDP_PIPE_RDMA0;
- break;
- case MDP_COMP_ISP_IMGI:
- mutex_id = MDP_PIPE_IMGI;
- break;
- case MDP_COMP_WPEI:
- mutex_id = MDP_PIPE_WPEI;
- break;
- case MDP_COMP_WPEI2:
- mutex_id = MDP_PIPE_WPEI2;
- break;
- default:
- dev_err(dev, "Unknown pipeline and no mutex is assigned");
- return -EINVAL;
- }
- subfrm->mutex_id = mutex_id;
-
- /* Set mutex mod */
for (index = 0; index < config->num_components; index++) {
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
- id = ctx->comp->id;
- switch (id) {
+
+ public_id = path->comps[index].comp->public_id;
+ switch (public_id) {
case MDP_COMP_AAL0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
case MDP_COMP_CCORR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
case MDP_COMP_WDMA:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA;
+ break;
case MDP_COMP_WROT0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0;
+ break;
case MDP_COMP_TDSHP0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0;
+ break;
case MDP_COMP_RSZ1:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1;
+ break;
case MDP_COMP_RSZ0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ0;
+ break;
case MDP_COMP_RDMA0:
- mutex_bit = mtk_mutex_get_mdp_mod(mutex[mutex_id], id);
- subfrm->mutex_mod |= mutex_bit;
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0;
+ break;
+ case MDP_COMP_ISP_IMGI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI);
+ mutex_id = data->pipe_info[j].mutex_id;
+ break;
+ case MDP_COMP_WPEI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_WPEI2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
default:
break;
}
}
- if (subfrm->mutex_mod)
- mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
- 0, 0, cmd);
+ subfrm->mutex_id = mutex_id;
+ if (-1 == mutex_id) {
+ dev_err(dev, "No mutex assigned");
+ return -EINVAL;
+ }
- /* Set SOF */
- for (index = 0; index < config->num_components; index++) {
- ctx = &path->comps[index];
- if (is_output_disable(ctx->param, count))
- continue;
- id = ctx->comp->id;
- switch (id) {
- case MDP_COMP_WDMA:
- case MDP_COMP_WROT0:
- case MDP_COMP_TDSHP0:
- case MDP_COMP_RSZ1:
- case MDP_COMP_RSZ0:
- case MDP_COMP_RDMA0:
- subfrm->sofs[subfrm->num_sofs++] = id;
- break;
- default:
- break;
- }
+ /* Set mutex modules */
+ if (subfrm->mutex_mod) {
+ mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
+ 0, mutex_sof, cmd);
}
return 0;
@@ -141,33 +171,36 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
}
if (subfrm->mutex_mod) {
- int index;
+ int index, evt;
/* Wait WROT SRAM shared to DISP RDMA */
/* Clear SOF event for each engine */
for (index = 0; index < subfrm->num_sofs; index++) {
switch (subfrm->sofs[index]) {
case MDP_COMP_RDMA0:
- MM_REG_CLEAR(cmd, RDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF);
break;
case MDP_COMP_TDSHP0:
- MM_REG_CLEAR(cmd, TDSHP0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF);
break;
case MDP_COMP_RSZ0:
- MM_REG_CLEAR(cmd, RSZ0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF);
break;
case MDP_COMP_RSZ1:
- MM_REG_CLEAR(cmd, RSZ1_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF);
break;
case MDP_COMP_WDMA:
- MM_REG_CLEAR(cmd, WDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF);
break;
case MDP_COMP_WROT0:
- MM_REG_CLEAR(cmd, WROT0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF);
break;
default:
+ evt = -1;
break;
}
+ if (evt > 0)
+ MM_REG_CLEAR(cmd, evt);
}
/* Enable the mutex */
@@ -177,26 +210,29 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
for (index = 0; index < subfrm->num_sofs; index++) {
switch (subfrm->sofs[index]) {
case MDP_COMP_RDMA0:
- MM_REG_WAIT(cmd, RDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF);
break;
case MDP_COMP_TDSHP0:
- MM_REG_WAIT(cmd, TDSHP0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF);
break;
case MDP_COMP_RSZ0:
- MM_REG_WAIT(cmd, RSZ0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF);
break;
case MDP_COMP_RSZ1:
- MM_REG_WAIT(cmd, RSZ1_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF);
break;
case MDP_COMP_WDMA:
- MM_REG_WAIT(cmd, WDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF);
break;
case MDP_COMP_WROT0:
- MM_REG_WAIT(cmd, WROT0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF);
break;
default:
+ evt = -1;
break;
}
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
}
}
return 0;
@@ -229,6 +265,7 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
const struct img_mmsys_ctrl *ctrl = &config->ctrls[count];
const struct img_mux *set;
struct device *mmsys_dev = path->mdp_dev->mdp_mmsys;
+ const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct mdp_comp_ctx *ctx;
int index, ret;
@@ -331,12 +368,14 @@ static void mdp_auto_release_work(struct work_struct *work)
{
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
+ int i;
cb_param = container_of(work, struct mdp_cmdq_cb_param,
auto_release_work);
mdp = cb_param->mdp;
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -352,6 +391,7 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
struct device *dev;
+ int i;
if (!data.data) {
pr_info("%s:no callback data\n", __func__);
@@ -377,7 +417,8 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
INIT_WORK(&cb_param->auto_release_work, mdp_auto_release_work);
if (!queue_work(mdp->clock_wq, &cb_param->auto_release_work)) {
dev_err(dev, "%s:queue_work fail!\n", __func__);
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -437,7 +478,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
goto err_destroy_pkt;
}
- mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
for (i = 0; i < param->config->num_components; i++)
mdp_comp_clock_on(&mdp->pdev->dev, path->comps[i].comp);
@@ -483,7 +526,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
return 0;
err_clock_off:
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
err_destroy_pkt:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index 622900d2152c..9073ddc19775 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -19,6 +19,36 @@
#include "mdp_reg_wdma.h"
#include "mdp_reg_isp.h"
+s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
+{
+ if (!mdp_dev)
+ return MDP_COMP_NONE;
+ if (id <= MDP_COMP_NONE || id >= MDP_MAX_COMP_COUNT)
+ return MDP_COMP_NONE;
+
+ return mdp_dev->mdp_data->comp_data[id].match.inner_id;
+}
+
+enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
+ u32 i;
+
+ if (IS_ERR(mdp_dev) || !inner_id)
+ goto err_public_id;
+
+ for (i = 0; i < MDP_MAX_COMP_COUNT; i++) {
+ if (mdp_dev->mdp_data->comp_data[i].match.inner_id == inner_id) {
+ public_id = i;
+ return public_id;
+ }
+ }
+
+err_public_id:
+ dev_err(&mdp_dev->pdev->dev, "Unmapped inner id %d", inner_id);
+ return public_id;
+}
+
static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ctx *ctx)
{
if (!ctx)
@@ -30,12 +60,18 @@ static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ct
static s64 get_comp_flag(const struct mdp_comp_ctx *ctx)
{
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ u32 rdma0, rsz1;
+
+ rdma0 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
+ rsz1 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RSZ1);
+ if (!rdma0 || !rsz1)
+ return MDP_COMP_NONE;
if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing)
- if (ctx->comp->id == MDP_COMP_RDMA0)
- return BIT(MDP_COMP_RDMA0) | BIT(MDP_COMP_RSZ1);
+ if (ctx->comp->inner_id == rdma0)
+ return BIT(rdma0) | BIT(rsz1);
- return BIT(ctx->comp->id);
+ return BIT(ctx->comp->inner_id);
}
static int init_rdma(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
@@ -43,12 +79,17 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ s32 rdma0;
- if (mdp_cfg && mdp_cfg->rdma_support_10bit) {
+ rdma0 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
+ if (!rdma0)
+ return -EINVAL;
+
+ if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) {
struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1];
/* Disable RSZ1 */
- if (ctx->comp->id == MDP_COMP_RDMA0 && prz1)
+ if (ctx->comp->inner_id == rdma0 && prz1)
MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE,
0x0, BIT(0));
}
@@ -188,14 +229,18 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx,
static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
+ enum mtk_mdp_comp_id id = ctx->comp->public_id;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt = -1;
- if (ctx->comp->alias_id == 0)
- MM_REG_WAIT(cmd, RDMA0_DONE);
+ if (id == MDP_COMP_RDMA0)
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA0_DONE);
else
dev_err(dev, "Do not support RDMA1_DONE event\n");
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
/* Disable RDMA */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
return 0;
@@ -416,14 +461,19 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
+ enum mtk_mdp_comp_id id = ctx->comp->public_id;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt = -1;
- if (ctx->comp->alias_id == 0)
- MM_REG_WAIT(cmd, WROT0_DONE);
+ if (id == MDP_COMP_WROT0)
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT0_DONE);
else
dev_err(dev, "Do not support WROT1_DONE event\n");
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
+
if (mdp_cfg && mdp_cfg->wrot_filter_constraint)
MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0,
0x77);
@@ -526,8 +576,11 @@ static int wait_wdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt;
- MM_REG_WAIT(cmd, WDMA0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WDMA0_DONE);
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
/* Disable WDMA */
MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0));
return 0;
@@ -592,14 +645,20 @@ static int init_isp(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
struct device *dev = ctx->comp->mdp_dev->mdp_mmsys;
const struct isp_data *isp = &ctx->param->isp;
+ s32 camin, camin2;
+
+ camin = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN);
+ camin2 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN2);
+ if (!camin || !camin2)
+ return -EINVAL;
/* Direct link */
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN)) {
+ if (isp->dl_flags & BIT(camin)) {
dev_dbg(dev, "SW_RST ASYNC");
mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN);
}
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN2)) {
+ if (isp->dl_flags & BIT(camin2)) {
dev_dbg(dev, "SW_RST ASYNC2");
mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN2);
}
@@ -711,69 +770,78 @@ static int wait_isp_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt;
+ s32 camin, camin2;
+
+ camin = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN);
+ camin2 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN2);
+ if (!camin || !camin2)
+ return MDP_COMP_NONE;
/* MDP_DL_SEL: select MDP_CROP */
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN))
+ if (isp->dl_flags & BIT(camin))
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x30, 0x0, BIT(9));
/* MDP2_DL_SEL: select MDP_CROP2 */
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN2))
+ if (isp->dl_flags & BIT(camin2))
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x30, 0x0,
BIT(10) | BIT(11));
switch (isp->cq_idx) {
case ISP_DRV_DIP_CQ_THRE0:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(0), BIT(0));
- MM_REG_WAIT(cmd, ISP_P2_0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_0_DONE);
break;
case ISP_DRV_DIP_CQ_THRE1:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(1), BIT(1));
- MM_REG_WAIT(cmd, ISP_P2_1_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_1_DONE);
break;
case ISP_DRV_DIP_CQ_THRE2:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(2), BIT(2));
- MM_REG_WAIT(cmd, ISP_P2_2_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_2_DONE);
break;
case ISP_DRV_DIP_CQ_THRE3:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(3), BIT(3));
- MM_REG_WAIT(cmd, ISP_P2_3_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_3_DONE);
break;
case ISP_DRV_DIP_CQ_THRE4:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(4), BIT(4));
- MM_REG_WAIT(cmd, ISP_P2_4_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_4_DONE);
break;
case ISP_DRV_DIP_CQ_THRE5:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(5), BIT(5));
- MM_REG_WAIT(cmd, ISP_P2_5_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_5_DONE);
break;
case ISP_DRV_DIP_CQ_THRE6:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(6), BIT(6));
- MM_REG_WAIT(cmd, ISP_P2_6_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_6_DONE);
break;
case ISP_DRV_DIP_CQ_THRE7:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(7), BIT(7));
- MM_REG_WAIT(cmd, ISP_P2_7_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_7_DONE);
break;
case ISP_DRV_DIP_CQ_THRE8:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(8), BIT(8));
- MM_REG_WAIT(cmd, ISP_P2_8_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_8_DONE);
break;
case ISP_DRV_DIP_CQ_THRE9:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(9), BIT(9));
- MM_REG_WAIT(cmd, ISP_P2_9_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_9_DONE);
break;
case ISP_DRV_DIP_CQ_THRE10:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(10), BIT(10));
- MM_REG_WAIT(cmd, ISP_P2_10_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_10_DONE);
break;
case ISP_DRV_DIP_CQ_THRE11:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(11), BIT(11));
- MM_REG_WAIT(cmd, ISP_P2_11_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_11_DONE);
break;
default:
dev_err(dev, "Do not support this cq (%d)", isp->cq_idx);
return -EINVAL;
}
+ MM_REG_WAIT(cmd, evt);
+
return 0;
}
@@ -832,52 +900,25 @@ static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = {
[MDP_COMP_TYPE_DL_PATH2] = &camin_ops,
};
-struct mdp_comp_match {
- enum mtk_mdp_comp_id id;
- enum mdp_comp_type type;
- u32 alias_id;
-};
-
-static const struct mdp_comp_match mdp_comp_matches[MDP_MAX_COMP_COUNT] = {
- [MDP_COMP_WPEI] = { MDP_COMP_WPEI, MDP_COMP_TYPE_WPEI, 0 },
- [MDP_COMP_WPEO] = { MDP_COMP_WPEO, MDP_COMP_TYPE_EXTO, 2 },
- [MDP_COMP_WPEI2] = { MDP_COMP_WPEI2, MDP_COMP_TYPE_WPEI, 1 },
- [MDP_COMP_WPEO2] = { MDP_COMP_WPEO2, MDP_COMP_TYPE_EXTO, 3 },
- [MDP_COMP_ISP_IMGI] = { MDP_COMP_ISP_IMGI, MDP_COMP_TYPE_IMGI, 0 },
- [MDP_COMP_ISP_IMGO] = { MDP_COMP_ISP_IMGO, MDP_COMP_TYPE_EXTO, 0 },
- [MDP_COMP_ISP_IMG2O] = { MDP_COMP_ISP_IMG2O, MDP_COMP_TYPE_EXTO, 1 },
-
- [MDP_COMP_CAMIN] = { MDP_COMP_CAMIN, MDP_COMP_TYPE_DL_PATH1, 0 },
- [MDP_COMP_CAMIN2] = { MDP_COMP_CAMIN2, MDP_COMP_TYPE_DL_PATH2, 1 },
- [MDP_COMP_RDMA0] = { MDP_COMP_RDMA0, MDP_COMP_TYPE_RDMA, 0 },
- [MDP_COMP_CCORR0] = { MDP_COMP_CCORR0, MDP_COMP_TYPE_CCORR, 0 },
- [MDP_COMP_RSZ0] = { MDP_COMP_RSZ0, MDP_COMP_TYPE_RSZ, 0 },
- [MDP_COMP_RSZ1] = { MDP_COMP_RSZ1, MDP_COMP_TYPE_RSZ, 1 },
- [MDP_COMP_PATH0_SOUT] = { MDP_COMP_PATH0_SOUT, MDP_COMP_TYPE_PATH1, 0 },
- [MDP_COMP_PATH1_SOUT] = { MDP_COMP_PATH1_SOUT, MDP_COMP_TYPE_PATH2, 1 },
- [MDP_COMP_WROT0] = { MDP_COMP_WROT0, MDP_COMP_TYPE_WROT, 0 },
- [MDP_COMP_WDMA] = { MDP_COMP_WDMA, MDP_COMP_TYPE_WDMA, 0 },
-};
-
static const struct of_device_id mdp_comp_dt_ids[] = {
{
.compatible = "mediatek,mt8183-mdp3-rdma0",
- .data = &mdp_comp_matches[MDP_COMP_RDMA0],
+ .data = (void *)MDP_COMP_RDMA0,
}, {
.compatible = "mediatek,mt8183-mdp3-ccorr",
- .data = &mdp_comp_matches[MDP_COMP_CCORR0],
+ .data = (void *)MDP_COMP_CCORR0,
}, {
.compatible = "mediatek,mt8183-mdp3-rsz0",
- .data = &mdp_comp_matches[MDP_COMP_RSZ0],
+ .data = (void *)MDP_COMP_RSZ0,
}, {
.compatible = "mediatek,mt8183-mdp3-rsz1",
- .data = &mdp_comp_matches[MDP_COMP_RSZ1],
+ .data = (void *)MDP_COMP_RSZ1,
}, {
.compatible = "mediatek,mt8183-mdp3-wrot0",
- .data = &mdp_comp_matches[MDP_COMP_WROT0],
+ .data = (void *)MDP_COMP_WROT0,
}, {
.compatible = "mediatek,mt8183-mdp3-wdma",
- .data = &mdp_comp_matches[MDP_COMP_WDMA],
+ .data = (void *)MDP_COMP_WDMA,
},
{}
};
@@ -885,47 +926,26 @@ static const struct of_device_id mdp_comp_dt_ids[] = {
static const struct of_device_id mdp_sub_comp_dt_ids[] = {
{
.compatible = "mediatek,mt8183-mdp3-path1",
- .data = &mdp_comp_matches[MDP_COMP_PATH0_SOUT],
+ .data = (void *)MDP_COMP_PATH0_SOUT,
}, {
.compatible = "mediatek,mt8183-mdp3-path2",
- .data = &mdp_comp_matches[MDP_COMP_PATH1_SOUT],
+ .data = (void *)MDP_COMP_PATH1_SOUT,
}, {
.compatible = "mediatek,mt8183-mdp3-imgi",
- .data = &mdp_comp_matches[MDP_COMP_ISP_IMGI],
+ .data = (void *)MDP_COMP_ISP_IMGI,
}, {
.compatible = "mediatek,mt8183-mdp3-exto",
- .data = &mdp_comp_matches[MDP_COMP_ISP_IMGO],
+ .data = (void *)MDP_COMP_ISP_IMGO,
}, {
.compatible = "mediatek,mt8183-mdp3-dl1",
- .data = &mdp_comp_matches[MDP_COMP_CAMIN],
+ .data = (void *)MDP_COMP_CAMIN,
}, {
.compatible = "mediatek,mt8183-mdp3-dl2",
- .data = &mdp_comp_matches[MDP_COMP_CAMIN2],
+ .data = (void *)MDP_COMP_CAMIN2,
},
{}
};
-/* Used to describe the item order in MDP property */
-struct mdp_comp_info {
- u32 clk_num;
- u32 clk_ofst;
- u32 dts_reg_ofst;
-};
-
-static const struct mdp_comp_info mdp_comp_dt_info[MDP_COMP_TYPE_COUNT] = {
- [MDP_COMP_TYPE_RDMA] = {2, 0, 0},
- [MDP_COMP_TYPE_RSZ] = {1, 0, 0},
- [MDP_COMP_TYPE_WROT] = {1, 0, 0},
- [MDP_COMP_TYPE_WDMA] = {1, 0, 0},
- [MDP_COMP_TYPE_PATH1] = {0, 0, 2},
- [MDP_COMP_TYPE_PATH2] = {0, 0, 3},
- [MDP_COMP_TYPE_CCORR] = {1, 0, 0},
- [MDP_COMP_TYPE_IMGI] = {0, 0, 4},
- [MDP_COMP_TYPE_EXTO] = {0, 0, 4},
- [MDP_COMP_TYPE_DL_PATH1] = {2, 2, 1},
- [MDP_COMP_TYPE_DL_PATH2] = {2, 4, 1},
-};
-
void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
{
int i, err;
@@ -935,7 +955,7 @@ void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
if (err < 0)
dev_err(dev,
"Failed to get power, err %d. type:%d id:%d\n",
- err, comp->type, comp->id);
+ err, comp->type, comp->inner_id);
}
for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
@@ -945,7 +965,7 @@ void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
if (err)
dev_err(dev,
"Failed to enable clk %d. type:%d id:%d\n",
- i, comp->type, comp->id);
+ i, comp->type, comp->inner_id);
}
}
@@ -979,7 +999,7 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num)
mdp_comp_clock_off(dev, &comps[i]);
}
-static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
+static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev, struct device_node *node,
struct mdp_comp *comp)
{
struct platform_device *comp_pdev;
@@ -993,12 +1013,12 @@ static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
comp_pdev = of_find_device_by_node(node);
if (!comp_pdev) {
- dev_err(dev, "get comp_pdev fail! comp id=%d type=%d\n",
- comp->id, comp->type);
+ dev_err(dev, "get comp_pdev fail! comp public id=%d, inner id = %d, type=%d\n",
+ comp->public_id, comp->inner_id, comp->type);
return -ENODEV;
}
- index = mdp_comp_dt_info[comp->type].dts_reg_ofst;
+ index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index);
if (ret != 0) {
dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n");
@@ -1016,8 +1036,9 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
{
struct resource res;
phys_addr_t base;
- int index = mdp_comp_dt_info[comp->type].dts_reg_ofst;
+ int index;
+ index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
if (of_address_to_resource(node, index, &res) < 0)
base = 0L;
else
@@ -1041,14 +1062,15 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
return -EINVAL;
}
- comp->type = mdp_comp_matches[id].type;
- comp->id = mdp_comp_matches[id].id;
- comp->alias_id = mdp_comp_matches[id].alias_id;
+ comp->public_id = id;
+ comp->type = mdp->mdp_data->comp_data[id].match.type;
+ comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id;
+ comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id;
comp->ops = mdp_comp_ops[comp->type];
__mdp_comp_init(mdp, node, comp);
- clk_num = mdp_comp_dt_info[comp->type].clk_num;
- clk_ofst = mdp_comp_dt_info[comp->type].clk_ofst;
+ clk_num = mdp->mdp_data->comp_data[id].info.clk_num;
+ clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst;
for (i = 0; i < clk_num; i++) {
comp->clks[i] = of_clk_get(node, i + clk_ofst);
@@ -1056,14 +1078,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
break;
}
- mdp_get_subsys_id(dev, node, comp);
+ mdp_get_subsys_id(mdp, dev, node, comp);
return 0;
}
static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp,
struct device_node *node,
- enum mtk_mdp_comp_id id)
+ enum mtk_mdp_comp_id id)
{
struct device *dev = &mdp->pdev->dev;
struct mdp_comp *comp;
@@ -1084,8 +1106,8 @@ static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp,
mdp->comp[id] = comp;
mdp->comp[id]->mdp_dev = mdp;
- dev_info(dev, "%s type:%d alias:%d id:%d base:%#x regs:%p\n",
- dev->of_node->name, comp->type, comp->alias_id, id,
+ dev_info(dev, "%s type:%d alias:%d public id:%d inner_id:%d base:%#x regs:%p\n",
+ dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id,
(u32)comp->reg_base, comp->regs);
return comp;
}
@@ -1097,21 +1119,22 @@ static int mdp_sub_comps_create(struct mdp_dev *mdp, struct device_node *node)
int index = 0;
of_property_for_each_string(node, "mediatek,mdp3-comps", prop, name) {
- const struct of_device_id *list = mdp_sub_comp_dt_ids;
- struct mdp_comp_match *match = NULL;
+ const struct of_device_id *matches = mdp_sub_comp_dt_ids;
+ enum mtk_mdp_comp_id id = MDP_COMP_NONE;
struct mdp_comp *comp;
- for (; list->compatible[0]; list++) {
- if (of_compat_cmp(name, list->compatible,
- strlen(list->compatible)) == 0) {
- match = (struct mdp_comp_match *)list->data;
+ for (; matches->compatible[0]; matches++) {
+ if (of_compat_cmp(name, matches->compatible,
+ strlen(matches->compatible)) == 0) {
+ id = (enum mtk_mdp_comp_id)matches->data;
break;
}
}
- if (match)
- comp = mdp_comp_create(mdp, node, match->id);
+ if (id == MDP_COMP_NONE)
+ return -ENODEV;
+ comp = mdp_comp_create(mdp, node, id);
if (IS_ERR(comp))
return PTR_ERR(comp);
@@ -1133,8 +1156,8 @@ void mdp_component_deinit(struct mdp_dev *mdp)
{
int i;
- for (i = 0; i < MDP_PIPE_MAX; i++)
- mtk_mutex_put(mdp->mdp_mutex[i]);
+ for (i = 0; i < mdp->mdp_data->pipe_info_len; i++)
+ mtk_mutex_put(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].pipe_id]);
for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) {
if (mdp->comp[i]) {
@@ -1156,7 +1179,7 @@ int mdp_component_init(struct mdp_dev *mdp)
/* Iterate over sibling MDP function blocks */
for_each_child_of_node(parent, node) {
const struct of_device_id *of_id;
- struct mdp_comp_match *match;
+ enum mtk_mdp_comp_id id;
struct mdp_comp *comp;
of_id = of_match_node(mdp_comp_dt_ids, node);
@@ -1168,9 +1191,8 @@ int mdp_component_init(struct mdp_dev *mdp)
continue;
}
- match = (struct mdp_comp_match *)of_id->data;
-
- comp = mdp_comp_create(mdp, node, match->id);
+ id = (enum mtk_mdp_comp_id)of_id->data;
+ comp = mdp_comp_create(mdp, node, id);
if (IS_ERR(comp))
goto err_init_comps;
@@ -1207,16 +1229,15 @@ int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_ipi_frameparam *frame)
{
struct device *dev = &mdp->pdev->dev;
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
int i;
- if (param->type < 0 || param->type >= MDP_MAX_COMP_COUNT) {
- dev_err(dev, "Invalid component id %d", param->type);
+ public_id = get_comp_public_id(mdp, param->type);
+ if (!public_id)
return -EINVAL;
- }
-
- ctx->comp = mdp->comp[param->type];
+ ctx->comp = mdp->comp[public_id];
if (!ctx->comp) {
- dev_err(dev, "Uninit component id %d", param->type);
+ dev_err(dev, "Uninit component inner id %d", param->type);
return -EINVAL;
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
index 7b34f9c42410..57f5ca3052ba 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
@@ -41,24 +41,38 @@
enum mdp_comp_type {
MDP_COMP_TYPE_INVALID = 0,
+ MDP_COMP_TYPE_IMGI,
+ MDP_COMP_TYPE_WPEI,
+
MDP_COMP_TYPE_RDMA,
MDP_COMP_TYPE_RSZ,
MDP_COMP_TYPE_WROT,
MDP_COMP_TYPE_WDMA,
MDP_COMP_TYPE_PATH1,
MDP_COMP_TYPE_PATH2,
+ MDP_COMP_TYPE_SPLIT,
+ MDP_COMP_TYPE_STITCH,
+ MDP_COMP_TYPE_FG,
+ MDP_COMP_TYPE_OVL,
+ MDP_COMP_TYPE_PAD,
+ MDP_COMP_TYPE_MERGE,
MDP_COMP_TYPE_TDSHP,
MDP_COMP_TYPE_COLOR,
MDP_COMP_TYPE_DRE,
MDP_COMP_TYPE_CCORR,
MDP_COMP_TYPE_HDR,
+ MDP_COMP_TYPE_AAL,
+ MDP_COMP_TYPE_TCC,
- MDP_COMP_TYPE_IMGI,
- MDP_COMP_TYPE_WPEI,
MDP_COMP_TYPE_EXTO, /* External path */
MDP_COMP_TYPE_DL_PATH1, /* Direct-link path1 */
MDP_COMP_TYPE_DL_PATH2, /* Direct-link path2 */
+ MDP_COMP_TYPE_DL_PATH3, /* Direct-link path3 */
+ MDP_COMP_TYPE_DL_PATH4, /* Direct-link path4 */
+ MDP_COMP_TYPE_DL_PATH5, /* Direct-link path5 */
+ MDP_COMP_TYPE_DL_PATH6, /* Direct-link path6 */
+ MDP_COMP_TYPE_DUMMY,
MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */
};
@@ -73,6 +87,18 @@ enum mdp_comp_event {
WROT0_DONE,
WDMA0_SOF,
WDMA0_DONE,
+ RDMA1_SOF,
+ RDMA2_SOF,
+ RDMA3_SOF,
+ WROT1_SOF,
+ WROT2_SOF,
+ WROT3_SOF,
+ RDMA1_FRAME_DONE,
+ RDMA2_FRAME_DONE,
+ RDMA3_FRAME_DONE,
+ WROT1_FRAME_DONE,
+ WROT2_FRAME_DONE,
+ WROT3_FRAME_DONE,
ISP_P2_0_DONE,
ISP_P2_1_DONE,
@@ -96,6 +122,43 @@ enum mdp_comp_event {
MDP_MAX_EVENT_COUNT /* ALWAYS keep at the end */
};
+enum mdp_mmsys_config_id {
+ CONFIG_VPP0_HW_DCM_1ST_DIS0,
+ CONFIG_VPP0_DL_IRELAY_WR,
+ CONFIG_VPP1_HW_DCM_1ST_DIS0,
+ CONFIG_VPP1_HW_DCM_1ST_DIS1,
+ CONFIG_VPP1_HW_DCM_2ND_DIS0,
+ CONFIG_VPP1_HW_DCM_2ND_DIS1,
+ CONFIG_SVPP2_BUF_BF_RSZ_SWITCH,
+ CONFIG_SVPP3_BUF_BF_RSZ_SWITCH,
+ MDP_MAX_CONFIG_COUNT
+};
+
+struct mdp_comp_match {
+ enum mdp_comp_type type;
+ u32 alias_id;
+ s32 inner_id;
+};
+
+/* Used to describe the item order in MDP property */
+struct mdp_comp_info {
+ u32 clk_num;
+ u32 clk_ofst;
+ u32 dts_reg_ofst;
+};
+
+struct mdp_mutex_info {
+ u32 mmsys_id;
+ u32 mod;
+ u32 mod2;
+};
+
+struct mdp_comp_data {
+ struct mdp_comp_match match;
+ struct mdp_comp_info info;
+ struct mdp_mutex_info mutex;
+};
+
struct mdp_comp_ops;
struct mdp_comp {
@@ -106,8 +169,9 @@ struct mdp_comp {
struct clk *clks[6];
struct device *comp_dev;
enum mdp_comp_type type;
- enum mtk_mdp_comp_id id;
+ enum mtk_mdp_comp_id public_id;
u32 alias_id;
+ s32 inner_id;
const struct mdp_comp_ops *ops;
};
@@ -134,6 +198,11 @@ struct mdp_comp_ops {
struct mdp_dev;
+s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id);
+enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 id);
+bool is_dummy_engine(struct mdp_dev *mdp_dev, s32 inner_id);
+bool is_rdma(struct mdp_dev *mdp_dev, s32 inner_id);
+
int mdp_component_init(struct mdp_dev *mdp);
void mdp_component_deinit(struct mdp_dev *mdp);
void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp);
@@ -142,6 +211,8 @@ void mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num);
void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num);
int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_compparam *param,
- const struct img_ipi_frameparam *frame);
+ const struct img_ipi_frameparam *frame);
+
+int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event);
#endif /* __MTK_MDP3_COMP_H__ */
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index 535a9b51ee88..a646e99e410f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -14,18 +14,17 @@
#include <media/videobuf2-dma-contig.h>
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
-
-static const struct mdp_platform_config mt8183_plat_cfg = {
- .rdma_support_10bit = true,
- .rdma_rsz1_sram_sharing = true,
- .rdma_upsample_repeat_only = true,
- .rsz_disable_dcm_small_sample = false,
- .wrot_filter_constraint = false,
- .gce_event_offset = 2,
-};
+#include "mt8183_mdp.h"
static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_cfg = &mt8183_plat_cfg,
+ .event = mt8183_mdp_event,
+ .event_len = ARRAY_SIZE(mt8183_mdp_event),
+ .comp_data = mt8183_mdp_comp_data,
+ .pipe_info = mt8183_pipe_info,
+ .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info),
+ .format = mt8183_formats,
+ .format_len = ARRAY_SIZE(mt8183_formats),
};
static const struct of_device_id mdp_of_ids[] = {
@@ -140,7 +139,7 @@ static int mdp_probe(struct platform_device *pdev)
struct device_node *mdp_node;
struct platform_device *mm_pdev;
u32 event_ofst;
- int ret, i;
+ int ret, i, mutex_id;
mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
if (!mdp) {
@@ -164,7 +163,7 @@ static int mdp_probe(struct platform_device *pdev)
}
event_ofst = mdp->mdp_data->mdp_cfg->gce_event_offset;
- for (i = RDMA0_SOF; i < MDP_MAX_EVENT_COUNT; i++) {
+ for (i = 0; i < mdp->mdp_data->event_len; i++) {
s32 event_id;
if (!dev)
@@ -188,9 +187,15 @@ static int mdp_probe(struct platform_device *pdev)
goto err_return;
}
- for (i = 0; i < MDP_PIPE_MAX; i++) {
- mdp->mdp_mutex[i] = mtk_mutex_mdp_get(&mm_pdev->dev, i);
- if (!mdp->mdp_mutex[i]) {
+ for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) {
+ mutex_id = mdp->mdp_data->pipe_info[i].mutex_id;
+ if (mdp->mdp_mutex[mutex_id])
+ continue;
+
+ mdp->mdp_mutex[mutex_id] =
+ mtk_mutex_mdp_get(&mm_pdev->dev, mdp->mdp_data->pipe_info[i].pipe_id);
+
+ if (!mdp->mdp_mutex[mutex_id]) {
ret = -ENODEV;
goto err_return;
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index d688071b0bf1..119af7666b59 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -31,10 +31,19 @@ struct mdp_platform_config {
bool rsz_disable_dcm_small_sample;
bool wrot_filter_constraint;
u32 gce_event_offset;
+ bool support_multi_larb;
};
struct mtk_mdp_driver_data {
const struct mdp_platform_config *mdp_cfg;
+ const enum mdp_comp_event *event;
+ unsigned int event_len;
+ const struct mdp_comp_data *comp_data;
+ const struct mdp_pipe_info *pipe_info;
+ unsigned int pipe_info_len;
+ const struct mdp_format *format;
+ unsigned int format_len;
+ const enum mdp_mmsys_config_id *config_table;
};
struct mdp_dev {
@@ -67,6 +76,13 @@ struct mdp_dev {
atomic_t job_count;
};
+struct mdp_pipe_info {
+ enum mtk_mdp_pipe_id pipe_id;
+ u32 mmsys_id;
+ u32 mutex_id;
+ u32 sof;
+};
+
int mdp_vpu_get_locked(struct mdp_dev *mdp);
void mdp_vpu_put_locked(struct mdp_dev *mdp);
int mdp_vpu_register(struct mdp_dev *mdp);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index 9b3d9a59ae48..ca1c19c41950 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -617,6 +617,8 @@ static int mdp_m2m_open(struct file *file)
int ret;
struct v4l2_format default_format;
+ mdp_format_init(mdp->mdp_data->format, mdp->mdp_data->format_len);
+
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index 439711298867..83e91735202b 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -11,226 +11,8 @@
#include "mtk-mdp3-regs.h"
#include "mtk-mdp3-m2m.h"
-static const struct mdp_format mdp_formats[] = {
- {
- .pixelformat = V4L2_PIX_FMT_GREY,
- .mdp_color = MDP_COLOR_GREY,
- .depth = { 8 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565X,
- .mdp_color = MDP_COLOR_RGB565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565,
- .mdp_color = MDP_COLOR_BGR565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB24,
- .mdp_color = MDP_COLOR_RGB888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_BGR24,
- .mdp_color = MDP_COLOR_BGR888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ABGR32,
- .mdp_color = MDP_COLOR_BGRA8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ARGB32,
- .mdp_color = MDP_COLOR_ARGB8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_UYVY,
- .mdp_color = MDP_COLOR_UYVY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_VYUY,
- .mdp_color = MDP_COLOR_VYUY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUYV,
- .mdp_color = MDP_COLOR_YUYV,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVYU,
- .mdp_color = MDP_COLOR_YVYU,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV24,
- .mdp_color = MDP_COLOR_NV24,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV42,
- .mdp_color = MDP_COLOR_NV42,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MT21C,
- .mdp_color = MDP_COLOR_420_BLK_UFO,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MM21,
- .mdp_color = MDP_COLOR_420_BLK,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12M,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21M,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16M,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61M,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420M,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420M,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }
-};
+static const struct mdp_format *mdp_formats;
+static u32 format_len;
static const struct mdp_limit mdp_def_limit = {
.out_limit = {
@@ -257,7 +39,7 @@ static const struct mdp_format *mdp_find_fmt(u32 pixelformat, u32 type)
flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
+ for (i = 0; i < format_len; ++i) {
if (!(mdp_formats[i].flags & flag))
continue;
if (mdp_formats[i].pixelformat == pixelformat)
@@ -272,7 +54,7 @@ static const struct mdp_format *mdp_find_fmt_by_index(u32 index, u32 type)
flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
+ for (i = 0; i < format_len; ++i) {
if (!(mdp_formats[i].flags & flag))
continue;
if (index == num)
@@ -735,3 +517,10 @@ int mdp_frameparam_init(struct mdp_frameparam *param)
return 0;
}
+
+void mdp_format_init(const struct mdp_format *format, u32 length)
+{
+ mdp_formats = format;
+ format_len = length;
+}
+
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 3ff784aa372b..0fdc1b228227 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -18,14 +18,17 @@
* V-subsample: 0, 1
* Color group: 0-RGB, 1-YUV, 2-raw
*/
-#define MDP_COLOR(PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\
- (((PACKED) << 27) | ((LOOSE) << 26) | ((VIDEO) << 23) |\
+#define MDP_COLOR(COMPRESS, PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\
+ (((COMPRESS) << 29) | ((PACKED) << 28) | ((LOOSE) << 27) | ((VIDEO) << 23) |\
((PLANE) << 21) | ((HF) << 19) | ((VF) << 18) | ((BITS) << 8) |\
((GROUP) << 6) | ((SWAP) << 5) | ((ID) << 0))
-#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x08000000 & (c)) >> 27)
-#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x0c000000 & (c)) >> 26) == 1)
-#define MDP_COLOR_IS_10BIT_TILE(c) (((0x0c000000 & (c)) >> 26) == 3)
+#define MDP_COLOR_IS_HYFBC_COMPRESS(c) ((0x40000000 & (c)) >> 30)
+#define MDP_COLOR_IS_COMPRESS(c) ((0x20000000 & (c)) >> 29)
+#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x10000000 & (c)) >> 28)
+#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x18000000 & (c)) >> 27) == 1)
+#define MDP_COLOR_IS_10BIT_TILE(c) (((0x18000000 & (c)) >> 27) == 3)
+#define MDP_COLOR_IS_10BIT_JUMP(c) ((0x04000000 & (c)) >> 26)
#define MDP_COLOR_IS_UFP(c) ((0x02000000 & (c)) >> 25)
#define MDP_COLOR_IS_INTERLACED(c) ((0x01000000 & (c)) >> 24)
#define MDP_COLOR_IS_BLOCK_MODE(c) ((0x00800000 & (c)) >> 23)
@@ -42,148 +45,120 @@
#define MDP_COLOR_IS_YUV(c) (MDP_COLOR_GET_GROUP(c) == 1)
#define MDP_COLOR_IS_UV_COPLANE(c) ((MDP_COLOR_GET_PLANE_COUNT(c) == 2) &&\
MDP_COLOR_IS_YUV(c))
+#define MDP_COLOR_IS_10BIT(c) (((0x18000000 & (c)) >> 27) != 0)
+#define MDP_COLOR_GET_AUO_MODE(c) (MDP_COLOR_IS_10BIT_JUMP(c))
enum mdp_color {
MDP_COLOR_UNKNOWN = 0,
- //MDP_COLOR_FULLG8,
- MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 21),
- MDP_COLOR_FULLG8 = MDP_COLOR_FULLG8_BGGR,
-
- //MDP_COLOR_FULLG10,
- MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 21),
- MDP_COLOR_FULLG10 = MDP_COLOR_FULLG10_BGGR,
-
- //MDP_COLOR_FULLG12,
- MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 21),
- MDP_COLOR_FULLG12 = MDP_COLOR_FULLG12_BGGR,
-
- //MDP_COLOR_FULLG14,
- MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 21),
- MDP_COLOR_FULLG14 = MDP_COLOR_FULLG14_BGGR,
-
- MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 24),
-
- //MDP_COLOR_BAYER8,
- MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 20),
- MDP_COLOR_BAYER8 = MDP_COLOR_BAYER8_BGGR,
-
- //MDP_COLOR_BAYER10,
- MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 20),
- MDP_COLOR_BAYER10 = MDP_COLOR_BAYER10_BGGR,
-
- //MDP_COLOR_BAYER12,
- MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 20),
- MDP_COLOR_BAYER12 = MDP_COLOR_BAYER12_BGGR,
-
- //MDP_COLOR_BAYER14,
- MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 20),
- MDP_COLOR_BAYER14 = MDP_COLOR_BAYER14_BGGR,
-
- MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 1, 0, 0, 48, 0, 0, 23),
- /* For bayer+mono raw-16 */
- MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 2, 0, 0),
-
- MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 22),
- MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 22),
- MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 22),
- MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 22),
-
- /* Unified formats */
- MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
-
- MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 0, 0),
- MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 1, 0),
- MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 1, 1),
- MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 0, 1),
- MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
- MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
- MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
- MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
-
- MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 4),
- MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 4),
- MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 5),
- MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 5),
-
- MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 0, 8),
- MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 1, 8),
- MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 0, 9),
- MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 1, 9),
- MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 0, 10),
- MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 1, 10),
-
- MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
- MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
- MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 0, 13),
- MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 1, 13),
- MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 0, 14),
- MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 1, 14),
-
- /* Mediatek proprietary formats */
- /* UFO encoded block mode */
- MDP_COLOR_420_BLK_UFO = MDP_COLOR(0, 0, 5, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode */
- MDP_COLOR_420_BLK = MDP_COLOR(0, 0, 1, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode + field mode */
- MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 3, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode */
- MDP_COLOR_422_BLK = MDP_COLOR(0, 0, 1, 1, 1, 0, 512, 1, 0, 4),
-
- MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 25),
- MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 30),
-
- /* Packed 10-bit formats */
- MDP_COLOR_RGBA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
- MDP_COLOR_BGRA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
- /* Packed 10-bit UYVY */
- MDP_COLOR_UYVY_10P = MDP_COLOR(1, 0, 0, 1, 1, 0, 20, 1, 0, 4),
- /* Packed 10-bit NV21 */
- MDP_COLOR_NV21_10P = MDP_COLOR(1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
- /* 10-bit block mode */
- MDP_COLOR_420_BLK_10_H = MDP_COLOR(1, 0, 1, 2, 1, 1, 320, 1, 0, 12),
- /* 10-bit HEVC tile mode */
- MDP_COLOR_420_BLK_10_V = MDP_COLOR(1, 1, 1, 2, 1, 1, 320, 1, 0, 12),
- /* UFO encoded 10-bit block mode */
- MDP_COLOR_420_BLK_U10_H = MDP_COLOR(1, 0, 5, 2, 1, 1, 320, 1, 0, 12),
- /* UFO encoded 10-bit HEVC tile mode */
- MDP_COLOR_420_BLK_U10_V = MDP_COLOR(1, 1, 5, 2, 1, 1, 320, 1, 0, 12),
-
- /* Loose 10-bit formats */
- MDP_COLOR_UYVY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 4),
- MDP_COLOR_VYUY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 4),
- MDP_COLOR_YUYV_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 5),
- MDP_COLOR_YVYU_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 5),
- MDP_COLOR_NV12_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 0, 12),
- MDP_COLOR_NV21_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 1, 12),
- MDP_COLOR_NV16_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 0, 13),
- MDP_COLOR_NV61_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 1, 13),
- MDP_COLOR_YV12_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 1, 8),
- MDP_COLOR_I420_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 0, 8),
+ // Unified format
+ MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
+
+ MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 0, 0),
+ MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 1, 0),
+ MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 1, 1),
+ MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 0, 1),
+ MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+
+ MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 4),
+ MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 4),
+ MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 5),
+ MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 5),
+
+ MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 0, 8),
+ MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 1, 8),
+ MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 0, 9),
+ MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 1, 9),
+ MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 0, 10),
+ MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 1, 10),
+
+ MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
+ MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
+ MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 0, 13),
+ MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 1, 13),
+ MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 0, 14),
+ MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 1, 14),
+
+ // Mediatek proprietary format
+ //Frame mode + Block mode + UFO
+ MDP_COLOR_420_BLKP_UFO = MDP_COLOR(0, 0, 0, 5, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode + Block mode + UFO AUO
+ MDP_COLOR_420_BLKP_UFO_AUO = MDP_COLOR(0, 0, 0, 13, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP = MDP_COLOR(0, 0, 0, 1, 2, 1, 1, 256, 1, 0, 12),
+ //Field mode + Block mode
+ MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 0, 3, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode
+ MDP_COLOR_422_BLKP = MDP_COLOR(0, 0, 0, 1, 1, 1, 0, 512, 1, 0, 4),
+
+ MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 25),
+ MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 30),
+
+ // Mediatek proprietary 10bit format
+ MDP_COLOR_RGBA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+ //Packed 10bit UYVY
+ MDP_COLOR_UYVY_10P = MDP_COLOR(0, 1, 0, 0, 1, 1, 0, 20, 1, 0, 4),
+ //Packed 10bit NV21
+ MDP_COLOR_NV12_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+ MDP_COLOR_NV21_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP_10_H = MDP_COLOR(0, 1, 0, 1, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode
+ MDP_COLOR_420_BLKP_10_V = MDP_COLOR(0, 1, 1, 1, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode + Jump
+ MDP_COLOR_420_BLKP_10_H_JUMP = MDP_COLOR(0, 1, 0, 9, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode + Jump
+ MDP_COLOR_420_BLKP_10_V_JUMP = MDP_COLOR(0, 1, 1, 9, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP_UFO_10_H = MDP_COLOR(0, 1, 0, 5, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode
+ MDP_COLOR_420_BLKP_UFO_10_V = MDP_COLOR(0, 1, 1, 5, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode + Jump
+ MDP_COLOR_420_BLKP_UFO_10_H_JUMP = MDP_COLOR(0, 1, 0, 13, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode + Jump
+ MDP_COLOR_420_BLKP_UFO_10_V_JUMP = MDP_COLOR(0, 1, 1, 13, 2, 1, 1, 320, 1, 0, 12),
+
+ // Loose 10bit format
+ MDP_COLOR_UYVY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 4),
+ MDP_COLOR_VYUY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 4),
+ MDP_COLOR_YUYV_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 5),
+ MDP_COLOR_YVYU_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 5),
+ MDP_COLOR_NV12_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 0, 12),
+ MDP_COLOR_NV21_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 1, 12),
+ MDP_COLOR_NV16_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 0, 13),
+ MDP_COLOR_NV61_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 1, 13),
+ MDP_COLOR_YV12_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 1, 8),
+ MDP_COLOR_I420_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 0, 8),
+
+ MDP_COLOR_YV12_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 1, 10, 1, 1, 8),
+ MDP_COLOR_I422_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 0, 10, 1, 0, 9),
+ MDP_COLOR_NV16_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 0, 13),
+ MDP_COLOR_NV61_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 1, 13),
+
+ MDP_COLOR_I422_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 0, 16, 1, 0, 9),
+
+ MDP_COLOR_RGBA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+ MDP_COLOR_RGBA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+
+ MDP_COLOR_NV12_AFBC = MDP_COLOR(1, 0, 0, 0, 2, 1, 1, 12, 1, 0, 12),
+ MDP_COLOR_P010_AFBC = MDP_COLOR(1, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+
+ MDP_COLOR_NV12_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
+ MDP_COLOR_NV21_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
+ MDP_COLOR_NV12_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+ MDP_COLOR_NV21_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
};
/* Minimum Y stride that is accepted by MDP HW */
@@ -368,5 +343,6 @@ void mdp_set_src_config(struct img_input *in,
void mdp_set_dst_config(struct img_output *out,
struct mdp_frame *frame, struct vb2_buffer *vb);
int mdp_frameparam_init(struct mdp_frameparam *param);
+void mdp_format_init(const struct mdp_format *format, u32 length);
#endif /* __MTK_MDP3_REGS_H__ */
--
2.18.0
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 05/14] media: platform: mtk-mdp3: add chip independence architecture
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add chip independence architecture
- Add hal architecture for mt8183
- Add driver data to adapt other soc
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mt8183_mdp.h | 411 ++++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 174 +++++---
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 265 +++++------
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 79 +++-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 33 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 16 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 2 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 233 +---------
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 262 +++++------
9 files changed, 905 insertions(+), 570 deletions(-)
create mode 100644 drivers/media/platform/mtk-mdp3/mt8183_mdp.h
diff --git a/drivers/media/platform/mtk-mdp3/mt8183_mdp.h b/drivers/media/platform/mtk-mdp3/mt8183_mdp.h
new file mode 100644
index 000000000000..9d30d87f5773
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mt8183_mdp.h
@@ -0,0 +1,411 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MT8183_MDP_H__
+#define __MT8183_MDP_H__
+
+static const struct mdp_platform_config mt8183_plat_cfg = {
+ .rdma_support_10bit = true,
+ .rdma_rsz1_sram_sharing = true,
+ .rdma_upsample_repeat_only = true,
+ .rsz_disable_dcm_small_sample = false,
+ .wrot_filter_constraint = false,
+ .gce_event_offset = 2,
+};
+
+enum mt8183_mdp_comp_id {
+ /* MT8183 Comp id */
+ /* ISP */
+ MT8183_MDP_COMP_WPEI = 0,
+ MT8183_MDP_COMP_WPEO, /* 1 */
+ MT8183_MDP_COMP_WPEI2, /* 2 */
+ MT8183_MDP_COMP_WPEO2, /* 3 */
+ MT8183_MDP_COMP_ISP_IMGI, /* 4 */
+ MT8183_MDP_COMP_ISP_IMGO, /* 5 */
+ MT8183_MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MT8183_MDP_COMP_IPUI, /* 7 */
+ MT8183_MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MT8183_MDP_COMP_CAMIN, /* 9 */
+ MT8183_MDP_COMP_CAMIN2, /* 10 */
+ MT8183_MDP_COMP_RDMA0, /* 11 */
+ MT8183_MDP_COMP_AAL0, /* 12 */
+ MT8183_MDP_COMP_CCORR0, /* 13 */
+ MT8183_MDP_COMP_RSZ0, /* 14 */
+ MT8183_MDP_COMP_RSZ1, /* 15 */
+ MT8183_MDP_COMP_TDSHP0, /* 16 */
+ MT8183_MDP_COMP_COLOR0, /* 17 */
+ MT8183_MDP_COMP_PATH0_SOUT, /* 18 */
+ MT8183_MDP_COMP_PATH1_SOUT, /* 19 */
+ MT8183_MDP_COMP_WROT0, /* 20 */
+ MT8183_MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MT8183_MDP_COMP_RDMA1, /* 22 */
+ MT8183_MDP_COMP_RSZ2, /* 23 */
+ MT8183_MDP_COMP_TDSHP1, /* 24 */
+ MT8183_MDP_COMP_WROT1, /* 25 */
+};
+
+static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_WPEI] = {
+ {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEO] = {
+ {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEI2] = {
+ {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEO2] = {
+ {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2},
+ {0, 0, 0},
+ {0, 0, 0},
+ },
+ [MDP_COMP_ISP_IMGI] = {
+ {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI},
+ {0, 0, 4},
+ {0, 0, 0}
+ },
+ [MDP_COMP_ISP_IMGO] = {
+ {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO},
+ {0, 0, 4},
+ {0, 0, 0}
+ },
+ [MDP_COMP_ISP_IMG2O] = {
+ {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN] = {
+ {MDP_COMP_TYPE_DL_PATH1, 0, MT8183_MDP_COMP_CAMIN},
+ {2, 2, 1},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN2] = {
+ {MDP_COMP_TYPE_DL_PATH2, 1, MT8183_MDP_COMP_CAMIN2},
+ {2, 4, 1},
+ {0, 0, 0}
+ },
+ [MDP_COMP_RDMA0] = {
+ {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0},
+ {2, 0, 0},
+ {0, BIT(2), 0},
+ },
+ [MDP_COMP_AAL0] = {
+ {MDP_COMP_TYPE_AAL, 0, MT8183_MDP_COMP_AAL0},
+ {0, 0, 0},
+ {0, BIT(23), 0},
+ },
+ [MDP_COMP_CCORR0] = {
+ {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0},
+ {1, 0, 0},
+ {0, BIT(24), 0}
+ },
+ [MDP_COMP_RSZ0] = {
+ {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0},
+ {1, 0, 0},
+ {0, BIT(4), 0}
+ },
+ [MDP_COMP_RSZ1] = {
+ {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1},
+ {1, 0, 0},
+ {0, BIT(5), 0}
+ },
+ [MDP_COMP_TDSHP0] = {
+ {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0},
+ {0, 0, 0},
+ {0, BIT(6), 0}
+ },
+ [MDP_COMP_PATH0_SOUT] = {
+ {MDP_COMP_TYPE_PATH1, 0, MT8183_MDP_COMP_PATH0_SOUT},
+ {0, 0, 2},
+ {0, 0, 0}
+ },
+ [MDP_COMP_PATH1_SOUT] = {
+ {MDP_COMP_TYPE_PATH2, 1, MT8183_MDP_COMP_PATH1_SOUT},
+ {0, 0, 3},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WROT0] = {
+ {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0},
+ {1, 0, 0},
+ {0, BIT(7), 0}
+ },
+ [MDP_COMP_WDMA] = {
+ {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA},
+ {1, 0, 0},
+ {0, BIT(8), 0}
+ },
+};
+
+static const enum mdp_comp_event mt8183_mdp_event[] = {
+ RDMA0_SOF,
+ RDMA0_DONE,
+ RSZ0_SOF,
+ RSZ1_SOF,
+ TDSHP0_SOF,
+ WROT0_SOF,
+ WROT0_DONE,
+ WDMA0_SOF,
+ WDMA0_DONE,
+ ISP_P2_0_DONE,
+ ISP_P2_1_DONE,
+ ISP_P2_2_DONE,
+ ISP_P2_3_DONE,
+ ISP_P2_4_DONE,
+ ISP_P2_5_DONE,
+ ISP_P2_6_DONE,
+ ISP_P2_7_DONE,
+ ISP_P2_8_DONE,
+ ISP_P2_9_DONE,
+ ISP_P2_10_DONE,
+ ISP_P2_11_DONE,
+ ISP_P2_12_DONE,
+ ISP_P2_13_DONE,
+ ISP_P2_14_DONE,
+ WPE_DONE,
+ WPE_B_DONE
+};
+
+static const struct mdp_pipe_info mt8183_pipe_info[] = {
+ {MDP_PIPE_IMGI, 0, 0},
+ {MDP_PIPE_RDMA0, 0, 1},
+ {MDP_PIPE_WPEI, 0, 2},
+ {MDP_PIPE_WPEI2, 0, 3}
+};
+
+static const struct mdp_format mt8183_formats[] = {
+ {
+ .pixelformat = V4L2_PIX_FMT_GREY,
+ .mdp_color = MDP_COLOR_GREY,
+ .depth = { 8 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565X,
+ .mdp_color = MDP_COLOR_RGB565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565,
+ .mdp_color = MDP_COLOR_BGR565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB24,
+ .mdp_color = MDP_COLOR_RGB888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_BGR24,
+ .mdp_color = MDP_COLOR_BGR888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ABGR32,
+ .mdp_color = MDP_COLOR_BGRA8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ARGB32,
+ .mdp_color = MDP_COLOR_ARGB8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_UYVY,
+ .mdp_color = MDP_COLOR_UYVY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_VYUY,
+ .mdp_color = MDP_COLOR_VYUY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .mdp_color = MDP_COLOR_YUYV,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVYU,
+ .mdp_color = MDP_COLOR_YVYU,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV24,
+ .mdp_color = MDP_COLOR_NV24,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV42,
+ .mdp_color = MDP_COLOR_NV42,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MT21C,
+ .mdp_color = MDP_COLOR_420_BLKP_UFO,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MM21,
+ .mdp_color = MDP_COLOR_420_BLKP,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12M,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21M,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16M,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61M,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420M,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420M,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }
+};
+
+#endif // __MT8183_MDP_H__
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index 87751f0e2513..879a120f78d9 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -42,86 +42,116 @@ static bool is_output_disable(const struct img_compparam *param, u32 count)
true;
}
+static int mdp_get_mutex_idx(const struct mtk_mdp_driver_data *data,
+ enum mtk_mdp_pipe_id pipe_id)
+{
+ int i = 0;
+
+ for (i = 0; i < data->pipe_info_len; i++) {
+ if (pipe_id == data->pipe_info[i].pipe_id)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event)
+{
+ int i = 0;
+
+ for (i = 0; i < mdp->mdp_data->event_len; i++) {
+ if (event == mdp->mdp_data->event[i])
+ return i;
+ }
+
+ return -ENODEV;
+}
+
static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
const struct mdp_path *path,
struct mmsys_cmdq_cmd *cmd, u32 count)
{
const struct img_config *config = path->config;
const struct mdp_comp_ctx *ctx;
+ const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
s32 mutex_id = -1;
- u32 mutex_bit = 0;
- int index, id;
+ u32 mutex_sof = 0;
+ int index, j;
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
/* Default value */
memset(subfrm, 0, sizeof(*subfrm));
- /* Decide which mutex to use based on the current pipeline */
- switch (path->comps[0].comp->id) {
- case MDP_COMP_RDMA0:
- mutex_id = MDP_PIPE_RDMA0;
- break;
- case MDP_COMP_ISP_IMGI:
- mutex_id = MDP_PIPE_IMGI;
- break;
- case MDP_COMP_WPEI:
- mutex_id = MDP_PIPE_WPEI;
- break;
- case MDP_COMP_WPEI2:
- mutex_id = MDP_PIPE_WPEI2;
- break;
- default:
- dev_err(dev, "Unknown pipeline and no mutex is assigned");
- return -EINVAL;
- }
- subfrm->mutex_id = mutex_id;
-
- /* Set mutex mod */
for (index = 0; index < config->num_components; index++) {
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
- id = ctx->comp->id;
- switch (id) {
+
+ public_id = path->comps[index].comp->public_id;
+ switch (public_id) {
case MDP_COMP_AAL0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
case MDP_COMP_CCORR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
case MDP_COMP_WDMA:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA;
+ break;
case MDP_COMP_WROT0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0;
+ break;
case MDP_COMP_TDSHP0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0;
+ break;
case MDP_COMP_RSZ1:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1;
+ break;
case MDP_COMP_RSZ0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ0;
+ break;
case MDP_COMP_RDMA0:
- mutex_bit = mtk_mutex_get_mdp_mod(mutex[mutex_id], id);
- subfrm->mutex_mod |= mutex_bit;
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0;
+ break;
+ case MDP_COMP_ISP_IMGI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI);
+ mutex_id = data->pipe_info[j].mutex_id;
+ break;
+ case MDP_COMP_WPEI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_WPEI2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
default:
break;
}
}
- if (subfrm->mutex_mod)
- mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
- 0, 0, cmd);
+ subfrm->mutex_id = mutex_id;
+ if (-1 == mutex_id) {
+ dev_err(dev, "No mutex assigned");
+ return -EINVAL;
+ }
- /* Set SOF */
- for (index = 0; index < config->num_components; index++) {
- ctx = &path->comps[index];
- if (is_output_disable(ctx->param, count))
- continue;
- id = ctx->comp->id;
- switch (id) {
- case MDP_COMP_WDMA:
- case MDP_COMP_WROT0:
- case MDP_COMP_TDSHP0:
- case MDP_COMP_RSZ1:
- case MDP_COMP_RSZ0:
- case MDP_COMP_RDMA0:
- subfrm->sofs[subfrm->num_sofs++] = id;
- break;
- default:
- break;
- }
+ /* Set mutex modules */
+ if (subfrm->mutex_mod) {
+ mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
+ 0, mutex_sof, cmd);
}
return 0;
@@ -141,33 +171,36 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
}
if (subfrm->mutex_mod) {
- int index;
+ int index, evt;
/* Wait WROT SRAM shared to DISP RDMA */
/* Clear SOF event for each engine */
for (index = 0; index < subfrm->num_sofs; index++) {
switch (subfrm->sofs[index]) {
case MDP_COMP_RDMA0:
- MM_REG_CLEAR(cmd, RDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF);
break;
case MDP_COMP_TDSHP0:
- MM_REG_CLEAR(cmd, TDSHP0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF);
break;
case MDP_COMP_RSZ0:
- MM_REG_CLEAR(cmd, RSZ0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF);
break;
case MDP_COMP_RSZ1:
- MM_REG_CLEAR(cmd, RSZ1_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF);
break;
case MDP_COMP_WDMA:
- MM_REG_CLEAR(cmd, WDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF);
break;
case MDP_COMP_WROT0:
- MM_REG_CLEAR(cmd, WROT0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF);
break;
default:
+ evt = -1;
break;
}
+ if (evt > 0)
+ MM_REG_CLEAR(cmd, evt);
}
/* Enable the mutex */
@@ -177,26 +210,29 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
for (index = 0; index < subfrm->num_sofs; index++) {
switch (subfrm->sofs[index]) {
case MDP_COMP_RDMA0:
- MM_REG_WAIT(cmd, RDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF);
break;
case MDP_COMP_TDSHP0:
- MM_REG_WAIT(cmd, TDSHP0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF);
break;
case MDP_COMP_RSZ0:
- MM_REG_WAIT(cmd, RSZ0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF);
break;
case MDP_COMP_RSZ1:
- MM_REG_WAIT(cmd, RSZ1_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF);
break;
case MDP_COMP_WDMA:
- MM_REG_WAIT(cmd, WDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF);
break;
case MDP_COMP_WROT0:
- MM_REG_WAIT(cmd, WROT0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF);
break;
default:
+ evt = -1;
break;
}
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
}
}
return 0;
@@ -229,6 +265,7 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
const struct img_mmsys_ctrl *ctrl = &config->ctrls[count];
const struct img_mux *set;
struct device *mmsys_dev = path->mdp_dev->mdp_mmsys;
+ const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct mdp_comp_ctx *ctx;
int index, ret;
@@ -331,12 +368,14 @@ static void mdp_auto_release_work(struct work_struct *work)
{
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
+ int i;
cb_param = container_of(work, struct mdp_cmdq_cb_param,
auto_release_work);
mdp = cb_param->mdp;
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -352,6 +391,7 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
struct device *dev;
+ int i;
if (!data.data) {
pr_info("%s:no callback data\n", __func__);
@@ -377,7 +417,8 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
INIT_WORK(&cb_param->auto_release_work, mdp_auto_release_work);
if (!queue_work(mdp->clock_wq, &cb_param->auto_release_work)) {
dev_err(dev, "%s:queue_work fail!\n", __func__);
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -437,7 +478,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
goto err_destroy_pkt;
}
- mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
for (i = 0; i < param->config->num_components; i++)
mdp_comp_clock_on(&mdp->pdev->dev, path->comps[i].comp);
@@ -483,7 +526,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
return 0;
err_clock_off:
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
err_destroy_pkt:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index 622900d2152c..9073ddc19775 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -19,6 +19,36 @@
#include "mdp_reg_wdma.h"
#include "mdp_reg_isp.h"
+s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
+{
+ if (!mdp_dev)
+ return MDP_COMP_NONE;
+ if (id <= MDP_COMP_NONE || id >= MDP_MAX_COMP_COUNT)
+ return MDP_COMP_NONE;
+
+ return mdp_dev->mdp_data->comp_data[id].match.inner_id;
+}
+
+enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
+ u32 i;
+
+ if (IS_ERR(mdp_dev) || !inner_id)
+ goto err_public_id;
+
+ for (i = 0; i < MDP_MAX_COMP_COUNT; i++) {
+ if (mdp_dev->mdp_data->comp_data[i].match.inner_id == inner_id) {
+ public_id = i;
+ return public_id;
+ }
+ }
+
+err_public_id:
+ dev_err(&mdp_dev->pdev->dev, "Unmapped inner id %d", inner_id);
+ return public_id;
+}
+
static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ctx *ctx)
{
if (!ctx)
@@ -30,12 +60,18 @@ static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ct
static s64 get_comp_flag(const struct mdp_comp_ctx *ctx)
{
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ u32 rdma0, rsz1;
+
+ rdma0 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
+ rsz1 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RSZ1);
+ if (!rdma0 || !rsz1)
+ return MDP_COMP_NONE;
if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing)
- if (ctx->comp->id == MDP_COMP_RDMA0)
- return BIT(MDP_COMP_RDMA0) | BIT(MDP_COMP_RSZ1);
+ if (ctx->comp->inner_id == rdma0)
+ return BIT(rdma0) | BIT(rsz1);
- return BIT(ctx->comp->id);
+ return BIT(ctx->comp->inner_id);
}
static int init_rdma(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
@@ -43,12 +79,17 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ s32 rdma0;
- if (mdp_cfg && mdp_cfg->rdma_support_10bit) {
+ rdma0 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RDMA0);
+ if (!rdma0)
+ return -EINVAL;
+
+ if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) {
struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1];
/* Disable RSZ1 */
- if (ctx->comp->id == MDP_COMP_RDMA0 && prz1)
+ if (ctx->comp->inner_id == rdma0 && prz1)
MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE,
0x0, BIT(0));
}
@@ -188,14 +229,18 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx,
static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
+ enum mtk_mdp_comp_id id = ctx->comp->public_id;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt = -1;
- if (ctx->comp->alias_id == 0)
- MM_REG_WAIT(cmd, RDMA0_DONE);
+ if (id == MDP_COMP_RDMA0)
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA0_DONE);
else
dev_err(dev, "Do not support RDMA1_DONE event\n");
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
/* Disable RDMA */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
return 0;
@@ -416,14 +461,19 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
+ enum mtk_mdp_comp_id id = ctx->comp->public_id;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt = -1;
- if (ctx->comp->alias_id == 0)
- MM_REG_WAIT(cmd, WROT0_DONE);
+ if (id == MDP_COMP_WROT0)
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT0_DONE);
else
dev_err(dev, "Do not support WROT1_DONE event\n");
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
+
if (mdp_cfg && mdp_cfg->wrot_filter_constraint)
MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0,
0x77);
@@ -526,8 +576,11 @@ static int wait_wdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt;
- MM_REG_WAIT(cmd, WDMA0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WDMA0_DONE);
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
/* Disable WDMA */
MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0));
return 0;
@@ -592,14 +645,20 @@ static int init_isp(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
struct device *dev = ctx->comp->mdp_dev->mdp_mmsys;
const struct isp_data *isp = &ctx->param->isp;
+ s32 camin, camin2;
+
+ camin = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN);
+ camin2 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN2);
+ if (!camin || !camin2)
+ return -EINVAL;
/* Direct link */
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN)) {
+ if (isp->dl_flags & BIT(camin)) {
dev_dbg(dev, "SW_RST ASYNC");
mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN);
}
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN2)) {
+ if (isp->dl_flags & BIT(camin2)) {
dev_dbg(dev, "SW_RST ASYNC2");
mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN2);
}
@@ -711,69 +770,78 @@ static int wait_isp_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt;
+ s32 camin, camin2;
+
+ camin = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN);
+ camin2 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_CAMIN2);
+ if (!camin || !camin2)
+ return MDP_COMP_NONE;
/* MDP_DL_SEL: select MDP_CROP */
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN))
+ if (isp->dl_flags & BIT(camin))
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x30, 0x0, BIT(9));
/* MDP2_DL_SEL: select MDP_CROP2 */
- if (isp->dl_flags & BIT(MDP_COMP_CAMIN2))
+ if (isp->dl_flags & BIT(camin2))
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x30, 0x0,
BIT(10) | BIT(11));
switch (isp->cq_idx) {
case ISP_DRV_DIP_CQ_THRE0:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(0), BIT(0));
- MM_REG_WAIT(cmd, ISP_P2_0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_0_DONE);
break;
case ISP_DRV_DIP_CQ_THRE1:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(1), BIT(1));
- MM_REG_WAIT(cmd, ISP_P2_1_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_1_DONE);
break;
case ISP_DRV_DIP_CQ_THRE2:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(2), BIT(2));
- MM_REG_WAIT(cmd, ISP_P2_2_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_2_DONE);
break;
case ISP_DRV_DIP_CQ_THRE3:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(3), BIT(3));
- MM_REG_WAIT(cmd, ISP_P2_3_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_3_DONE);
break;
case ISP_DRV_DIP_CQ_THRE4:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(4), BIT(4));
- MM_REG_WAIT(cmd, ISP_P2_4_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_4_DONE);
break;
case ISP_DRV_DIP_CQ_THRE5:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(5), BIT(5));
- MM_REG_WAIT(cmd, ISP_P2_5_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_5_DONE);
break;
case ISP_DRV_DIP_CQ_THRE6:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(6), BIT(6));
- MM_REG_WAIT(cmd, ISP_P2_6_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_6_DONE);
break;
case ISP_DRV_DIP_CQ_THRE7:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(7), BIT(7));
- MM_REG_WAIT(cmd, ISP_P2_7_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_7_DONE);
break;
case ISP_DRV_DIP_CQ_THRE8:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(8), BIT(8));
- MM_REG_WAIT(cmd, ISP_P2_8_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_8_DONE);
break;
case ISP_DRV_DIP_CQ_THRE9:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(9), BIT(9));
- MM_REG_WAIT(cmd, ISP_P2_9_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_9_DONE);
break;
case ISP_DRV_DIP_CQ_THRE10:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(10), BIT(10));
- MM_REG_WAIT(cmd, ISP_P2_10_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_10_DONE);
break;
case ISP_DRV_DIP_CQ_THRE11:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, BIT(11), BIT(11));
- MM_REG_WAIT(cmd, ISP_P2_11_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_11_DONE);
break;
default:
dev_err(dev, "Do not support this cq (%d)", isp->cq_idx);
return -EINVAL;
}
+ MM_REG_WAIT(cmd, evt);
+
return 0;
}
@@ -832,52 +900,25 @@ static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = {
[MDP_COMP_TYPE_DL_PATH2] = &camin_ops,
};
-struct mdp_comp_match {
- enum mtk_mdp_comp_id id;
- enum mdp_comp_type type;
- u32 alias_id;
-};
-
-static const struct mdp_comp_match mdp_comp_matches[MDP_MAX_COMP_COUNT] = {
- [MDP_COMP_WPEI] = { MDP_COMP_WPEI, MDP_COMP_TYPE_WPEI, 0 },
- [MDP_COMP_WPEO] = { MDP_COMP_WPEO, MDP_COMP_TYPE_EXTO, 2 },
- [MDP_COMP_WPEI2] = { MDP_COMP_WPEI2, MDP_COMP_TYPE_WPEI, 1 },
- [MDP_COMP_WPEO2] = { MDP_COMP_WPEO2, MDP_COMP_TYPE_EXTO, 3 },
- [MDP_COMP_ISP_IMGI] = { MDP_COMP_ISP_IMGI, MDP_COMP_TYPE_IMGI, 0 },
- [MDP_COMP_ISP_IMGO] = { MDP_COMP_ISP_IMGO, MDP_COMP_TYPE_EXTO, 0 },
- [MDP_COMP_ISP_IMG2O] = { MDP_COMP_ISP_IMG2O, MDP_COMP_TYPE_EXTO, 1 },
-
- [MDP_COMP_CAMIN] = { MDP_COMP_CAMIN, MDP_COMP_TYPE_DL_PATH1, 0 },
- [MDP_COMP_CAMIN2] = { MDP_COMP_CAMIN2, MDP_COMP_TYPE_DL_PATH2, 1 },
- [MDP_COMP_RDMA0] = { MDP_COMP_RDMA0, MDP_COMP_TYPE_RDMA, 0 },
- [MDP_COMP_CCORR0] = { MDP_COMP_CCORR0, MDP_COMP_TYPE_CCORR, 0 },
- [MDP_COMP_RSZ0] = { MDP_COMP_RSZ0, MDP_COMP_TYPE_RSZ, 0 },
- [MDP_COMP_RSZ1] = { MDP_COMP_RSZ1, MDP_COMP_TYPE_RSZ, 1 },
- [MDP_COMP_PATH0_SOUT] = { MDP_COMP_PATH0_SOUT, MDP_COMP_TYPE_PATH1, 0 },
- [MDP_COMP_PATH1_SOUT] = { MDP_COMP_PATH1_SOUT, MDP_COMP_TYPE_PATH2, 1 },
- [MDP_COMP_WROT0] = { MDP_COMP_WROT0, MDP_COMP_TYPE_WROT, 0 },
- [MDP_COMP_WDMA] = { MDP_COMP_WDMA, MDP_COMP_TYPE_WDMA, 0 },
-};
-
static const struct of_device_id mdp_comp_dt_ids[] = {
{
.compatible = "mediatek,mt8183-mdp3-rdma0",
- .data = &mdp_comp_matches[MDP_COMP_RDMA0],
+ .data = (void *)MDP_COMP_RDMA0,
}, {
.compatible = "mediatek,mt8183-mdp3-ccorr",
- .data = &mdp_comp_matches[MDP_COMP_CCORR0],
+ .data = (void *)MDP_COMP_CCORR0,
}, {
.compatible = "mediatek,mt8183-mdp3-rsz0",
- .data = &mdp_comp_matches[MDP_COMP_RSZ0],
+ .data = (void *)MDP_COMP_RSZ0,
}, {
.compatible = "mediatek,mt8183-mdp3-rsz1",
- .data = &mdp_comp_matches[MDP_COMP_RSZ1],
+ .data = (void *)MDP_COMP_RSZ1,
}, {
.compatible = "mediatek,mt8183-mdp3-wrot0",
- .data = &mdp_comp_matches[MDP_COMP_WROT0],
+ .data = (void *)MDP_COMP_WROT0,
}, {
.compatible = "mediatek,mt8183-mdp3-wdma",
- .data = &mdp_comp_matches[MDP_COMP_WDMA],
+ .data = (void *)MDP_COMP_WDMA,
},
{}
};
@@ -885,47 +926,26 @@ static const struct of_device_id mdp_comp_dt_ids[] = {
static const struct of_device_id mdp_sub_comp_dt_ids[] = {
{
.compatible = "mediatek,mt8183-mdp3-path1",
- .data = &mdp_comp_matches[MDP_COMP_PATH0_SOUT],
+ .data = (void *)MDP_COMP_PATH0_SOUT,
}, {
.compatible = "mediatek,mt8183-mdp3-path2",
- .data = &mdp_comp_matches[MDP_COMP_PATH1_SOUT],
+ .data = (void *)MDP_COMP_PATH1_SOUT,
}, {
.compatible = "mediatek,mt8183-mdp3-imgi",
- .data = &mdp_comp_matches[MDP_COMP_ISP_IMGI],
+ .data = (void *)MDP_COMP_ISP_IMGI,
}, {
.compatible = "mediatek,mt8183-mdp3-exto",
- .data = &mdp_comp_matches[MDP_COMP_ISP_IMGO],
+ .data = (void *)MDP_COMP_ISP_IMGO,
}, {
.compatible = "mediatek,mt8183-mdp3-dl1",
- .data = &mdp_comp_matches[MDP_COMP_CAMIN],
+ .data = (void *)MDP_COMP_CAMIN,
}, {
.compatible = "mediatek,mt8183-mdp3-dl2",
- .data = &mdp_comp_matches[MDP_COMP_CAMIN2],
+ .data = (void *)MDP_COMP_CAMIN2,
},
{}
};
-/* Used to describe the item order in MDP property */
-struct mdp_comp_info {
- u32 clk_num;
- u32 clk_ofst;
- u32 dts_reg_ofst;
-};
-
-static const struct mdp_comp_info mdp_comp_dt_info[MDP_COMP_TYPE_COUNT] = {
- [MDP_COMP_TYPE_RDMA] = {2, 0, 0},
- [MDP_COMP_TYPE_RSZ] = {1, 0, 0},
- [MDP_COMP_TYPE_WROT] = {1, 0, 0},
- [MDP_COMP_TYPE_WDMA] = {1, 0, 0},
- [MDP_COMP_TYPE_PATH1] = {0, 0, 2},
- [MDP_COMP_TYPE_PATH2] = {0, 0, 3},
- [MDP_COMP_TYPE_CCORR] = {1, 0, 0},
- [MDP_COMP_TYPE_IMGI] = {0, 0, 4},
- [MDP_COMP_TYPE_EXTO] = {0, 0, 4},
- [MDP_COMP_TYPE_DL_PATH1] = {2, 2, 1},
- [MDP_COMP_TYPE_DL_PATH2] = {2, 4, 1},
-};
-
void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
{
int i, err;
@@ -935,7 +955,7 @@ void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
if (err < 0)
dev_err(dev,
"Failed to get power, err %d. type:%d id:%d\n",
- err, comp->type, comp->id);
+ err, comp->type, comp->inner_id);
}
for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
@@ -945,7 +965,7 @@ void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp)
if (err)
dev_err(dev,
"Failed to enable clk %d. type:%d id:%d\n",
- i, comp->type, comp->id);
+ i, comp->type, comp->inner_id);
}
}
@@ -979,7 +999,7 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num)
mdp_comp_clock_off(dev, &comps[i]);
}
-static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
+static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev, struct device_node *node,
struct mdp_comp *comp)
{
struct platform_device *comp_pdev;
@@ -993,12 +1013,12 @@ static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
comp_pdev = of_find_device_by_node(node);
if (!comp_pdev) {
- dev_err(dev, "get comp_pdev fail! comp id=%d type=%d\n",
- comp->id, comp->type);
+ dev_err(dev, "get comp_pdev fail! comp public id=%d, inner id = %d, type=%d\n",
+ comp->public_id, comp->inner_id, comp->type);
return -ENODEV;
}
- index = mdp_comp_dt_info[comp->type].dts_reg_ofst;
+ index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index);
if (ret != 0) {
dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n");
@@ -1016,8 +1036,9 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
{
struct resource res;
phys_addr_t base;
- int index = mdp_comp_dt_info[comp->type].dts_reg_ofst;
+ int index;
+ index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst;
if (of_address_to_resource(node, index, &res) < 0)
base = 0L;
else
@@ -1041,14 +1062,15 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
return -EINVAL;
}
- comp->type = mdp_comp_matches[id].type;
- comp->id = mdp_comp_matches[id].id;
- comp->alias_id = mdp_comp_matches[id].alias_id;
+ comp->public_id = id;
+ comp->type = mdp->mdp_data->comp_data[id].match.type;
+ comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id;
+ comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id;
comp->ops = mdp_comp_ops[comp->type];
__mdp_comp_init(mdp, node, comp);
- clk_num = mdp_comp_dt_info[comp->type].clk_num;
- clk_ofst = mdp_comp_dt_info[comp->type].clk_ofst;
+ clk_num = mdp->mdp_data->comp_data[id].info.clk_num;
+ clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst;
for (i = 0; i < clk_num; i++) {
comp->clks[i] = of_clk_get(node, i + clk_ofst);
@@ -1056,14 +1078,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
break;
}
- mdp_get_subsys_id(dev, node, comp);
+ mdp_get_subsys_id(mdp, dev, node, comp);
return 0;
}
static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp,
struct device_node *node,
- enum mtk_mdp_comp_id id)
+ enum mtk_mdp_comp_id id)
{
struct device *dev = &mdp->pdev->dev;
struct mdp_comp *comp;
@@ -1084,8 +1106,8 @@ static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp,
mdp->comp[id] = comp;
mdp->comp[id]->mdp_dev = mdp;
- dev_info(dev, "%s type:%d alias:%d id:%d base:%#x regs:%p\n",
- dev->of_node->name, comp->type, comp->alias_id, id,
+ dev_info(dev, "%s type:%d alias:%d public id:%d inner_id:%d base:%#x regs:%p\n",
+ dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id,
(u32)comp->reg_base, comp->regs);
return comp;
}
@@ -1097,21 +1119,22 @@ static int mdp_sub_comps_create(struct mdp_dev *mdp, struct device_node *node)
int index = 0;
of_property_for_each_string(node, "mediatek,mdp3-comps", prop, name) {
- const struct of_device_id *list = mdp_sub_comp_dt_ids;
- struct mdp_comp_match *match = NULL;
+ const struct of_device_id *matches = mdp_sub_comp_dt_ids;
+ enum mtk_mdp_comp_id id = MDP_COMP_NONE;
struct mdp_comp *comp;
- for (; list->compatible[0]; list++) {
- if (of_compat_cmp(name, list->compatible,
- strlen(list->compatible)) == 0) {
- match = (struct mdp_comp_match *)list->data;
+ for (; matches->compatible[0]; matches++) {
+ if (of_compat_cmp(name, matches->compatible,
+ strlen(matches->compatible)) == 0) {
+ id = (enum mtk_mdp_comp_id)matches->data;
break;
}
}
- if (match)
- comp = mdp_comp_create(mdp, node, match->id);
+ if (id == MDP_COMP_NONE)
+ return -ENODEV;
+ comp = mdp_comp_create(mdp, node, id);
if (IS_ERR(comp))
return PTR_ERR(comp);
@@ -1133,8 +1156,8 @@ void mdp_component_deinit(struct mdp_dev *mdp)
{
int i;
- for (i = 0; i < MDP_PIPE_MAX; i++)
- mtk_mutex_put(mdp->mdp_mutex[i]);
+ for (i = 0; i < mdp->mdp_data->pipe_info_len; i++)
+ mtk_mutex_put(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].pipe_id]);
for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) {
if (mdp->comp[i]) {
@@ -1156,7 +1179,7 @@ int mdp_component_init(struct mdp_dev *mdp)
/* Iterate over sibling MDP function blocks */
for_each_child_of_node(parent, node) {
const struct of_device_id *of_id;
- struct mdp_comp_match *match;
+ enum mtk_mdp_comp_id id;
struct mdp_comp *comp;
of_id = of_match_node(mdp_comp_dt_ids, node);
@@ -1168,9 +1191,8 @@ int mdp_component_init(struct mdp_dev *mdp)
continue;
}
- match = (struct mdp_comp_match *)of_id->data;
-
- comp = mdp_comp_create(mdp, node, match->id);
+ id = (enum mtk_mdp_comp_id)of_id->data;
+ comp = mdp_comp_create(mdp, node, id);
if (IS_ERR(comp))
goto err_init_comps;
@@ -1207,16 +1229,15 @@ int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_ipi_frameparam *frame)
{
struct device *dev = &mdp->pdev->dev;
+ enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
int i;
- if (param->type < 0 || param->type >= MDP_MAX_COMP_COUNT) {
- dev_err(dev, "Invalid component id %d", param->type);
+ public_id = get_comp_public_id(mdp, param->type);
+ if (!public_id)
return -EINVAL;
- }
-
- ctx->comp = mdp->comp[param->type];
+ ctx->comp = mdp->comp[public_id];
if (!ctx->comp) {
- dev_err(dev, "Uninit component id %d", param->type);
+ dev_err(dev, "Uninit component inner id %d", param->type);
return -EINVAL;
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
index 7b34f9c42410..57f5ca3052ba 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
@@ -41,24 +41,38 @@
enum mdp_comp_type {
MDP_COMP_TYPE_INVALID = 0,
+ MDP_COMP_TYPE_IMGI,
+ MDP_COMP_TYPE_WPEI,
+
MDP_COMP_TYPE_RDMA,
MDP_COMP_TYPE_RSZ,
MDP_COMP_TYPE_WROT,
MDP_COMP_TYPE_WDMA,
MDP_COMP_TYPE_PATH1,
MDP_COMP_TYPE_PATH2,
+ MDP_COMP_TYPE_SPLIT,
+ MDP_COMP_TYPE_STITCH,
+ MDP_COMP_TYPE_FG,
+ MDP_COMP_TYPE_OVL,
+ MDP_COMP_TYPE_PAD,
+ MDP_COMP_TYPE_MERGE,
MDP_COMP_TYPE_TDSHP,
MDP_COMP_TYPE_COLOR,
MDP_COMP_TYPE_DRE,
MDP_COMP_TYPE_CCORR,
MDP_COMP_TYPE_HDR,
+ MDP_COMP_TYPE_AAL,
+ MDP_COMP_TYPE_TCC,
- MDP_COMP_TYPE_IMGI,
- MDP_COMP_TYPE_WPEI,
MDP_COMP_TYPE_EXTO, /* External path */
MDP_COMP_TYPE_DL_PATH1, /* Direct-link path1 */
MDP_COMP_TYPE_DL_PATH2, /* Direct-link path2 */
+ MDP_COMP_TYPE_DL_PATH3, /* Direct-link path3 */
+ MDP_COMP_TYPE_DL_PATH4, /* Direct-link path4 */
+ MDP_COMP_TYPE_DL_PATH5, /* Direct-link path5 */
+ MDP_COMP_TYPE_DL_PATH6, /* Direct-link path6 */
+ MDP_COMP_TYPE_DUMMY,
MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */
};
@@ -73,6 +87,18 @@ enum mdp_comp_event {
WROT0_DONE,
WDMA0_SOF,
WDMA0_DONE,
+ RDMA1_SOF,
+ RDMA2_SOF,
+ RDMA3_SOF,
+ WROT1_SOF,
+ WROT2_SOF,
+ WROT3_SOF,
+ RDMA1_FRAME_DONE,
+ RDMA2_FRAME_DONE,
+ RDMA3_FRAME_DONE,
+ WROT1_FRAME_DONE,
+ WROT2_FRAME_DONE,
+ WROT3_FRAME_DONE,
ISP_P2_0_DONE,
ISP_P2_1_DONE,
@@ -96,6 +122,43 @@ enum mdp_comp_event {
MDP_MAX_EVENT_COUNT /* ALWAYS keep at the end */
};
+enum mdp_mmsys_config_id {
+ CONFIG_VPP0_HW_DCM_1ST_DIS0,
+ CONFIG_VPP0_DL_IRELAY_WR,
+ CONFIG_VPP1_HW_DCM_1ST_DIS0,
+ CONFIG_VPP1_HW_DCM_1ST_DIS1,
+ CONFIG_VPP1_HW_DCM_2ND_DIS0,
+ CONFIG_VPP1_HW_DCM_2ND_DIS1,
+ CONFIG_SVPP2_BUF_BF_RSZ_SWITCH,
+ CONFIG_SVPP3_BUF_BF_RSZ_SWITCH,
+ MDP_MAX_CONFIG_COUNT
+};
+
+struct mdp_comp_match {
+ enum mdp_comp_type type;
+ u32 alias_id;
+ s32 inner_id;
+};
+
+/* Used to describe the item order in MDP property */
+struct mdp_comp_info {
+ u32 clk_num;
+ u32 clk_ofst;
+ u32 dts_reg_ofst;
+};
+
+struct mdp_mutex_info {
+ u32 mmsys_id;
+ u32 mod;
+ u32 mod2;
+};
+
+struct mdp_comp_data {
+ struct mdp_comp_match match;
+ struct mdp_comp_info info;
+ struct mdp_mutex_info mutex;
+};
+
struct mdp_comp_ops;
struct mdp_comp {
@@ -106,8 +169,9 @@ struct mdp_comp {
struct clk *clks[6];
struct device *comp_dev;
enum mdp_comp_type type;
- enum mtk_mdp_comp_id id;
+ enum mtk_mdp_comp_id public_id;
u32 alias_id;
+ s32 inner_id;
const struct mdp_comp_ops *ops;
};
@@ -134,6 +198,11 @@ struct mdp_comp_ops {
struct mdp_dev;
+s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id);
+enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 id);
+bool is_dummy_engine(struct mdp_dev *mdp_dev, s32 inner_id);
+bool is_rdma(struct mdp_dev *mdp_dev, s32 inner_id);
+
int mdp_component_init(struct mdp_dev *mdp);
void mdp_component_deinit(struct mdp_dev *mdp);
void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp);
@@ -142,6 +211,8 @@ void mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num);
void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num);
int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_compparam *param,
- const struct img_ipi_frameparam *frame);
+ const struct img_ipi_frameparam *frame);
+
+int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event);
#endif /* __MTK_MDP3_COMP_H__ */
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index 535a9b51ee88..a646e99e410f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -14,18 +14,17 @@
#include <media/videobuf2-dma-contig.h>
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
-
-static const struct mdp_platform_config mt8183_plat_cfg = {
- .rdma_support_10bit = true,
- .rdma_rsz1_sram_sharing = true,
- .rdma_upsample_repeat_only = true,
- .rsz_disable_dcm_small_sample = false,
- .wrot_filter_constraint = false,
- .gce_event_offset = 2,
-};
+#include "mt8183_mdp.h"
static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_cfg = &mt8183_plat_cfg,
+ .event = mt8183_mdp_event,
+ .event_len = ARRAY_SIZE(mt8183_mdp_event),
+ .comp_data = mt8183_mdp_comp_data,
+ .pipe_info = mt8183_pipe_info,
+ .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info),
+ .format = mt8183_formats,
+ .format_len = ARRAY_SIZE(mt8183_formats),
};
static const struct of_device_id mdp_of_ids[] = {
@@ -140,7 +139,7 @@ static int mdp_probe(struct platform_device *pdev)
struct device_node *mdp_node;
struct platform_device *mm_pdev;
u32 event_ofst;
- int ret, i;
+ int ret, i, mutex_id;
mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
if (!mdp) {
@@ -164,7 +163,7 @@ static int mdp_probe(struct platform_device *pdev)
}
event_ofst = mdp->mdp_data->mdp_cfg->gce_event_offset;
- for (i = RDMA0_SOF; i < MDP_MAX_EVENT_COUNT; i++) {
+ for (i = 0; i < mdp->mdp_data->event_len; i++) {
s32 event_id;
if (!dev)
@@ -188,9 +187,15 @@ static int mdp_probe(struct platform_device *pdev)
goto err_return;
}
- for (i = 0; i < MDP_PIPE_MAX; i++) {
- mdp->mdp_mutex[i] = mtk_mutex_mdp_get(&mm_pdev->dev, i);
- if (!mdp->mdp_mutex[i]) {
+ for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) {
+ mutex_id = mdp->mdp_data->pipe_info[i].mutex_id;
+ if (mdp->mdp_mutex[mutex_id])
+ continue;
+
+ mdp->mdp_mutex[mutex_id] =
+ mtk_mutex_mdp_get(&mm_pdev->dev, mdp->mdp_data->pipe_info[i].pipe_id);
+
+ if (!mdp->mdp_mutex[mutex_id]) {
ret = -ENODEV;
goto err_return;
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index d688071b0bf1..119af7666b59 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -31,10 +31,19 @@ struct mdp_platform_config {
bool rsz_disable_dcm_small_sample;
bool wrot_filter_constraint;
u32 gce_event_offset;
+ bool support_multi_larb;
};
struct mtk_mdp_driver_data {
const struct mdp_platform_config *mdp_cfg;
+ const enum mdp_comp_event *event;
+ unsigned int event_len;
+ const struct mdp_comp_data *comp_data;
+ const struct mdp_pipe_info *pipe_info;
+ unsigned int pipe_info_len;
+ const struct mdp_format *format;
+ unsigned int format_len;
+ const enum mdp_mmsys_config_id *config_table;
};
struct mdp_dev {
@@ -67,6 +76,13 @@ struct mdp_dev {
atomic_t job_count;
};
+struct mdp_pipe_info {
+ enum mtk_mdp_pipe_id pipe_id;
+ u32 mmsys_id;
+ u32 mutex_id;
+ u32 sof;
+};
+
int mdp_vpu_get_locked(struct mdp_dev *mdp);
void mdp_vpu_put_locked(struct mdp_dev *mdp);
int mdp_vpu_register(struct mdp_dev *mdp);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index 9b3d9a59ae48..ca1c19c41950 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -617,6 +617,8 @@ static int mdp_m2m_open(struct file *file)
int ret;
struct v4l2_format default_format;
+ mdp_format_init(mdp->mdp_data->format, mdp->mdp_data->format_len);
+
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index 439711298867..83e91735202b 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -11,226 +11,8 @@
#include "mtk-mdp3-regs.h"
#include "mtk-mdp3-m2m.h"
-static const struct mdp_format mdp_formats[] = {
- {
- .pixelformat = V4L2_PIX_FMT_GREY,
- .mdp_color = MDP_COLOR_GREY,
- .depth = { 8 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565X,
- .mdp_color = MDP_COLOR_RGB565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565,
- .mdp_color = MDP_COLOR_BGR565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB24,
- .mdp_color = MDP_COLOR_RGB888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_BGR24,
- .mdp_color = MDP_COLOR_BGR888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ABGR32,
- .mdp_color = MDP_COLOR_BGRA8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ARGB32,
- .mdp_color = MDP_COLOR_ARGB8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_UYVY,
- .mdp_color = MDP_COLOR_UYVY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_VYUY,
- .mdp_color = MDP_COLOR_VYUY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUYV,
- .mdp_color = MDP_COLOR_YUYV,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVYU,
- .mdp_color = MDP_COLOR_YVYU,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV24,
- .mdp_color = MDP_COLOR_NV24,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV42,
- .mdp_color = MDP_COLOR_NV42,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MT21C,
- .mdp_color = MDP_COLOR_420_BLK_UFO,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MM21,
- .mdp_color = MDP_COLOR_420_BLK,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12M,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21M,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16M,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61M,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420M,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420M,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }
-};
+static const struct mdp_format *mdp_formats;
+static u32 format_len;
static const struct mdp_limit mdp_def_limit = {
.out_limit = {
@@ -257,7 +39,7 @@ static const struct mdp_format *mdp_find_fmt(u32 pixelformat, u32 type)
flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
+ for (i = 0; i < format_len; ++i) {
if (!(mdp_formats[i].flags & flag))
continue;
if (mdp_formats[i].pixelformat == pixelformat)
@@ -272,7 +54,7 @@ static const struct mdp_format *mdp_find_fmt_by_index(u32 index, u32 type)
flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
+ for (i = 0; i < format_len; ++i) {
if (!(mdp_formats[i].flags & flag))
continue;
if (index == num)
@@ -735,3 +517,10 @@ int mdp_frameparam_init(struct mdp_frameparam *param)
return 0;
}
+
+void mdp_format_init(const struct mdp_format *format, u32 length)
+{
+ mdp_formats = format;
+ format_len = length;
+}
+
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 3ff784aa372b..0fdc1b228227 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -18,14 +18,17 @@
* V-subsample: 0, 1
* Color group: 0-RGB, 1-YUV, 2-raw
*/
-#define MDP_COLOR(PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\
- (((PACKED) << 27) | ((LOOSE) << 26) | ((VIDEO) << 23) |\
+#define MDP_COLOR(COMPRESS, PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\
+ (((COMPRESS) << 29) | ((PACKED) << 28) | ((LOOSE) << 27) | ((VIDEO) << 23) |\
((PLANE) << 21) | ((HF) << 19) | ((VF) << 18) | ((BITS) << 8) |\
((GROUP) << 6) | ((SWAP) << 5) | ((ID) << 0))
-#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x08000000 & (c)) >> 27)
-#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x0c000000 & (c)) >> 26) == 1)
-#define MDP_COLOR_IS_10BIT_TILE(c) (((0x0c000000 & (c)) >> 26) == 3)
+#define MDP_COLOR_IS_HYFBC_COMPRESS(c) ((0x40000000 & (c)) >> 30)
+#define MDP_COLOR_IS_COMPRESS(c) ((0x20000000 & (c)) >> 29)
+#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x10000000 & (c)) >> 28)
+#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x18000000 & (c)) >> 27) == 1)
+#define MDP_COLOR_IS_10BIT_TILE(c) (((0x18000000 & (c)) >> 27) == 3)
+#define MDP_COLOR_IS_10BIT_JUMP(c) ((0x04000000 & (c)) >> 26)
#define MDP_COLOR_IS_UFP(c) ((0x02000000 & (c)) >> 25)
#define MDP_COLOR_IS_INTERLACED(c) ((0x01000000 & (c)) >> 24)
#define MDP_COLOR_IS_BLOCK_MODE(c) ((0x00800000 & (c)) >> 23)
@@ -42,148 +45,120 @@
#define MDP_COLOR_IS_YUV(c) (MDP_COLOR_GET_GROUP(c) == 1)
#define MDP_COLOR_IS_UV_COPLANE(c) ((MDP_COLOR_GET_PLANE_COUNT(c) == 2) &&\
MDP_COLOR_IS_YUV(c))
+#define MDP_COLOR_IS_10BIT(c) (((0x18000000 & (c)) >> 27) != 0)
+#define MDP_COLOR_GET_AUO_MODE(c) (MDP_COLOR_IS_10BIT_JUMP(c))
enum mdp_color {
MDP_COLOR_UNKNOWN = 0,
- //MDP_COLOR_FULLG8,
- MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 21),
- MDP_COLOR_FULLG8 = MDP_COLOR_FULLG8_BGGR,
-
- //MDP_COLOR_FULLG10,
- MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 21),
- MDP_COLOR_FULLG10 = MDP_COLOR_FULLG10_BGGR,
-
- //MDP_COLOR_FULLG12,
- MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 21),
- MDP_COLOR_FULLG12 = MDP_COLOR_FULLG12_BGGR,
-
- //MDP_COLOR_FULLG14,
- MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 21),
- MDP_COLOR_FULLG14 = MDP_COLOR_FULLG14_BGGR,
-
- MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 24),
-
- //MDP_COLOR_BAYER8,
- MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 20),
- MDP_COLOR_BAYER8 = MDP_COLOR_BAYER8_BGGR,
-
- //MDP_COLOR_BAYER10,
- MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 20),
- MDP_COLOR_BAYER10 = MDP_COLOR_BAYER10_BGGR,
-
- //MDP_COLOR_BAYER12,
- MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 20),
- MDP_COLOR_BAYER12 = MDP_COLOR_BAYER12_BGGR,
-
- //MDP_COLOR_BAYER14,
- MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 20),
- MDP_COLOR_BAYER14 = MDP_COLOR_BAYER14_BGGR,
-
- MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 1, 0, 0, 48, 0, 0, 23),
- /* For bayer+mono raw-16 */
- MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 2, 0, 0),
-
- MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 22),
- MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 22),
- MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 22),
- MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 22),
-
- /* Unified formats */
- MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
-
- MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 0, 0),
- MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 1, 0),
- MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 1, 1),
- MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 0, 1),
- MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
- MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
- MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
- MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
-
- MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 4),
- MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 4),
- MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 5),
- MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 5),
-
- MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 0, 8),
- MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 1, 8),
- MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 0, 9),
- MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 1, 9),
- MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 0, 10),
- MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 1, 10),
-
- MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
- MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
- MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 0, 13),
- MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 1, 13),
- MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 0, 14),
- MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 1, 14),
-
- /* Mediatek proprietary formats */
- /* UFO encoded block mode */
- MDP_COLOR_420_BLK_UFO = MDP_COLOR(0, 0, 5, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode */
- MDP_COLOR_420_BLK = MDP_COLOR(0, 0, 1, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode + field mode */
- MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 3, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode */
- MDP_COLOR_422_BLK = MDP_COLOR(0, 0, 1, 1, 1, 0, 512, 1, 0, 4),
-
- MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 25),
- MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 30),
-
- /* Packed 10-bit formats */
- MDP_COLOR_RGBA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
- MDP_COLOR_BGRA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
- /* Packed 10-bit UYVY */
- MDP_COLOR_UYVY_10P = MDP_COLOR(1, 0, 0, 1, 1, 0, 20, 1, 0, 4),
- /* Packed 10-bit NV21 */
- MDP_COLOR_NV21_10P = MDP_COLOR(1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
- /* 10-bit block mode */
- MDP_COLOR_420_BLK_10_H = MDP_COLOR(1, 0, 1, 2, 1, 1, 320, 1, 0, 12),
- /* 10-bit HEVC tile mode */
- MDP_COLOR_420_BLK_10_V = MDP_COLOR(1, 1, 1, 2, 1, 1, 320, 1, 0, 12),
- /* UFO encoded 10-bit block mode */
- MDP_COLOR_420_BLK_U10_H = MDP_COLOR(1, 0, 5, 2, 1, 1, 320, 1, 0, 12),
- /* UFO encoded 10-bit HEVC tile mode */
- MDP_COLOR_420_BLK_U10_V = MDP_COLOR(1, 1, 5, 2, 1, 1, 320, 1, 0, 12),
-
- /* Loose 10-bit formats */
- MDP_COLOR_UYVY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 4),
- MDP_COLOR_VYUY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 4),
- MDP_COLOR_YUYV_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 5),
- MDP_COLOR_YVYU_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 5),
- MDP_COLOR_NV12_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 0, 12),
- MDP_COLOR_NV21_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 1, 12),
- MDP_COLOR_NV16_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 0, 13),
- MDP_COLOR_NV61_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 1, 13),
- MDP_COLOR_YV12_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 1, 8),
- MDP_COLOR_I420_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 0, 8),
+ // Unified format
+ MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
+
+ MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 0, 0),
+ MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 1, 0),
+ MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 1, 1),
+ MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 0, 1),
+ MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+
+ MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 4),
+ MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 4),
+ MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 5),
+ MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 5),
+
+ MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 0, 8),
+ MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 1, 8),
+ MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 0, 9),
+ MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 1, 9),
+ MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 0, 10),
+ MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 1, 10),
+
+ MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
+ MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
+ MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 0, 13),
+ MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 1, 13),
+ MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 0, 14),
+ MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 1, 14),
+
+ // Mediatek proprietary format
+ //Frame mode + Block mode + UFO
+ MDP_COLOR_420_BLKP_UFO = MDP_COLOR(0, 0, 0, 5, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode + Block mode + UFO AUO
+ MDP_COLOR_420_BLKP_UFO_AUO = MDP_COLOR(0, 0, 0, 13, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP = MDP_COLOR(0, 0, 0, 1, 2, 1, 1, 256, 1, 0, 12),
+ //Field mode + Block mode
+ MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 0, 3, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode
+ MDP_COLOR_422_BLKP = MDP_COLOR(0, 0, 0, 1, 1, 1, 0, 512, 1, 0, 4),
+
+ MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 25),
+ MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 30),
+
+ // Mediatek proprietary 10bit format
+ MDP_COLOR_RGBA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+ //Packed 10bit UYVY
+ MDP_COLOR_UYVY_10P = MDP_COLOR(0, 1, 0, 0, 1, 1, 0, 20, 1, 0, 4),
+ //Packed 10bit NV21
+ MDP_COLOR_NV12_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+ MDP_COLOR_NV21_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP_10_H = MDP_COLOR(0, 1, 0, 1, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode
+ MDP_COLOR_420_BLKP_10_V = MDP_COLOR(0, 1, 1, 1, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode + Jump
+ MDP_COLOR_420_BLKP_10_H_JUMP = MDP_COLOR(0, 1, 0, 9, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode + Jump
+ MDP_COLOR_420_BLKP_10_V_JUMP = MDP_COLOR(0, 1, 1, 9, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP_UFO_10_H = MDP_COLOR(0, 1, 0, 5, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode
+ MDP_COLOR_420_BLKP_UFO_10_V = MDP_COLOR(0, 1, 1, 5, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode + Jump
+ MDP_COLOR_420_BLKP_UFO_10_H_JUMP = MDP_COLOR(0, 1, 0, 13, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode + Jump
+ MDP_COLOR_420_BLKP_UFO_10_V_JUMP = MDP_COLOR(0, 1, 1, 13, 2, 1, 1, 320, 1, 0, 12),
+
+ // Loose 10bit format
+ MDP_COLOR_UYVY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 4),
+ MDP_COLOR_VYUY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 4),
+ MDP_COLOR_YUYV_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 5),
+ MDP_COLOR_YVYU_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 5),
+ MDP_COLOR_NV12_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 0, 12),
+ MDP_COLOR_NV21_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 1, 12),
+ MDP_COLOR_NV16_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 0, 13),
+ MDP_COLOR_NV61_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 1, 13),
+ MDP_COLOR_YV12_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 1, 8),
+ MDP_COLOR_I420_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 0, 8),
+
+ MDP_COLOR_YV12_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 1, 10, 1, 1, 8),
+ MDP_COLOR_I422_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 0, 10, 1, 0, 9),
+ MDP_COLOR_NV16_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 0, 13),
+ MDP_COLOR_NV61_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 1, 13),
+
+ MDP_COLOR_I422_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 0, 16, 1, 0, 9),
+
+ MDP_COLOR_RGBA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+ MDP_COLOR_RGBA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+
+ MDP_COLOR_NV12_AFBC = MDP_COLOR(1, 0, 0, 0, 2, 1, 1, 12, 1, 0, 12),
+ MDP_COLOR_P010_AFBC = MDP_COLOR(1, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+
+ MDP_COLOR_NV12_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
+ MDP_COLOR_NV21_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
+ MDP_COLOR_NV12_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+ MDP_COLOR_NV21_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
};
/* Minimum Y stride that is accepted by MDP HW */
@@ -368,5 +343,6 @@ void mdp_set_src_config(struct img_input *in,
void mdp_set_dst_config(struct img_output *out,
struct mdp_frame *frame, struct vb2_buffer *vb);
int mdp_frameparam_init(struct mdp_frameparam *param);
+void mdp_format_init(const struct mdp_format *format, u32 length);
#endif /* __MTK_MDP3_REGS_H__ */
--
2.18.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 06/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
1. Modify struct member to 4 byte-alignment for MT8195 SCP limitation
2. Add new struct for hw engine adding in MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 219 +++++++++++++++---
1 file changed, 181 insertions(+), 38 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h b/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
index f8560dad87da..8dd0bcdee431 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
@@ -42,14 +42,14 @@ struct img_sw_addr {
struct img_plane_format {
u32 size;
- u16 stride;
+ u32 stride;
} __packed;
struct img_pix_format {
- u16 width;
- u16 height;
+ u32 width;
+ u32 height;
u32 colorformat; /* enum mdp_color */
- u16 ycbcr_prof; /* enum mdp_ycbcr_profile */
+ u32 ycbcr_prof; /* enum mdp_ycbcr_profile */
struct img_plane_format plane_fmt[IMG_MAX_PLANES];
} __packed;
@@ -63,10 +63,10 @@ struct img_image_buffer {
#define IMG_SUBPIXEL_SHIFT 20
struct img_crop {
- s16 left;
- s16 top;
- u16 width;
- u16 height;
+ s32 left;
+ s32 top;
+ u32 width;
+ u32 height;
u32 left_subpix;
u32 top_subpix;
u32 width_subpix;
@@ -78,27 +78,29 @@ struct img_crop {
#define IMG_CTRL_FLAG_SHARPNESS BIT(4)
#define IMG_CTRL_FLAG_HDR BIT(5)
#define IMG_CTRL_FLAG_DRE BIT(6)
+#define IMG_CTRL_FLAG_RSZ BIT(7)
struct img_input {
struct img_image_buffer buffer;
- u16 flags; /* HDR, DRE, dither */
+ u32 flags; /* HDR, DRE, dither */
} __packed;
struct img_output {
struct img_image_buffer buffer;
struct img_crop crop;
- s16 rotation;
- u16 flags; /* H-flip, sharpness, dither */
+ s32 rotation;
+ u32 flags; /* H-flip, sharpness, dither */
+ u64 pqid;
} __packed;
struct img_ipi_frameparam {
u32 index;
u32 frame_no;
u64 timestamp;
- u8 type; /* enum mdp_stream_type */
- u8 state;
- u8 num_inputs;
- u8 num_outputs;
+ u32 type; /* enum mdp_stream_type */
+ u32 state;
+ u32 num_inputs;
+ u32 num_outputs;
u64 drv_data;
struct img_input inputs[IMG_MAX_HW_INPUTS];
struct img_output outputs[IMG_MAX_HW_OUTPUTS];
@@ -106,6 +108,7 @@ struct img_ipi_frameparam {
struct img_addr subfrm_data;
struct img_sw_addr config_data;
struct img_sw_addr self_data;
+ u32 frame_change;
} __packed;
struct img_sw_buffer {
@@ -114,51 +117,51 @@ struct img_sw_buffer {
} __packed;
struct img_ipi_param {
- u8 usage;
+ u32 usage;
struct img_sw_buffer frm_param;
} __packed;
struct img_frameparam {
struct list_head list_entry;
struct img_ipi_frameparam frameparam;
-};
+} __packed;
/* ISP-MDP generic output information */
struct img_comp_frame {
- u32 output_disable:1;
- u32 bypass:1;
- u16 in_width;
- u16 in_height;
- u16 out_width;
- u16 out_height;
+ u32 output_disable;
+ u32 bypass;
+ u32 in_width;
+ u32 in_height;
+ u32 out_width;
+ u32 out_height;
struct img_crop crop;
- u16 in_total_width;
- u16 out_total_width;
+ u32 in_total_width;
+ u32 out_total_width;
} __packed;
struct img_region {
- s16 left;
- s16 right;
- s16 top;
- s16 bottom;
+ s32 left;
+ s32 right;
+ s32 top;
+ s32 bottom;
} __packed;
struct img_offset {
- s16 left;
- s16 top;
+ s32 left;
+ s32 top;
u32 left_subpix;
u32 top_subpix;
} __packed;
struct img_comp_subfrm {
- u32 tile_disable:1;
+ u32 tile_disable;
struct img_region in;
struct img_region out;
struct img_offset luma;
struct img_offset chroma;
- s16 out_vertical; /* Output vertical index */
- s16 out_horizontal; /* Output horizontal index */
+ s32 out_vertical; /* Output vertical index */
+ s32 out_horizontal; /* Output horizontal index */
} __packed;
#define IMG_MAX_SUBFRAMES 14
@@ -169,10 +172,13 @@ struct mdp_rdma_subfrm {
u32 src;
u32 clip;
u32 clip_ofst;
+ u32 in_tile_xleft;
+ u32 in_tile_ytop;
} __packed;
struct mdp_rdma_data {
u32 src_ctrl;
+ u32 comp_ctrl;
u32 control;
u32 iova[IMG_MAX_PLANES];
u32 iova_end[IMG_MAX_PLANES];
@@ -182,13 +188,72 @@ struct mdp_rdma_data {
u32 ufo_dec_y;
u32 ufo_dec_c;
u32 transform;
+ u32 dmabuf_con0;
+ u32 ultra_th_high_con0;
+ u32 ultra_th_low_con0;
+ u32 dmabuf_con1;
+ u32 ultra_th_high_con1;
+ u32 ultra_th_low_con1;
+ u32 dmabuf_con2;
+ u32 ultra_th_high_con2;
+ u32 ultra_th_low_con2;
+ u32 dmabuf_con3;
struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES];
} __packed;
+struct mdp_fg_subfrm {
+ u32 info_0;
+ u32 info_1;
+} __packed;
+
+struct mdp_fg_data {
+ u32 ctrl_0;
+ u32 ck_en;
+ struct mdp_fg_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_hdr_subfrm {
+ u32 win_size;
+ u32 src;
+ u32 clip_ofst0;
+ u32 clip_ofst1;
+ u32 hist_ctrl_0;
+ u32 hist_ctrl_1;
+ u32 hdr_top;
+ u32 hist_addr;
+} __packed;
+
+struct mdp_hdr_data {
+ u32 top;
+ u32 relay;
+ struct mdp_hdr_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_aal_subfrm {
+ u32 src;
+ u32 clip;
+ u32 clip_ofst;
+} __packed;
+
+struct mdp_aal_data {
+ u32 cfg_main;
+ u32 cfg;
+ struct mdp_aal_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
struct mdp_rsz_subfrm {
u32 control2;
u32 src;
u32 clip;
+ u32 hdmirx_en;
+ u32 luma_h_int_ofst;
+ u32 luma_h_sub_ofst;
+ u32 luma_v_int_ofst;
+ u32 luma_v_sub_ofst;
+ u32 chroma_h_int_ofst;
+ u32 chroma_h_sub_ofst;
+ u32 rsz_switch;
+ u32 merge_cfg;
} __packed;
struct mdp_rsz_data {
@@ -196,9 +261,70 @@ struct mdp_rsz_data {
u32 coeff_step_y;
u32 control1;
u32 control2;
+ u32 etc_control;
+ u32 prz_enable;
+ u32 ibse_softclip;
+ u32 tap_adapt;
+ u32 ibse_gaincontrol1;
+ u32 ibse_gaincontrol2;
+ u32 ibse_ylevel_1;
+ u32 ibse_ylevel_2;
+ u32 ibse_ylevel_3;
+ u32 ibse_ylevel_4;
+ u32 ibse_ylevel_5;
struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES];
} __packed;
+struct mdp_tdshp_subfrm {
+ u32 src;
+ u32 clip;
+ u32 clip_ofst;
+ u32 hist_cfg_0;
+ u32 hist_cfg_1;
+} __packed;
+
+struct mdp_tdshp_data {
+ u32 cfg;
+ struct mdp_tdshp_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_color_subfrm {
+ u32 in_hsize;
+ u32 in_vsize;
+} __packed;
+
+struct mdp_color_data {
+ u32 start;
+ struct mdp_color_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_ovl_subfrm {
+ u32 L0_src_size;
+ u32 roi_size;
+} __packed;
+
+struct mdp_ovl_data {
+ u32 L0_con;
+ u32 src_con;
+ struct mdp_ovl_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_pad_subfrm {
+ u32 pic_size;
+} __packed;
+
+struct mdp_pad_data {
+ struct mdp_pad_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_tcc_subfrm {
+ u32 pic_size;
+} __packed;
+
+struct mdp_tcc_data {
+ struct mdp_tcc_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
struct mdp_wrot_subfrm {
u32 offset[IMG_MAX_PLANES];
u32 src;
@@ -214,6 +340,14 @@ struct mdp_wrot_data {
u32 mat_ctrl;
u32 fifo_test;
u32 filter;
+ u32 pre_ultra;
+ u32 framesize;
+ u32 afbc_yuvtrans;
+ u32 scan_10bit;
+ u32 pending_zero;
+ u32 bit_number;
+ u32 pvric;
+ u32 vpp02vpp1;
struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES];
} __packed;
@@ -241,8 +375,8 @@ struct isp_data {
} __packed;
struct img_compparam {
- u16 type; /* enum mdp_comp_type */
- u16 id; /* enum mtk_mdp_comp_id */
+ u32 type; /* enum mdp_comp_id */
+ u32 id; /* engine alias_id */
u32 input;
u32 outputs[IMG_MAX_HW_OUTPUTS];
u32 num_outputs;
@@ -251,7 +385,15 @@ struct img_compparam {
u32 num_subfrms;
union {
struct mdp_rdma_data rdma;
+ struct mdp_fg_data fg;
+ struct mdp_hdr_data hdr;
+ struct mdp_aal_data aal;
struct mdp_rsz_data rsz;
+ struct mdp_tdshp_data tdshp;
+ struct mdp_color_data color;
+ struct mdp_ovl_data ovl;
+ struct mdp_pad_data pad;
+ struct mdp_tcc_data tcc;
struct mdp_wrot_data wrot;
struct mdp_wdma_data wdma;
struct isp_data isp;
@@ -263,12 +405,13 @@ struct img_compparam {
struct img_mux {
u32 reg;
u32 value;
-};
+ u32 vpp_id;
+} __packed;
struct img_mmsys_ctrl {
struct img_mux sets[IMG_MAX_COMPONENTS * 2];
u32 num_sets;
-};
+} __packed;
struct img_config {
struct img_compparam components[IMG_MAX_COMPONENTS];
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 06/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
1. Modify struct member to 4 byte-alignment for MT8195 SCP limitation
2. Add new struct for hw engine adding in MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 219 +++++++++++++++---
1 file changed, 181 insertions(+), 38 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h b/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
index f8560dad87da..8dd0bcdee431 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
@@ -42,14 +42,14 @@ struct img_sw_addr {
struct img_plane_format {
u32 size;
- u16 stride;
+ u32 stride;
} __packed;
struct img_pix_format {
- u16 width;
- u16 height;
+ u32 width;
+ u32 height;
u32 colorformat; /* enum mdp_color */
- u16 ycbcr_prof; /* enum mdp_ycbcr_profile */
+ u32 ycbcr_prof; /* enum mdp_ycbcr_profile */
struct img_plane_format plane_fmt[IMG_MAX_PLANES];
} __packed;
@@ -63,10 +63,10 @@ struct img_image_buffer {
#define IMG_SUBPIXEL_SHIFT 20
struct img_crop {
- s16 left;
- s16 top;
- u16 width;
- u16 height;
+ s32 left;
+ s32 top;
+ u32 width;
+ u32 height;
u32 left_subpix;
u32 top_subpix;
u32 width_subpix;
@@ -78,27 +78,29 @@ struct img_crop {
#define IMG_CTRL_FLAG_SHARPNESS BIT(4)
#define IMG_CTRL_FLAG_HDR BIT(5)
#define IMG_CTRL_FLAG_DRE BIT(6)
+#define IMG_CTRL_FLAG_RSZ BIT(7)
struct img_input {
struct img_image_buffer buffer;
- u16 flags; /* HDR, DRE, dither */
+ u32 flags; /* HDR, DRE, dither */
} __packed;
struct img_output {
struct img_image_buffer buffer;
struct img_crop crop;
- s16 rotation;
- u16 flags; /* H-flip, sharpness, dither */
+ s32 rotation;
+ u32 flags; /* H-flip, sharpness, dither */
+ u64 pqid;
} __packed;
struct img_ipi_frameparam {
u32 index;
u32 frame_no;
u64 timestamp;
- u8 type; /* enum mdp_stream_type */
- u8 state;
- u8 num_inputs;
- u8 num_outputs;
+ u32 type; /* enum mdp_stream_type */
+ u32 state;
+ u32 num_inputs;
+ u32 num_outputs;
u64 drv_data;
struct img_input inputs[IMG_MAX_HW_INPUTS];
struct img_output outputs[IMG_MAX_HW_OUTPUTS];
@@ -106,6 +108,7 @@ struct img_ipi_frameparam {
struct img_addr subfrm_data;
struct img_sw_addr config_data;
struct img_sw_addr self_data;
+ u32 frame_change;
} __packed;
struct img_sw_buffer {
@@ -114,51 +117,51 @@ struct img_sw_buffer {
} __packed;
struct img_ipi_param {
- u8 usage;
+ u32 usage;
struct img_sw_buffer frm_param;
} __packed;
struct img_frameparam {
struct list_head list_entry;
struct img_ipi_frameparam frameparam;
-};
+} __packed;
/* ISP-MDP generic output information */
struct img_comp_frame {
- u32 output_disable:1;
- u32 bypass:1;
- u16 in_width;
- u16 in_height;
- u16 out_width;
- u16 out_height;
+ u32 output_disable;
+ u32 bypass;
+ u32 in_width;
+ u32 in_height;
+ u32 out_width;
+ u32 out_height;
struct img_crop crop;
- u16 in_total_width;
- u16 out_total_width;
+ u32 in_total_width;
+ u32 out_total_width;
} __packed;
struct img_region {
- s16 left;
- s16 right;
- s16 top;
- s16 bottom;
+ s32 left;
+ s32 right;
+ s32 top;
+ s32 bottom;
} __packed;
struct img_offset {
- s16 left;
- s16 top;
+ s32 left;
+ s32 top;
u32 left_subpix;
u32 top_subpix;
} __packed;
struct img_comp_subfrm {
- u32 tile_disable:1;
+ u32 tile_disable;
struct img_region in;
struct img_region out;
struct img_offset luma;
struct img_offset chroma;
- s16 out_vertical; /* Output vertical index */
- s16 out_horizontal; /* Output horizontal index */
+ s32 out_vertical; /* Output vertical index */
+ s32 out_horizontal; /* Output horizontal index */
} __packed;
#define IMG_MAX_SUBFRAMES 14
@@ -169,10 +172,13 @@ struct mdp_rdma_subfrm {
u32 src;
u32 clip;
u32 clip_ofst;
+ u32 in_tile_xleft;
+ u32 in_tile_ytop;
} __packed;
struct mdp_rdma_data {
u32 src_ctrl;
+ u32 comp_ctrl;
u32 control;
u32 iova[IMG_MAX_PLANES];
u32 iova_end[IMG_MAX_PLANES];
@@ -182,13 +188,72 @@ struct mdp_rdma_data {
u32 ufo_dec_y;
u32 ufo_dec_c;
u32 transform;
+ u32 dmabuf_con0;
+ u32 ultra_th_high_con0;
+ u32 ultra_th_low_con0;
+ u32 dmabuf_con1;
+ u32 ultra_th_high_con1;
+ u32 ultra_th_low_con1;
+ u32 dmabuf_con2;
+ u32 ultra_th_high_con2;
+ u32 ultra_th_low_con2;
+ u32 dmabuf_con3;
struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES];
} __packed;
+struct mdp_fg_subfrm {
+ u32 info_0;
+ u32 info_1;
+} __packed;
+
+struct mdp_fg_data {
+ u32 ctrl_0;
+ u32 ck_en;
+ struct mdp_fg_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_hdr_subfrm {
+ u32 win_size;
+ u32 src;
+ u32 clip_ofst0;
+ u32 clip_ofst1;
+ u32 hist_ctrl_0;
+ u32 hist_ctrl_1;
+ u32 hdr_top;
+ u32 hist_addr;
+} __packed;
+
+struct mdp_hdr_data {
+ u32 top;
+ u32 relay;
+ struct mdp_hdr_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_aal_subfrm {
+ u32 src;
+ u32 clip;
+ u32 clip_ofst;
+} __packed;
+
+struct mdp_aal_data {
+ u32 cfg_main;
+ u32 cfg;
+ struct mdp_aal_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
struct mdp_rsz_subfrm {
u32 control2;
u32 src;
u32 clip;
+ u32 hdmirx_en;
+ u32 luma_h_int_ofst;
+ u32 luma_h_sub_ofst;
+ u32 luma_v_int_ofst;
+ u32 luma_v_sub_ofst;
+ u32 chroma_h_int_ofst;
+ u32 chroma_h_sub_ofst;
+ u32 rsz_switch;
+ u32 merge_cfg;
} __packed;
struct mdp_rsz_data {
@@ -196,9 +261,70 @@ struct mdp_rsz_data {
u32 coeff_step_y;
u32 control1;
u32 control2;
+ u32 etc_control;
+ u32 prz_enable;
+ u32 ibse_softclip;
+ u32 tap_adapt;
+ u32 ibse_gaincontrol1;
+ u32 ibse_gaincontrol2;
+ u32 ibse_ylevel_1;
+ u32 ibse_ylevel_2;
+ u32 ibse_ylevel_3;
+ u32 ibse_ylevel_4;
+ u32 ibse_ylevel_5;
struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES];
} __packed;
+struct mdp_tdshp_subfrm {
+ u32 src;
+ u32 clip;
+ u32 clip_ofst;
+ u32 hist_cfg_0;
+ u32 hist_cfg_1;
+} __packed;
+
+struct mdp_tdshp_data {
+ u32 cfg;
+ struct mdp_tdshp_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_color_subfrm {
+ u32 in_hsize;
+ u32 in_vsize;
+} __packed;
+
+struct mdp_color_data {
+ u32 start;
+ struct mdp_color_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_ovl_subfrm {
+ u32 L0_src_size;
+ u32 roi_size;
+} __packed;
+
+struct mdp_ovl_data {
+ u32 L0_con;
+ u32 src_con;
+ struct mdp_ovl_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_pad_subfrm {
+ u32 pic_size;
+} __packed;
+
+struct mdp_pad_data {
+ struct mdp_pad_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
+struct mdp_tcc_subfrm {
+ u32 pic_size;
+} __packed;
+
+struct mdp_tcc_data {
+ struct mdp_tcc_subfrm subfrms[IMG_MAX_SUBFRAMES];
+} __packed;
+
struct mdp_wrot_subfrm {
u32 offset[IMG_MAX_PLANES];
u32 src;
@@ -214,6 +340,14 @@ struct mdp_wrot_data {
u32 mat_ctrl;
u32 fifo_test;
u32 filter;
+ u32 pre_ultra;
+ u32 framesize;
+ u32 afbc_yuvtrans;
+ u32 scan_10bit;
+ u32 pending_zero;
+ u32 bit_number;
+ u32 pvric;
+ u32 vpp02vpp1;
struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES];
} __packed;
@@ -241,8 +375,8 @@ struct isp_data {
} __packed;
struct img_compparam {
- u16 type; /* enum mdp_comp_type */
- u16 id; /* enum mtk_mdp_comp_id */
+ u32 type; /* enum mdp_comp_id */
+ u32 id; /* engine alias_id */
u32 input;
u32 outputs[IMG_MAX_HW_OUTPUTS];
u32 num_outputs;
@@ -251,7 +385,15 @@ struct img_compparam {
u32 num_subfrms;
union {
struct mdp_rdma_data rdma;
+ struct mdp_fg_data fg;
+ struct mdp_hdr_data hdr;
+ struct mdp_aal_data aal;
struct mdp_rsz_data rsz;
+ struct mdp_tdshp_data tdshp;
+ struct mdp_color_data color;
+ struct mdp_ovl_data ovl;
+ struct mdp_pad_data pad;
+ struct mdp_tcc_data tcc;
struct mdp_wrot_data wrot;
struct mdp_wdma_data wdma;
struct isp_data isp;
@@ -263,12 +405,13 @@ struct img_compparam {
struct img_mux {
u32 reg;
u32 value;
-};
+ u32 vpp_id;
+} __packed;
struct img_mmsys_ctrl {
struct img_mux sets[IMG_MAX_COMPONENTS * 2];
u32 num_sets;
-};
+} __packed;
struct img_config {
struct img_compparam components[IMG_MAX_COMPONENTS];
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 07/14] media: platform: mtk-mdp3: Add platform configuration for MT8195
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add platform configuration for MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mt8195_mdp.h | 682 ++++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 144 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 22 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 13 +
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 11 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 67 ++
6 files changed, 933 insertions(+), 6 deletions(-)
create mode 100644 drivers/media/platform/mtk-mdp3/mt8195_mdp.h
diff --git a/drivers/media/platform/mtk-mdp3/mt8195_mdp.h b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
new file mode 100644
index 000000000000..f69bc86bcd1e
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
@@ -0,0 +1,682 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MT8195_MDP_H__
+#define __MT8195_MDP_H__
+
+static const struct mdp_platform_config mt8195_plat_cfg = {
+ .rdma_support_10bit = true,
+ .rdma_support_extend_ufo = true,
+ .rdma_support_hyfbc = true,
+ .rdma_support_afbc = true,
+ .rdma_esl_setting = true,
+ .rdma_rsz1_sram_sharing = false,
+ .rdma_upsample_repeat_only = false,
+ .rsz_disable_dcm_small_sample = false,
+ .rsz_etc_control = true,
+ .wrot_filter_constraint = false,
+ .tdshp_1_1 = true,
+ .tdshp_dyn_contrast_version = 2,
+ .mdp_version_8195 = true,
+ .mdp_version_6885 = true,
+ .gce_event_offset = 0,
+ .support_multi_larb = true,
+};
+
+enum mt8195_mdp_comp_id {
+ /* MT8195 Comp id */
+ /* ISP */
+ MT8195_MDP_COMP_WPEI = 0,
+ MT8195_MDP_COMP_WPEO, /* 1 */
+ MT8195_MDP_COMP_WPEI2, /* 2 */
+ MT8195_MDP_COMP_WPEO2, /* 3 */
+
+ /* MDP */
+ MT8195_MDP_COMP_CAMIN, /* 4 */
+ MT8195_MDP_COMP_CAMIN2, /* 5 */
+ MT8195_MDP_COMP_SPLIT, /* 6 */
+ MT8195_MDP_COMP_SPLIT2, /* 7 */
+ MT8195_MDP_COMP_RDMA0, /* 8 */
+ MT8195_MDP_COMP_RDMA1, /* 9 */
+ MT8195_MDP_COMP_RDMA2, /* 10 */
+ MT8195_MDP_COMP_RDMA3, /* 11 */
+ MT8195_MDP_COMP_STITCH, /* 12 */
+ MT8195_MDP_COMP_FG0, /* 13 */
+ MT8195_MDP_COMP_FG1, /* 14 */
+ MT8195_MDP_COMP_FG2, /* 15 */
+ MT8195_MDP_COMP_FG3, /* 16 */
+ MT8195_MDP_COMP_TO_SVPP2MOUT, /* 17 */
+ MT8195_MDP_COMP_TO_SVPP3MOUT, /* 18 */
+ MT8195_MDP_COMP_TO_WARP0MOUT, /* 19 */
+ MT8195_MDP_COMP_TO_WARP1MOUT, /* 20 */
+ MT8195_MDP_COMP_VPP0_SOUT, /* 21 */
+ MT8195_MDP_COMP_VPP1_SOUT, /* 22 */
+ MT8195_MDP_COMP_PQ0_SOUT, /* 23 */
+ MT8195_MDP_COMP_PQ1_SOUT, /* 24 */
+ MT8195_MDP_COMP_HDR0, /* 25 */
+ MT8195_MDP_COMP_HDR1, /* 26 */
+ MT8195_MDP_COMP_HDR2, /* 27 */
+ MT8195_MDP_COMP_HDR3, /* 28 */
+ MT8195_MDP_COMP_AAL0, /* 29 */
+ MT8195_MDP_COMP_AAL1, /* 30 */
+ MT8195_MDP_COMP_AAL2, /* 31 */
+ MT8195_MDP_COMP_AAL3, /* 32 */
+ MT8195_MDP_COMP_RSZ0, /* 33 */
+ MT8195_MDP_COMP_RSZ1, /* 34 */
+ MT8195_MDP_COMP_RSZ2, /* 35 */
+ MT8195_MDP_COMP_RSZ3, /* 36 */
+ MT8195_MDP_COMP_TDSHP0, /* 37 */
+ MT8195_MDP_COMP_TDSHP1, /* 38 */
+ MT8195_MDP_COMP_TDSHP2, /* 39 */
+ MT8195_MDP_COMP_TDSHP3, /* 40 */
+ MT8195_MDP_COMP_COLOR0, /* 41 */
+ MT8195_MDP_COMP_COLOR1, /* 42 */
+ MT8195_MDP_COMP_COLOR2, /* 43 */
+ MT8195_MDP_COMP_COLOR3, /* 44 */
+ MT8195_MDP_COMP_OVL0, /* 45 */
+ MT8195_MDP_COMP_OVL1, /* 46 */
+ MT8195_MDP_COMP_PAD0, /* 47 */
+ MT8195_MDP_COMP_PAD1, /* 48 */
+ MT8195_MDP_COMP_PAD2, /* 49 */
+ MT8195_MDP_COMP_PAD3, /* 50 */
+ MT8195_MDP_COMP_TCC0, /* 51 */
+ MT8195_MDP_COMP_TCC1, /* 52 */
+ MT8195_MDP_COMP_WROT0, /* 53 */
+ MT8195_MDP_COMP_WROT1, /* 54 */
+ MT8195_MDP_COMP_WROT2, /* 55 */
+ MT8195_MDP_COMP_WROT3, /* 56 */
+ MT8195_MDP_COMP_MERGE2, /* 57 */
+ MT8195_MDP_COMP_MERGE3, /* 58 */
+
+ MT8195_MDP_COMP_VDO0DL0, /* 59 */
+ MT8195_MDP_COMP_VDO1DL0, /* 60 */
+ MT8195_MDP_COMP_VDO0DL1, /* 61 */
+ MT8195_MDP_COMP_VDO1DL1, /* 62 */
+};
+
+static const struct mdp_comp_data mt8195_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_WPEI] = {
+ {MDP_COMP_TYPE_WPEI, 0, MT8195_MDP_COMP_WPEI},
+ {0, 0, 0},
+ {0, BIT(13), 0}
+ },
+ [MDP_COMP_WPEO] = {
+ {MDP_COMP_TYPE_EXTO, 2, MT8195_MDP_COMP_WPEO},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEI2] = {
+ {MDP_COMP_TYPE_WPEI, 1, MT8195_MDP_COMP_WPEI2},
+ {0, 0, 0},
+ {0, BIT(14), 0}
+ },
+ [MDP_COMP_WPEO2] = {
+ {MDP_COMP_TYPE_EXTO, 3, MT8195_MDP_COMP_WPEO2},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN] = {
+ {MDP_COMP_TYPE_DL_PATH1, 0, MT8195_MDP_COMP_CAMIN},
+ {3, 3, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN2] = {
+ {MDP_COMP_TYPE_DL_PATH2, 1, MT8195_MDP_COMP_CAMIN2},
+ {3, 6, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_SPLIT] = {
+ {MDP_COMP_TYPE_SPLIT, 0, MT8195_MDP_COMP_SPLIT},
+ {7, 0, 0},
+ {1, BIT(2), 0}
+ },
+ [MDP_COMP_SPLIT2] = {
+ {MDP_COMP_TYPE_SPLIT, 1, MT8195_MDP_COMP_SPLIT2},
+ {7, 0, 0},
+ {1, BIT(2), 0}
+ },
+ [MDP_COMP_RDMA0] = {
+ {MDP_COMP_TYPE_RDMA, 0, MT8195_MDP_COMP_RDMA0},
+ {3, 0, 0},
+ {0, BIT(0), 0}
+ },
+ [MDP_COMP_RDMA1] = {
+ {MDP_COMP_TYPE_RDMA, 1, MT8195_MDP_COMP_RDMA1},
+ {3, 0, 0},
+ {1, BIT(4), 0}
+ },
+ [MDP_COMP_RDMA2] = {
+ {MDP_COMP_TYPE_RDMA, 2, MT8195_MDP_COMP_RDMA2},
+ {3, 0, 0},
+ {1, BIT(5), 0}
+ },
+ [MDP_COMP_RDMA3] = {
+ {MDP_COMP_TYPE_RDMA, 3, MT8195_MDP_COMP_RDMA3},
+ {3, 0, 0},
+ {1, BIT(6), 0}
+ },
+ [MDP_COMP_STITCH] = {
+ {MDP_COMP_TYPE_STITCH, 0, MT8195_MDP_COMP_STITCH},
+ {1, 0, 0},
+ {0, BIT(2), 0}
+ },
+ [MDP_COMP_FG0] = {
+ {MDP_COMP_TYPE_FG, 0, MT8195_MDP_COMP_FG0},
+ {1, 0, 0},
+ {0, BIT(1), 0}
+ },
+ [MDP_COMP_FG1] = {
+ {MDP_COMP_TYPE_FG, 1, MT8195_MDP_COMP_FG1},
+ {1, 0, 0},
+ {1, BIT(7), 0}
+ },
+ [MDP_COMP_FG2] = {
+ {MDP_COMP_TYPE_FG, 2, MT8195_MDP_COMP_FG2},
+ {1, 0, 0},
+ {1, BIT(8), 0}
+ },
+ [MDP_COMP_FG3] = {
+ {MDP_COMP_TYPE_FG, 3, MT8195_MDP_COMP_FG3},
+ {1, 0, 0},
+ {1, BIT(9), 0}
+ },
+ [MDP_COMP_HDR0] = {
+ {MDP_COMP_TYPE_HDR, 0, MT8195_MDP_COMP_HDR0},
+ {1, 0, 0},
+ {0, BIT(3), 0}
+ },
+ [MDP_COMP_HDR1] = {
+ {MDP_COMP_TYPE_HDR, 1, MT8195_MDP_COMP_HDR1},
+ {1, 0, 0},
+ {1, BIT(10), 0}
+ },
+ [MDP_COMP_HDR2] = {
+ {MDP_COMP_TYPE_HDR, 2, MT8195_MDP_COMP_HDR2},
+ {1, 0, 0},
+ {1, BIT(11), 0}
+ },
+ [MDP_COMP_HDR3] = {
+ {MDP_COMP_TYPE_HDR, 3, MT8195_MDP_COMP_HDR3},
+ {1, 0, 0},
+ {1, BIT(12), 0}
+ },
+ [MDP_COMP_AAL0] = {
+ {MDP_COMP_TYPE_AAL, 0, MT8195_MDP_COMP_AAL0},
+ {1, 0, 0},
+ {0, BIT(4), 0}
+ },
+ [MDP_COMP_AAL1] = {
+ {MDP_COMP_TYPE_AAL, 1, MT8195_MDP_COMP_AAL1},
+ {1, 0, 0},
+ {1, BIT(13), 0}
+ },
+ [MDP_COMP_AAL2] = {
+ {MDP_COMP_TYPE_AAL, 2, MT8195_MDP_COMP_AAL2},
+ {1, 0, 0},
+ {1, BIT(14), 0}
+ },
+ [MDP_COMP_AAL3] = {
+ {MDP_COMP_TYPE_AAL, 3, MT8195_MDP_COMP_AAL3},
+ {1, 0, 0},
+ {1, BIT(15), 0}
+ },
+ [MDP_COMP_RSZ0] = {
+ {MDP_COMP_TYPE_RSZ, 0, MT8195_MDP_COMP_RSZ0},
+ {1, 0, 0},
+ {0, BIT(5), 0}
+ },
+ [MDP_COMP_RSZ1] = {
+ {MDP_COMP_TYPE_RSZ, 1, MT8195_MDP_COMP_RSZ1},
+ {1, 0, 0},
+ {1, BIT(16), 0}
+ },
+ [MDP_COMP_RSZ2] = {
+ {MDP_COMP_TYPE_RSZ, 2, MT8195_MDP_COMP_RSZ2},
+ {2, 0, 0},
+ {1, BIT(17) | BIT(22), 0}
+ },
+ [MDP_COMP_RSZ3] = {
+ {MDP_COMP_TYPE_RSZ, 3, MT8195_MDP_COMP_RSZ3},
+ {2, 0, 0},
+ {1, BIT(18) | BIT(23), 0}
+ },
+ [MDP_COMP_TDSHP0] = {
+ {MDP_COMP_TYPE_TDSHP, 0, MT8195_MDP_COMP_TDSHP0},
+ {1, 0, 0},
+ {0, BIT(6), 0}
+ },
+ [MDP_COMP_TDSHP1] = {
+ {MDP_COMP_TYPE_TDSHP, 1, MT8195_MDP_COMP_TDSHP1},
+ {1, 0, 0},
+ {1, BIT(19), 0}
+ },
+ [MDP_COMP_TDSHP2] = {
+ {MDP_COMP_TYPE_TDSHP, 2, MT8195_MDP_COMP_TDSHP2},
+ {1, 0, 0},
+ {1, BIT(20), 0}
+ },
+ [MDP_COMP_TDSHP3] = {
+ {MDP_COMP_TYPE_TDSHP, 3, MT8195_MDP_COMP_TDSHP3},
+ {1, 0, 0},
+ {1, BIT(21), 0}
+ },
+ [MDP_COMP_COLOR0] = {
+ {MDP_COMP_TYPE_COLOR, 0, MT8195_MDP_COMP_COLOR0},
+ {1, 0, 0},
+ {0, BIT(7), 0}
+ },
+ [MDP_COMP_COLOR1] = {
+ {MDP_COMP_TYPE_COLOR, 1, MT8195_MDP_COMP_COLOR1},
+ {1, 0, 0},
+ {1, BIT(24), 0}
+ },
+ [MDP_COMP_COLOR2] = {
+ {MDP_COMP_TYPE_COLOR, 2, MT8195_MDP_COMP_COLOR2},
+ {1, 0, 0},
+ {1, BIT(25), 0}
+ },
+ [MDP_COMP_COLOR3] = {
+ {MDP_COMP_TYPE_COLOR, 3, MT8195_MDP_COMP_COLOR3},
+ {1, 0, 0},
+ {1, BIT(26), 0}
+ },
+ [MDP_COMP_OVL0] = {
+ {MDP_COMP_TYPE_OVL, 0, MT8195_MDP_COMP_OVL0},
+ {1, 0, 0},
+ {0, BIT(8), 0}
+ },
+ [MDP_COMP_OVL1] = {
+ {MDP_COMP_TYPE_OVL, 1, MT8195_MDP_COMP_OVL1},
+ {1, 0, 0},
+ {1, BIT(27), 0}
+ },
+ [MDP_COMP_PAD0] = {
+ {MDP_COMP_TYPE_PAD, 0, MT8195_MDP_COMP_PAD0},
+ {1, 0, 0},
+ {0, BIT(9), 0}
+ },
+ [MDP_COMP_PAD1] = {
+ {MDP_COMP_TYPE_PAD, 1, MT8195_MDP_COMP_PAD1},
+ {1, 0, 0},
+ {1, BIT(28), 0}
+ },
+ [MDP_COMP_PAD2] = {
+ {MDP_COMP_TYPE_PAD, 2, MT8195_MDP_COMP_PAD2},
+ {1, 0, 0},
+ {1, BIT(29), 0}
+ },
+ [MDP_COMP_PAD3] = {
+ {MDP_COMP_TYPE_PAD, 3, MT8195_MDP_COMP_PAD3},
+ {1, 0, 0},
+ {1, BIT(30), 0}
+ },
+ [MDP_COMP_TCC0] = {
+ {MDP_COMP_TYPE_TCC, 0, MT8195_MDP_COMP_TCC0},
+ {1, 0, 0},
+ {0, BIT(10), 0}
+ },
+ [MDP_COMP_TCC1] = {
+ {MDP_COMP_TYPE_TCC, 1, MT8195_MDP_COMP_TCC1},
+ {1, 0, 0},
+ {1, BIT(3), 0}
+ },
+ [MDP_COMP_WROT0] = {
+ {MDP_COMP_TYPE_WROT, 0, MT8195_MDP_COMP_WROT0},
+ {1, 0, 0},
+ {0, BIT(11), 0}
+ },
+ [MDP_COMP_WROT1] = {
+ {MDP_COMP_TYPE_WROT, 1, MT8195_MDP_COMP_WROT1},
+ {1, 0, 0},
+ {1, BIT(31), 0}
+ },
+ [MDP_COMP_WROT2] = {
+ {MDP_COMP_TYPE_WROT, 2, MT8195_MDP_COMP_WROT2},
+ {1, 0, 0},
+ {1, 0, BIT(0)}
+ },
+ [MDP_COMP_WROT3] = {
+ {MDP_COMP_TYPE_WROT, 3, MT8195_MDP_COMP_WROT3},
+ {1, 0, 0},
+ {1, 0, BIT(1)}
+ },
+ [MDP_COMP_MERGE2] = {
+ {MDP_COMP_TYPE_MERGE, 2, MT8195_MDP_COMP_MERGE2},
+ {1, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_MERGE3] = {
+ {MDP_COMP_TYPE_MERGE, 3, MT8195_MDP_COMP_MERGE2},
+ {1, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_PQ0_SOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 0, MT8195_MDP_COMP_PQ0_SOUT},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_PQ1_SOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 1, MT8195_MDP_COMP_PQ1_SOUT},
+ {0, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_TO_WARP0MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 2, MT8195_MDP_COMP_TO_WARP0MOUT},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_TO_WARP1MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 3, MT8195_MDP_COMP_TO_WARP1MOUT},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_TO_SVPP2MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 4, MT8195_MDP_COMP_TO_SVPP2MOUT},
+ {0, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_TO_SVPP3MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 5, MT8195_MDP_COMP_TO_SVPP3MOUT},
+ {0, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_VPP0_SOUT] = {
+ {MDP_COMP_TYPE_PATH1, 0, MT8195_MDP_COMP_VPP0_SOUT},
+ {4, 9, 0},
+ {0, BIT(15), BIT(2)}
+ },
+ [MDP_COMP_VPP1_SOUT] = {
+ {MDP_COMP_TYPE_PATH2, 1, MT8195_MDP_COMP_VPP1_SOUT},
+ {2, 13, 0},
+ {1, BIT(16), BIT(3)}
+ },
+ [MDP_COMP_VDO0DL0] = {
+ {MDP_COMP_TYPE_DL_PATH3, 0, MT8195_MDP_COMP_VDO0DL0},
+ {1, 15, 0},
+ {1, 0, BIT(4)}
+ },
+ [MDP_COMP_VDO1DL0] = {
+ {MDP_COMP_TYPE_DL_PATH4, 0, MT8195_MDP_COMP_VDO1DL0},
+ {1, 17, 0},
+ {1, 0, BIT(6)}
+ },
+ [MDP_COMP_VDO0DL1] = {
+ {MDP_COMP_TYPE_DL_PATH5, 0, MT8195_MDP_COMP_VDO0DL1},
+ {1, 18, 0},
+ {1, 0, BIT(5)}
+ },
+ [MDP_COMP_VDO1DL1] = {
+ {MDP_COMP_TYPE_DL_PATH6, 0, MT8195_MDP_COMP_VDO1DL1},
+ {1, 16, 0},
+ {1, 0, BIT(7)}
+ },
+};
+
+static const enum mdp_comp_event mt8195_mdp_event[] = {
+ RDMA0_SOF,
+ WROT0_SOF,
+ RDMA0_DONE,
+ WROT0_DONE,
+ RDMA1_SOF,
+ RDMA2_SOF,
+ RDMA3_SOF,
+ WROT1_SOF,
+ WROT2_SOF,
+ WROT3_SOF,
+ RDMA1_DONE,
+ RDMA2_DONE,
+ RDMA3_DONE,
+ WROT1_DONE,
+ WROT2_DONE,
+ WROT3_DONE
+};
+
+static const struct mdp_pipe_info mt8195_pipe_info[] = {
+ {MDP_PIPE_WPEI, 0, 0},
+ {MDP_PIPE_WPEI2, 0, 1},
+ {MDP_PIPE_RDMA0, 0, 2},
+ {MDP_PIPE_VPP1_SOUT, 0, 3},
+ {MDP_PIPE_SPLIT, 1, 2, 0x387},
+ {MDP_PIPE_SPLIT2, 1, 3, 0x387},
+ {MDP_PIPE_RDMA1, 1, 1},
+ {MDP_PIPE_RDMA2, 1, 2},
+ {MDP_PIPE_RDMA3, 1, 3},
+ {MDP_PIPE_VPP0_SOUT, 1, 4},
+};
+
+static const struct mdp_format mt8195_formats[] = {
+ {
+ .pixelformat = V4L2_PIX_FMT_GREY,
+ .mdp_color = MDP_COLOR_GREY,
+ .depth = { 8 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565X,
+ .mdp_color = MDP_COLOR_RGB565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565,
+ .mdp_color = MDP_COLOR_BGR565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB24,
+ .mdp_color = MDP_COLOR_RGB888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_BGR24,
+ .mdp_color = MDP_COLOR_BGR888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ABGR32,
+ .mdp_color = MDP_COLOR_BGRA8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ARGB32,
+ .mdp_color = MDP_COLOR_ARGB8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_UYVY,
+ .mdp_color = MDP_COLOR_UYVY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_VYUY,
+ .mdp_color = MDP_COLOR_VYUY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .mdp_color = MDP_COLOR_YUYV,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVYU,
+ .mdp_color = MDP_COLOR_YVYU,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV24,
+ .mdp_color = MDP_COLOR_NV24,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV42,
+ .mdp_color = MDP_COLOR_NV42,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MT21C,
+ .mdp_color = MDP_COLOR_NV12_HYFBC,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 1,
+ .walign = 4,
+ .halign = 4,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MM21,
+ .mdp_color = MDP_COLOR_420_BLKP,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12M,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21M,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16M,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61M,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420M,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420M,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }
+};
+
+static const u32 mt8195_mdp_mmsys_config_table[] = {
+ [CONFIG_VPP0_HW_DCM_1ST_DIS0] = 0,
+ [CONFIG_VPP0_DL_IRELAY_WR] = 1,
+ [CONFIG_VPP1_HW_DCM_1ST_DIS0] = 2,
+ [CONFIG_VPP1_HW_DCM_1ST_DIS1] = 3,
+ [CONFIG_VPP1_HW_DCM_2ND_DIS0] = 4,
+ [CONFIG_VPP1_HW_DCM_2ND_DIS1] = 5,
+ [CONFIG_SVPP2_BUF_BF_RSZ_SWITCH] = 6,
+ [CONFIG_SVPP3_BUF_BF_RSZ_SWITCH] = 7,
+};
+
+#endif // __MT8195_MDP_H__
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index 9073ddc19775..fdf072e48238 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -919,6 +919,126 @@ static const struct of_device_id mdp_comp_dt_ids[] = {
}, {
.compatible = "mediatek,mt8183-mdp3-wdma",
.data = (void *)MDP_COMP_WDMA,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rdma1",
+ .data = (void *)MDP_COMP_RDMA1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rdma2",
+ .data = (void *)MDP_COMP_RDMA2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rdma3",
+ .data = (void *)MDP_COMP_RDMA3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-wrot1",
+ .data = (void *)MDP_COMP_WROT1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-wrot2",
+ .data = (void *)MDP_COMP_WROT2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-wrot3",
+ .data = (void *)MDP_COMP_WROT3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-split",
+ .data = (void *)MDP_COMP_SPLIT,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-stitch",
+ .data = (void *)MDP_COMP_STITCH,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg0",
+ .data = (void *)MDP_COMP_FG0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg1",
+ .data = (void *)MDP_COMP_FG1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg2",
+ .data = (void *)MDP_COMP_FG2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg3",
+ .data = (void *)MDP_COMP_FG3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr0",
+ .data = (void *)MDP_COMP_HDR0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr1",
+ .data = (void *)MDP_COMP_HDR1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr2",
+ .data = (void *)MDP_COMP_HDR2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr3",
+ .data = (void *)MDP_COMP_HDR3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal0",
+ .data = (void *)MDP_COMP_AAL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal1",
+ .data = (void *)MDP_COMP_AAL1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal2",
+ .data = (void *)MDP_COMP_AAL2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal3",
+ .data = (void *)MDP_COMP_AAL3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rsz2",
+ .data = (void *)MDP_COMP_RSZ2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rsz3",
+ .data = (void *)MDP_COMP_RSZ3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-merge2",
+ .data = (void *)MDP_COMP_MERGE2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-merge3",
+ .data = (void *)MDP_COMP_MERGE3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp0",
+ .data = (void *)MDP_COMP_TDSHP0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp1",
+ .data = (void *)MDP_COMP_TDSHP1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp2",
+ .data = (void *)MDP_COMP_TDSHP2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp3",
+ .data = (void *)MDP_COMP_TDSHP3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color0",
+ .data = (void *)MDP_COMP_COLOR0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color1",
+ .data = (void *)MDP_COMP_COLOR1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color2",
+ .data = (void *)MDP_COMP_COLOR2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color3",
+ .data = (void *)MDP_COMP_COLOR3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-ovl0",
+ .data = (void *)MDP_COMP_OVL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-ovl1",
+ .data = (void *)MDP_COMP_OVL1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad0",
+ .data = (void *)MDP_COMP_PAD0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad1",
+ .data = (void *)MDP_COMP_PAD1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad2",
+ .data = (void *)MDP_COMP_PAD2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad3",
+ .data = (void *)MDP_COMP_PAD3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tcc0",
+ .data = (void *)MDP_COMP_TCC0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tcc1",
+ .data = (void *)MDP_COMP_TCC1,
},
{}
};
@@ -936,12 +1056,36 @@ static const struct of_device_id mdp_sub_comp_dt_ids[] = {
}, {
.compatible = "mediatek,mt8183-mdp3-exto",
.data = (void *)MDP_COMP_ISP_IMGO,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path1",
+ .data = (void *)MDP_COMP_VPP0_SOUT,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path2",
+ .data = (void *)MDP_COMP_VPP1_SOUT,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path3",
+ .data = (void *)MDP_COMP_VDO0DL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path4",
+ .data = (void *)MDP_COMP_VDO1DL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path5",
+ .data = (void *)MDP_COMP_VDO0DL1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path6",
+ .data = (void *)MDP_COMP_VDO1DL1,
}, {
.compatible = "mediatek,mt8183-mdp3-dl1",
.data = (void *)MDP_COMP_CAMIN,
}, {
.compatible = "mediatek,mt8183-mdp3-dl2",
.data = (void *)MDP_COMP_CAMIN2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-dl1",
+ .data = (void *)MDP_COMP_CAMIN,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-dl2",
+ .data = (void *)MDP_COMP_CAMIN2,
},
{}
};
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
index 57f5ca3052ba..05a60771d4bc 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
@@ -93,12 +93,12 @@ enum mdp_comp_event {
WROT1_SOF,
WROT2_SOF,
WROT3_SOF,
- RDMA1_FRAME_DONE,
- RDMA2_FRAME_DONE,
- RDMA3_FRAME_DONE,
- WROT1_FRAME_DONE,
- WROT2_FRAME_DONE,
- WROT3_FRAME_DONE,
+ RDMA1_DONE,
+ RDMA2_DONE,
+ RDMA3_DONE,
+ WROT1_DONE,
+ WROT2_DONE,
+ WROT3_DONE,
ISP_P2_0_DONE,
ISP_P2_1_DONE,
@@ -159,6 +159,16 @@ struct mdp_comp_data {
struct mdp_mutex_info mutex;
};
+struct hyfbc_init_info {
+ bool is10b;
+ u32 width_in_mb;
+ u32 height_in_mb;
+ u32 w_stride_in_mb;
+ u32 h_stride_in_mb;
+ u32 byte_per_mb;
+ u32 pa_base;
+};
+
struct mdp_comp_ops;
struct mdp_comp {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index a646e99e410f..bef8da6fff1c 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -15,6 +15,7 @@
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
#include "mt8183_mdp.h"
+#include "mt8195_mdp.h"
static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_cfg = &mt8183_plat_cfg,
@@ -27,6 +28,18 @@ static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.format_len = ARRAY_SIZE(mt8183_formats),
};
+static const struct mtk_mdp_driver_data mt8195_mdp_driver_data = {
+ .mdp_cfg = &mt8195_plat_cfg,
+ .event = mt8195_mdp_event,
+ .event_len = ARRAY_SIZE(mt8195_mdp_event),
+ .comp_data = mt8195_mdp_comp_data,
+ .pipe_info = mt8195_pipe_info,
+ .pipe_info_len = ARRAY_SIZE(mt8195_pipe_info),
+ .format = mt8195_formats,
+ .format_len = ARRAY_SIZE(mt8195_formats),
+ .config_table = mt8195_mdp_mmsys_config_table,
+};
+
static const struct of_device_id mdp_of_ids[] = {
{ .compatible = "mediatek,mt8183-mdp3",
.data = &mt8183_mdp_driver_data,
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index 119af7666b59..c668e317f947 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -28,8 +28,19 @@ struct mdp_platform_config {
bool rdma_support_10bit;
bool rdma_rsz1_sram_sharing;
bool rdma_upsample_repeat_only;
+ bool rdma_support_extend_ufo;
+ bool rdma_support_hyfbc;
+ bool rdma_support_afbc;
+ bool rdma_esl_setting;
bool rsz_disable_dcm_small_sample;
+ bool rsz_etc_control;
+ bool tdshp_1_1;
bool wrot_filter_constraint;
+ bool wrot_support_afbc;
+ bool wrot_support_10bit;
+ bool mdp_version_6885;
+ bool mdp_version_8195;
+ u8 tdshp_dyn_contrast_version;
u32 gce_event_offset;
bool support_multi_larb;
};
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 0fdc1b228227..4a25f86bfaa5 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -51,6 +51,73 @@
enum mdp_color {
MDP_COLOR_UNKNOWN = 0,
+ //MDP_COLOR_FULLG8,
+ MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8 = MDP_COLOR_FULLG8_BGGR,
+
+ //MDP_COLOR_FULLG10,
+ MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10 = MDP_COLOR_FULLG10_BGGR,
+
+ //MDP_COLOR_FULLG12,
+ MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12 = MDP_COLOR_FULLG12_BGGR,
+
+ //MDP_COLOR_FULLG14,
+ MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14 = MDP_COLOR_FULLG14_BGGR,
+
+ MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 24),
+
+ //MDP_COLOR_BAYER8,
+ MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8 = MDP_COLOR_BAYER8_BGGR,
+
+ //MDP_COLOR_BAYER10,
+ MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10 = MDP_COLOR_BAYER10_BGGR,
+
+ //MDP_COLOR_BAYER12,
+ MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12 = MDP_COLOR_BAYER12_BGGR,
+
+ //MDP_COLOR_BAYER14,
+ MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14 = MDP_COLOR_BAYER14_BGGR,
+
+ MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 48, 0, 0, 23),
+ /* For bayer+mono raw-16 */
+ MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 2, 0, 0),
+
+ MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 22),
+ MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 22),
+ MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 22),
+ MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 22),
+
// Unified format
MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 07/14] media: platform: mtk-mdp3: Add platform configuration for MT8195
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add platform configuration for MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mt8195_mdp.h | 682 ++++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 144 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 22 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 13 +
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 11 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 67 ++
6 files changed, 933 insertions(+), 6 deletions(-)
create mode 100644 drivers/media/platform/mtk-mdp3/mt8195_mdp.h
diff --git a/drivers/media/platform/mtk-mdp3/mt8195_mdp.h b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
new file mode 100644
index 000000000000..f69bc86bcd1e
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
@@ -0,0 +1,682 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MT8195_MDP_H__
+#define __MT8195_MDP_H__
+
+static const struct mdp_platform_config mt8195_plat_cfg = {
+ .rdma_support_10bit = true,
+ .rdma_support_extend_ufo = true,
+ .rdma_support_hyfbc = true,
+ .rdma_support_afbc = true,
+ .rdma_esl_setting = true,
+ .rdma_rsz1_sram_sharing = false,
+ .rdma_upsample_repeat_only = false,
+ .rsz_disable_dcm_small_sample = false,
+ .rsz_etc_control = true,
+ .wrot_filter_constraint = false,
+ .tdshp_1_1 = true,
+ .tdshp_dyn_contrast_version = 2,
+ .mdp_version_8195 = true,
+ .mdp_version_6885 = true,
+ .gce_event_offset = 0,
+ .support_multi_larb = true,
+};
+
+enum mt8195_mdp_comp_id {
+ /* MT8195 Comp id */
+ /* ISP */
+ MT8195_MDP_COMP_WPEI = 0,
+ MT8195_MDP_COMP_WPEO, /* 1 */
+ MT8195_MDP_COMP_WPEI2, /* 2 */
+ MT8195_MDP_COMP_WPEO2, /* 3 */
+
+ /* MDP */
+ MT8195_MDP_COMP_CAMIN, /* 4 */
+ MT8195_MDP_COMP_CAMIN2, /* 5 */
+ MT8195_MDP_COMP_SPLIT, /* 6 */
+ MT8195_MDP_COMP_SPLIT2, /* 7 */
+ MT8195_MDP_COMP_RDMA0, /* 8 */
+ MT8195_MDP_COMP_RDMA1, /* 9 */
+ MT8195_MDP_COMP_RDMA2, /* 10 */
+ MT8195_MDP_COMP_RDMA3, /* 11 */
+ MT8195_MDP_COMP_STITCH, /* 12 */
+ MT8195_MDP_COMP_FG0, /* 13 */
+ MT8195_MDP_COMP_FG1, /* 14 */
+ MT8195_MDP_COMP_FG2, /* 15 */
+ MT8195_MDP_COMP_FG3, /* 16 */
+ MT8195_MDP_COMP_TO_SVPP2MOUT, /* 17 */
+ MT8195_MDP_COMP_TO_SVPP3MOUT, /* 18 */
+ MT8195_MDP_COMP_TO_WARP0MOUT, /* 19 */
+ MT8195_MDP_COMP_TO_WARP1MOUT, /* 20 */
+ MT8195_MDP_COMP_VPP0_SOUT, /* 21 */
+ MT8195_MDP_COMP_VPP1_SOUT, /* 22 */
+ MT8195_MDP_COMP_PQ0_SOUT, /* 23 */
+ MT8195_MDP_COMP_PQ1_SOUT, /* 24 */
+ MT8195_MDP_COMP_HDR0, /* 25 */
+ MT8195_MDP_COMP_HDR1, /* 26 */
+ MT8195_MDP_COMP_HDR2, /* 27 */
+ MT8195_MDP_COMP_HDR3, /* 28 */
+ MT8195_MDP_COMP_AAL0, /* 29 */
+ MT8195_MDP_COMP_AAL1, /* 30 */
+ MT8195_MDP_COMP_AAL2, /* 31 */
+ MT8195_MDP_COMP_AAL3, /* 32 */
+ MT8195_MDP_COMP_RSZ0, /* 33 */
+ MT8195_MDP_COMP_RSZ1, /* 34 */
+ MT8195_MDP_COMP_RSZ2, /* 35 */
+ MT8195_MDP_COMP_RSZ3, /* 36 */
+ MT8195_MDP_COMP_TDSHP0, /* 37 */
+ MT8195_MDP_COMP_TDSHP1, /* 38 */
+ MT8195_MDP_COMP_TDSHP2, /* 39 */
+ MT8195_MDP_COMP_TDSHP3, /* 40 */
+ MT8195_MDP_COMP_COLOR0, /* 41 */
+ MT8195_MDP_COMP_COLOR1, /* 42 */
+ MT8195_MDP_COMP_COLOR2, /* 43 */
+ MT8195_MDP_COMP_COLOR3, /* 44 */
+ MT8195_MDP_COMP_OVL0, /* 45 */
+ MT8195_MDP_COMP_OVL1, /* 46 */
+ MT8195_MDP_COMP_PAD0, /* 47 */
+ MT8195_MDP_COMP_PAD1, /* 48 */
+ MT8195_MDP_COMP_PAD2, /* 49 */
+ MT8195_MDP_COMP_PAD3, /* 50 */
+ MT8195_MDP_COMP_TCC0, /* 51 */
+ MT8195_MDP_COMP_TCC1, /* 52 */
+ MT8195_MDP_COMP_WROT0, /* 53 */
+ MT8195_MDP_COMP_WROT1, /* 54 */
+ MT8195_MDP_COMP_WROT2, /* 55 */
+ MT8195_MDP_COMP_WROT3, /* 56 */
+ MT8195_MDP_COMP_MERGE2, /* 57 */
+ MT8195_MDP_COMP_MERGE3, /* 58 */
+
+ MT8195_MDP_COMP_VDO0DL0, /* 59 */
+ MT8195_MDP_COMP_VDO1DL0, /* 60 */
+ MT8195_MDP_COMP_VDO0DL1, /* 61 */
+ MT8195_MDP_COMP_VDO1DL1, /* 62 */
+};
+
+static const struct mdp_comp_data mt8195_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_WPEI] = {
+ {MDP_COMP_TYPE_WPEI, 0, MT8195_MDP_COMP_WPEI},
+ {0, 0, 0},
+ {0, BIT(13), 0}
+ },
+ [MDP_COMP_WPEO] = {
+ {MDP_COMP_TYPE_EXTO, 2, MT8195_MDP_COMP_WPEO},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_WPEI2] = {
+ {MDP_COMP_TYPE_WPEI, 1, MT8195_MDP_COMP_WPEI2},
+ {0, 0, 0},
+ {0, BIT(14), 0}
+ },
+ [MDP_COMP_WPEO2] = {
+ {MDP_COMP_TYPE_EXTO, 3, MT8195_MDP_COMP_WPEO2},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN] = {
+ {MDP_COMP_TYPE_DL_PATH1, 0, MT8195_MDP_COMP_CAMIN},
+ {3, 3, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_CAMIN2] = {
+ {MDP_COMP_TYPE_DL_PATH2, 1, MT8195_MDP_COMP_CAMIN2},
+ {3, 6, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_SPLIT] = {
+ {MDP_COMP_TYPE_SPLIT, 0, MT8195_MDP_COMP_SPLIT},
+ {7, 0, 0},
+ {1, BIT(2), 0}
+ },
+ [MDP_COMP_SPLIT2] = {
+ {MDP_COMP_TYPE_SPLIT, 1, MT8195_MDP_COMP_SPLIT2},
+ {7, 0, 0},
+ {1, BIT(2), 0}
+ },
+ [MDP_COMP_RDMA0] = {
+ {MDP_COMP_TYPE_RDMA, 0, MT8195_MDP_COMP_RDMA0},
+ {3, 0, 0},
+ {0, BIT(0), 0}
+ },
+ [MDP_COMP_RDMA1] = {
+ {MDP_COMP_TYPE_RDMA, 1, MT8195_MDP_COMP_RDMA1},
+ {3, 0, 0},
+ {1, BIT(4), 0}
+ },
+ [MDP_COMP_RDMA2] = {
+ {MDP_COMP_TYPE_RDMA, 2, MT8195_MDP_COMP_RDMA2},
+ {3, 0, 0},
+ {1, BIT(5), 0}
+ },
+ [MDP_COMP_RDMA3] = {
+ {MDP_COMP_TYPE_RDMA, 3, MT8195_MDP_COMP_RDMA3},
+ {3, 0, 0},
+ {1, BIT(6), 0}
+ },
+ [MDP_COMP_STITCH] = {
+ {MDP_COMP_TYPE_STITCH, 0, MT8195_MDP_COMP_STITCH},
+ {1, 0, 0},
+ {0, BIT(2), 0}
+ },
+ [MDP_COMP_FG0] = {
+ {MDP_COMP_TYPE_FG, 0, MT8195_MDP_COMP_FG0},
+ {1, 0, 0},
+ {0, BIT(1), 0}
+ },
+ [MDP_COMP_FG1] = {
+ {MDP_COMP_TYPE_FG, 1, MT8195_MDP_COMP_FG1},
+ {1, 0, 0},
+ {1, BIT(7), 0}
+ },
+ [MDP_COMP_FG2] = {
+ {MDP_COMP_TYPE_FG, 2, MT8195_MDP_COMP_FG2},
+ {1, 0, 0},
+ {1, BIT(8), 0}
+ },
+ [MDP_COMP_FG3] = {
+ {MDP_COMP_TYPE_FG, 3, MT8195_MDP_COMP_FG3},
+ {1, 0, 0},
+ {1, BIT(9), 0}
+ },
+ [MDP_COMP_HDR0] = {
+ {MDP_COMP_TYPE_HDR, 0, MT8195_MDP_COMP_HDR0},
+ {1, 0, 0},
+ {0, BIT(3), 0}
+ },
+ [MDP_COMP_HDR1] = {
+ {MDP_COMP_TYPE_HDR, 1, MT8195_MDP_COMP_HDR1},
+ {1, 0, 0},
+ {1, BIT(10), 0}
+ },
+ [MDP_COMP_HDR2] = {
+ {MDP_COMP_TYPE_HDR, 2, MT8195_MDP_COMP_HDR2},
+ {1, 0, 0},
+ {1, BIT(11), 0}
+ },
+ [MDP_COMP_HDR3] = {
+ {MDP_COMP_TYPE_HDR, 3, MT8195_MDP_COMP_HDR3},
+ {1, 0, 0},
+ {1, BIT(12), 0}
+ },
+ [MDP_COMP_AAL0] = {
+ {MDP_COMP_TYPE_AAL, 0, MT8195_MDP_COMP_AAL0},
+ {1, 0, 0},
+ {0, BIT(4), 0}
+ },
+ [MDP_COMP_AAL1] = {
+ {MDP_COMP_TYPE_AAL, 1, MT8195_MDP_COMP_AAL1},
+ {1, 0, 0},
+ {1, BIT(13), 0}
+ },
+ [MDP_COMP_AAL2] = {
+ {MDP_COMP_TYPE_AAL, 2, MT8195_MDP_COMP_AAL2},
+ {1, 0, 0},
+ {1, BIT(14), 0}
+ },
+ [MDP_COMP_AAL3] = {
+ {MDP_COMP_TYPE_AAL, 3, MT8195_MDP_COMP_AAL3},
+ {1, 0, 0},
+ {1, BIT(15), 0}
+ },
+ [MDP_COMP_RSZ0] = {
+ {MDP_COMP_TYPE_RSZ, 0, MT8195_MDP_COMP_RSZ0},
+ {1, 0, 0},
+ {0, BIT(5), 0}
+ },
+ [MDP_COMP_RSZ1] = {
+ {MDP_COMP_TYPE_RSZ, 1, MT8195_MDP_COMP_RSZ1},
+ {1, 0, 0},
+ {1, BIT(16), 0}
+ },
+ [MDP_COMP_RSZ2] = {
+ {MDP_COMP_TYPE_RSZ, 2, MT8195_MDP_COMP_RSZ2},
+ {2, 0, 0},
+ {1, BIT(17) | BIT(22), 0}
+ },
+ [MDP_COMP_RSZ3] = {
+ {MDP_COMP_TYPE_RSZ, 3, MT8195_MDP_COMP_RSZ3},
+ {2, 0, 0},
+ {1, BIT(18) | BIT(23), 0}
+ },
+ [MDP_COMP_TDSHP0] = {
+ {MDP_COMP_TYPE_TDSHP, 0, MT8195_MDP_COMP_TDSHP0},
+ {1, 0, 0},
+ {0, BIT(6), 0}
+ },
+ [MDP_COMP_TDSHP1] = {
+ {MDP_COMP_TYPE_TDSHP, 1, MT8195_MDP_COMP_TDSHP1},
+ {1, 0, 0},
+ {1, BIT(19), 0}
+ },
+ [MDP_COMP_TDSHP2] = {
+ {MDP_COMP_TYPE_TDSHP, 2, MT8195_MDP_COMP_TDSHP2},
+ {1, 0, 0},
+ {1, BIT(20), 0}
+ },
+ [MDP_COMP_TDSHP3] = {
+ {MDP_COMP_TYPE_TDSHP, 3, MT8195_MDP_COMP_TDSHP3},
+ {1, 0, 0},
+ {1, BIT(21), 0}
+ },
+ [MDP_COMP_COLOR0] = {
+ {MDP_COMP_TYPE_COLOR, 0, MT8195_MDP_COMP_COLOR0},
+ {1, 0, 0},
+ {0, BIT(7), 0}
+ },
+ [MDP_COMP_COLOR1] = {
+ {MDP_COMP_TYPE_COLOR, 1, MT8195_MDP_COMP_COLOR1},
+ {1, 0, 0},
+ {1, BIT(24), 0}
+ },
+ [MDP_COMP_COLOR2] = {
+ {MDP_COMP_TYPE_COLOR, 2, MT8195_MDP_COMP_COLOR2},
+ {1, 0, 0},
+ {1, BIT(25), 0}
+ },
+ [MDP_COMP_COLOR3] = {
+ {MDP_COMP_TYPE_COLOR, 3, MT8195_MDP_COMP_COLOR3},
+ {1, 0, 0},
+ {1, BIT(26), 0}
+ },
+ [MDP_COMP_OVL0] = {
+ {MDP_COMP_TYPE_OVL, 0, MT8195_MDP_COMP_OVL0},
+ {1, 0, 0},
+ {0, BIT(8), 0}
+ },
+ [MDP_COMP_OVL1] = {
+ {MDP_COMP_TYPE_OVL, 1, MT8195_MDP_COMP_OVL1},
+ {1, 0, 0},
+ {1, BIT(27), 0}
+ },
+ [MDP_COMP_PAD0] = {
+ {MDP_COMP_TYPE_PAD, 0, MT8195_MDP_COMP_PAD0},
+ {1, 0, 0},
+ {0, BIT(9), 0}
+ },
+ [MDP_COMP_PAD1] = {
+ {MDP_COMP_TYPE_PAD, 1, MT8195_MDP_COMP_PAD1},
+ {1, 0, 0},
+ {1, BIT(28), 0}
+ },
+ [MDP_COMP_PAD2] = {
+ {MDP_COMP_TYPE_PAD, 2, MT8195_MDP_COMP_PAD2},
+ {1, 0, 0},
+ {1, BIT(29), 0}
+ },
+ [MDP_COMP_PAD3] = {
+ {MDP_COMP_TYPE_PAD, 3, MT8195_MDP_COMP_PAD3},
+ {1, 0, 0},
+ {1, BIT(30), 0}
+ },
+ [MDP_COMP_TCC0] = {
+ {MDP_COMP_TYPE_TCC, 0, MT8195_MDP_COMP_TCC0},
+ {1, 0, 0},
+ {0, BIT(10), 0}
+ },
+ [MDP_COMP_TCC1] = {
+ {MDP_COMP_TYPE_TCC, 1, MT8195_MDP_COMP_TCC1},
+ {1, 0, 0},
+ {1, BIT(3), 0}
+ },
+ [MDP_COMP_WROT0] = {
+ {MDP_COMP_TYPE_WROT, 0, MT8195_MDP_COMP_WROT0},
+ {1, 0, 0},
+ {0, BIT(11), 0}
+ },
+ [MDP_COMP_WROT1] = {
+ {MDP_COMP_TYPE_WROT, 1, MT8195_MDP_COMP_WROT1},
+ {1, 0, 0},
+ {1, BIT(31), 0}
+ },
+ [MDP_COMP_WROT2] = {
+ {MDP_COMP_TYPE_WROT, 2, MT8195_MDP_COMP_WROT2},
+ {1, 0, 0},
+ {1, 0, BIT(0)}
+ },
+ [MDP_COMP_WROT3] = {
+ {MDP_COMP_TYPE_WROT, 3, MT8195_MDP_COMP_WROT3},
+ {1, 0, 0},
+ {1, 0, BIT(1)}
+ },
+ [MDP_COMP_MERGE2] = {
+ {MDP_COMP_TYPE_MERGE, 2, MT8195_MDP_COMP_MERGE2},
+ {1, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_MERGE3] = {
+ {MDP_COMP_TYPE_MERGE, 3, MT8195_MDP_COMP_MERGE2},
+ {1, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_PQ0_SOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 0, MT8195_MDP_COMP_PQ0_SOUT},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_PQ1_SOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 1, MT8195_MDP_COMP_PQ1_SOUT},
+ {0, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_TO_WARP0MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 2, MT8195_MDP_COMP_TO_WARP0MOUT},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_TO_WARP1MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 3, MT8195_MDP_COMP_TO_WARP1MOUT},
+ {0, 0, 0},
+ {0, 0, 0}
+ },
+ [MDP_COMP_TO_SVPP2MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 4, MT8195_MDP_COMP_TO_SVPP2MOUT},
+ {0, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_TO_SVPP3MOUT] = {
+ {MDP_COMP_TYPE_DUMMY, 5, MT8195_MDP_COMP_TO_SVPP3MOUT},
+ {0, 0, 0},
+ {1, 0, 0}
+ },
+ [MDP_COMP_VPP0_SOUT] = {
+ {MDP_COMP_TYPE_PATH1, 0, MT8195_MDP_COMP_VPP0_SOUT},
+ {4, 9, 0},
+ {0, BIT(15), BIT(2)}
+ },
+ [MDP_COMP_VPP1_SOUT] = {
+ {MDP_COMP_TYPE_PATH2, 1, MT8195_MDP_COMP_VPP1_SOUT},
+ {2, 13, 0},
+ {1, BIT(16), BIT(3)}
+ },
+ [MDP_COMP_VDO0DL0] = {
+ {MDP_COMP_TYPE_DL_PATH3, 0, MT8195_MDP_COMP_VDO0DL0},
+ {1, 15, 0},
+ {1, 0, BIT(4)}
+ },
+ [MDP_COMP_VDO1DL0] = {
+ {MDP_COMP_TYPE_DL_PATH4, 0, MT8195_MDP_COMP_VDO1DL0},
+ {1, 17, 0},
+ {1, 0, BIT(6)}
+ },
+ [MDP_COMP_VDO0DL1] = {
+ {MDP_COMP_TYPE_DL_PATH5, 0, MT8195_MDP_COMP_VDO0DL1},
+ {1, 18, 0},
+ {1, 0, BIT(5)}
+ },
+ [MDP_COMP_VDO1DL1] = {
+ {MDP_COMP_TYPE_DL_PATH6, 0, MT8195_MDP_COMP_VDO1DL1},
+ {1, 16, 0},
+ {1, 0, BIT(7)}
+ },
+};
+
+static const enum mdp_comp_event mt8195_mdp_event[] = {
+ RDMA0_SOF,
+ WROT0_SOF,
+ RDMA0_DONE,
+ WROT0_DONE,
+ RDMA1_SOF,
+ RDMA2_SOF,
+ RDMA3_SOF,
+ WROT1_SOF,
+ WROT2_SOF,
+ WROT3_SOF,
+ RDMA1_DONE,
+ RDMA2_DONE,
+ RDMA3_DONE,
+ WROT1_DONE,
+ WROT2_DONE,
+ WROT3_DONE
+};
+
+static const struct mdp_pipe_info mt8195_pipe_info[] = {
+ {MDP_PIPE_WPEI, 0, 0},
+ {MDP_PIPE_WPEI2, 0, 1},
+ {MDP_PIPE_RDMA0, 0, 2},
+ {MDP_PIPE_VPP1_SOUT, 0, 3},
+ {MDP_PIPE_SPLIT, 1, 2, 0x387},
+ {MDP_PIPE_SPLIT2, 1, 3, 0x387},
+ {MDP_PIPE_RDMA1, 1, 1},
+ {MDP_PIPE_RDMA2, 1, 2},
+ {MDP_PIPE_RDMA3, 1, 3},
+ {MDP_PIPE_VPP0_SOUT, 1, 4},
+};
+
+static const struct mdp_format mt8195_formats[] = {
+ {
+ .pixelformat = V4L2_PIX_FMT_GREY,
+ .mdp_color = MDP_COLOR_GREY,
+ .depth = { 8 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565X,
+ .mdp_color = MDP_COLOR_RGB565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565,
+ .mdp_color = MDP_COLOR_BGR565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB24,
+ .mdp_color = MDP_COLOR_RGB888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_BGR24,
+ .mdp_color = MDP_COLOR_BGR888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ABGR32,
+ .mdp_color = MDP_COLOR_BGRA8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ARGB32,
+ .mdp_color = MDP_COLOR_ARGB8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_UYVY,
+ .mdp_color = MDP_COLOR_UYVY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_VYUY,
+ .mdp_color = MDP_COLOR_VYUY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .mdp_color = MDP_COLOR_YUYV,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVYU,
+ .mdp_color = MDP_COLOR_YVYU,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV24,
+ .mdp_color = MDP_COLOR_NV24,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV42,
+ .mdp_color = MDP_COLOR_NV42,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MT21C,
+ .mdp_color = MDP_COLOR_NV12_HYFBC,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 1,
+ .walign = 4,
+ .halign = 4,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MM21,
+ .mdp_color = MDP_COLOR_420_BLKP,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12M,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21M,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16M,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61M,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420M,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420M,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }
+};
+
+static const u32 mt8195_mdp_mmsys_config_table[] = {
+ [CONFIG_VPP0_HW_DCM_1ST_DIS0] = 0,
+ [CONFIG_VPP0_DL_IRELAY_WR] = 1,
+ [CONFIG_VPP1_HW_DCM_1ST_DIS0] = 2,
+ [CONFIG_VPP1_HW_DCM_1ST_DIS1] = 3,
+ [CONFIG_VPP1_HW_DCM_2ND_DIS0] = 4,
+ [CONFIG_VPP1_HW_DCM_2ND_DIS1] = 5,
+ [CONFIG_SVPP2_BUF_BF_RSZ_SWITCH] = 6,
+ [CONFIG_SVPP3_BUF_BF_RSZ_SWITCH] = 7,
+};
+
+#endif // __MT8195_MDP_H__
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index 9073ddc19775..fdf072e48238 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -919,6 +919,126 @@ static const struct of_device_id mdp_comp_dt_ids[] = {
}, {
.compatible = "mediatek,mt8183-mdp3-wdma",
.data = (void *)MDP_COMP_WDMA,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rdma1",
+ .data = (void *)MDP_COMP_RDMA1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rdma2",
+ .data = (void *)MDP_COMP_RDMA2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rdma3",
+ .data = (void *)MDP_COMP_RDMA3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-wrot1",
+ .data = (void *)MDP_COMP_WROT1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-wrot2",
+ .data = (void *)MDP_COMP_WROT2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-wrot3",
+ .data = (void *)MDP_COMP_WROT3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-split",
+ .data = (void *)MDP_COMP_SPLIT,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-stitch",
+ .data = (void *)MDP_COMP_STITCH,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg0",
+ .data = (void *)MDP_COMP_FG0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg1",
+ .data = (void *)MDP_COMP_FG1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg2",
+ .data = (void *)MDP_COMP_FG2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-fg3",
+ .data = (void *)MDP_COMP_FG3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr0",
+ .data = (void *)MDP_COMP_HDR0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr1",
+ .data = (void *)MDP_COMP_HDR1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr2",
+ .data = (void *)MDP_COMP_HDR2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-hdr3",
+ .data = (void *)MDP_COMP_HDR3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal0",
+ .data = (void *)MDP_COMP_AAL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal1",
+ .data = (void *)MDP_COMP_AAL1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal2",
+ .data = (void *)MDP_COMP_AAL2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-aal3",
+ .data = (void *)MDP_COMP_AAL3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rsz2",
+ .data = (void *)MDP_COMP_RSZ2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-rsz3",
+ .data = (void *)MDP_COMP_RSZ3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-merge2",
+ .data = (void *)MDP_COMP_MERGE2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-merge3",
+ .data = (void *)MDP_COMP_MERGE3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp0",
+ .data = (void *)MDP_COMP_TDSHP0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp1",
+ .data = (void *)MDP_COMP_TDSHP1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp2",
+ .data = (void *)MDP_COMP_TDSHP2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tdshp3",
+ .data = (void *)MDP_COMP_TDSHP3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color0",
+ .data = (void *)MDP_COMP_COLOR0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color1",
+ .data = (void *)MDP_COMP_COLOR1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color2",
+ .data = (void *)MDP_COMP_COLOR2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-color3",
+ .data = (void *)MDP_COMP_COLOR3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-ovl0",
+ .data = (void *)MDP_COMP_OVL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-ovl1",
+ .data = (void *)MDP_COMP_OVL1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad0",
+ .data = (void *)MDP_COMP_PAD0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad1",
+ .data = (void *)MDP_COMP_PAD1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad2",
+ .data = (void *)MDP_COMP_PAD2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-pad3",
+ .data = (void *)MDP_COMP_PAD3,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tcc0",
+ .data = (void *)MDP_COMP_TCC0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-tcc1",
+ .data = (void *)MDP_COMP_TCC1,
},
{}
};
@@ -936,12 +1056,36 @@ static const struct of_device_id mdp_sub_comp_dt_ids[] = {
}, {
.compatible = "mediatek,mt8183-mdp3-exto",
.data = (void *)MDP_COMP_ISP_IMGO,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path1",
+ .data = (void *)MDP_COMP_VPP0_SOUT,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path2",
+ .data = (void *)MDP_COMP_VPP1_SOUT,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path3",
+ .data = (void *)MDP_COMP_VDO0DL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path4",
+ .data = (void *)MDP_COMP_VDO1DL0,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path5",
+ .data = (void *)MDP_COMP_VDO0DL1,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-path6",
+ .data = (void *)MDP_COMP_VDO1DL1,
}, {
.compatible = "mediatek,mt8183-mdp3-dl1",
.data = (void *)MDP_COMP_CAMIN,
}, {
.compatible = "mediatek,mt8183-mdp3-dl2",
.data = (void *)MDP_COMP_CAMIN2,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-dl1",
+ .data = (void *)MDP_COMP_CAMIN,
+ }, {
+ .compatible = "mediatek,mt8195-mdp3-dl2",
+ .data = (void *)MDP_COMP_CAMIN2,
},
{}
};
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
index 57f5ca3052ba..05a60771d4bc 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
@@ -93,12 +93,12 @@ enum mdp_comp_event {
WROT1_SOF,
WROT2_SOF,
WROT3_SOF,
- RDMA1_FRAME_DONE,
- RDMA2_FRAME_DONE,
- RDMA3_FRAME_DONE,
- WROT1_FRAME_DONE,
- WROT2_FRAME_DONE,
- WROT3_FRAME_DONE,
+ RDMA1_DONE,
+ RDMA2_DONE,
+ RDMA3_DONE,
+ WROT1_DONE,
+ WROT2_DONE,
+ WROT3_DONE,
ISP_P2_0_DONE,
ISP_P2_1_DONE,
@@ -159,6 +159,16 @@ struct mdp_comp_data {
struct mdp_mutex_info mutex;
};
+struct hyfbc_init_info {
+ bool is10b;
+ u32 width_in_mb;
+ u32 height_in_mb;
+ u32 w_stride_in_mb;
+ u32 h_stride_in_mb;
+ u32 byte_per_mb;
+ u32 pa_base;
+};
+
struct mdp_comp_ops;
struct mdp_comp {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index a646e99e410f..bef8da6fff1c 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -15,6 +15,7 @@
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
#include "mt8183_mdp.h"
+#include "mt8195_mdp.h"
static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_cfg = &mt8183_plat_cfg,
@@ -27,6 +28,18 @@ static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.format_len = ARRAY_SIZE(mt8183_formats),
};
+static const struct mtk_mdp_driver_data mt8195_mdp_driver_data = {
+ .mdp_cfg = &mt8195_plat_cfg,
+ .event = mt8195_mdp_event,
+ .event_len = ARRAY_SIZE(mt8195_mdp_event),
+ .comp_data = mt8195_mdp_comp_data,
+ .pipe_info = mt8195_pipe_info,
+ .pipe_info_len = ARRAY_SIZE(mt8195_pipe_info),
+ .format = mt8195_formats,
+ .format_len = ARRAY_SIZE(mt8195_formats),
+ .config_table = mt8195_mdp_mmsys_config_table,
+};
+
static const struct of_device_id mdp_of_ids[] = {
{ .compatible = "mediatek,mt8183-mdp3",
.data = &mt8183_mdp_driver_data,
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index 119af7666b59..c668e317f947 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -28,8 +28,19 @@ struct mdp_platform_config {
bool rdma_support_10bit;
bool rdma_rsz1_sram_sharing;
bool rdma_upsample_repeat_only;
+ bool rdma_support_extend_ufo;
+ bool rdma_support_hyfbc;
+ bool rdma_support_afbc;
+ bool rdma_esl_setting;
bool rsz_disable_dcm_small_sample;
+ bool rsz_etc_control;
+ bool tdshp_1_1;
bool wrot_filter_constraint;
+ bool wrot_support_afbc;
+ bool wrot_support_10bit;
+ bool mdp_version_6885;
+ bool mdp_version_8195;
+ u8 tdshp_dyn_contrast_version;
u32 gce_event_offset;
bool support_multi_larb;
};
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 0fdc1b228227..4a25f86bfaa5 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -51,6 +51,73 @@
enum mdp_color {
MDP_COLOR_UNKNOWN = 0,
+ //MDP_COLOR_FULLG8,
+ MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 8, 2, 0, 21),
+ MDP_COLOR_FULLG8 = MDP_COLOR_FULLG8_BGGR,
+
+ //MDP_COLOR_FULLG10,
+ MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 10, 2, 0, 21),
+ MDP_COLOR_FULLG10 = MDP_COLOR_FULLG10_BGGR,
+
+ //MDP_COLOR_FULLG12,
+ MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 12, 2, 0, 21),
+ MDP_COLOR_FULLG12 = MDP_COLOR_FULLG12_BGGR,
+
+ //MDP_COLOR_FULLG14,
+ MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 14, 2, 0, 21),
+ MDP_COLOR_FULLG14 = MDP_COLOR_FULLG14_BGGR,
+
+ MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 24),
+
+ //MDP_COLOR_BAYER8,
+ MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 8, 2, 0, 20),
+ MDP_COLOR_BAYER8 = MDP_COLOR_BAYER8_BGGR,
+
+ //MDP_COLOR_BAYER10,
+ MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 10, 2, 0, 20),
+ MDP_COLOR_BAYER10 = MDP_COLOR_BAYER10_BGGR,
+
+ //MDP_COLOR_BAYER12,
+ MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 12, 2, 0, 20),
+ MDP_COLOR_BAYER12 = MDP_COLOR_BAYER12_BGGR,
+
+ //MDP_COLOR_BAYER14,
+ MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 14, 2, 0, 20),
+ MDP_COLOR_BAYER14 = MDP_COLOR_BAYER14_BGGR,
+
+ MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 48, 0, 0, 23),
+ /* For bayer+mono raw-16 */
+ MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 2, 0, 0),
+
+ MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 22),
+ MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 22),
+ MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 22),
+ MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 22),
+
// Unified format
MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 08/14] media: platform: mtk-mdp3: Add engine setting for MT8195
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add engine setting and related header files for MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mdp_reg_aal.h | 24 +
.../media/platform/mtk-mdp3/mdp_reg_color.h | 29 +
drivers/media/platform/mtk-mdp3/mdp_reg_fg.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h | 31 +
.../media/platform/mtk-mdp3/mdp_reg_merge.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h | 24 +
drivers/media/platform/mtk-mdp3/mdp_reg_pad.h | 20 +
.../media/platform/mtk-mdp3/mdp_reg_rdma.h | 31 +
drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 2 +
.../media/platform/mtk-mdp3/mdp_reg_tdshp.h | 116 +++
.../media/platform/mtk-mdp3/mdp_reg_wrot.h | 18 +
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 705 +++++++++++++++++-
12 files changed, 1033 insertions(+), 13 deletions(-)
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_color.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h b/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
new file mode 100644
index 000000000000..2275a06fbdf9
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_AAL_H__
+#define __MDP_REG_AAL_H__
+
+#define MDP_AAL_EN (0x000)
+#define MDP_AAL_CFG (0x020)
+#define MDP_AAL_SIZE (0x030)
+#define MDP_AAL_OUTPUT_SIZE (0x034)
+#define MDP_AAL_OUTPUT_OFFSET (0x038)
+#define MDP_AAL_CFG_MAIN (0x200)
+
+#define MDP_AAL_EN_MASK (0x01)
+#define MDP_AAL_CFG_MASK (0x70FF00B3)
+#define MDP_AAL_SIZE_MASK (0x1FFF1FFF)
+#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF)
+#define MDP_AAL_CFG_MAIN_MASK (0x0FE)
+
+#endif // __MDP_REG_AAL_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_color.h b/drivers/media/platform/mtk-mdp3/mdp_reg_color.h
new file mode 100644
index 000000000000..54d917a20362
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_color.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_COLOR_H__
+#define __MDP_REG_COLOR_H__
+
+#define DISP_COLOR_WIN_X_MAIN (0x40C)
+#define DISP_COLOR_WIN_Y_MAIN (0x410)
+#define DISP_COLOR_START (0xC00)
+#define DISP_COLOR_INTEN (0xC04)
+#define DISP_COLOR_OUT_SEL (0xC0C)
+#define DISP_COLOR_INTERNAL_IP_WIDTH (0xC50)
+#define DISP_COLOR_INTERNAL_IP_HEIGHT (0xC54)
+#define DISP_COLOR_CM1_EN (0xC60)
+#define DISP_COLOR_CM2_EN (0xCA0)
+// MASK
+#define DISP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF)
+#define DISP_COLOR_WIN_Y_MAIN_MASK (0xFFFFFFFF)
+#define DISP_COLOR_START_MASK (0x0FF013F)
+#define DISP_COLOR_INTEN_MASK (0x07)
+#define DISP_COLOR_OUT_SEL_MASK (0x0777)
+#define DISP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF)
+#define DISP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF)
+#define DISP_COLOR_CM1_EN_MASK (0x03)
+#define DISP_COLOR_CM2_EN_MASK (0x017)
+#endif // __MDP_REG_COLOR_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h b/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
new file mode 100644
index 000000000000..34f68554c0bb
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_FG_H__
+#define __MDP_REG_FG_H__
+
+#define MDP_FG_TRIGGER (0x0)
+#define MDP_FG_FG_CTRL_0 (0x20)
+#define MDP_FG_FG_CK_EN (0x24)
+#define MDP_FG_TILE_INFO_0 (0x418)
+#define MDP_FG_TILE_INFO_1 (0x41c)
+
+/* MASK */
+#define MDP_FG_TRIGGER_MASK (0x00000007)
+#define MDP_FG_FG_CTRL_0_MASK (0x00000033)
+#define MDP_FG_FG_CK_EN_MASK (0x0000000F)
+#define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF)
+#define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF)
+
+#endif //__MDP_REG_FG_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h b/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
new file mode 100644
index 000000000000..06d0d3a6a139
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_HDR_H__
+#define __MDP_REG_HDR_H__
+
+#define MDP_HDR_TOP (0x000)
+#define MDP_HDR_RELAY (0x004)
+#define MDP_HDR_SIZE_0 (0x014)
+#define MDP_HDR_SIZE_1 (0x018)
+#define MDP_HDR_SIZE_2 (0x01C)
+#define MDP_HDR_HIST_CTRL_0 (0x020)
+#define MDP_HDR_HIST_CTRL_1 (0x024)
+#define MDP_HDR_HIST_ADDR (0x0DC)
+#define MDP_HDR_TILE_POS (0x118)
+
+// MASK
+#define MDP_HDR_RELAY_MASK (0x01)
+#define MDP_HDR_TOP_MASK (0xFF0FEB6D)
+#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF)
+#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF)
+#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F)
+#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF)
+
+#endif // __MDP_REG_HDR_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h b/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
new file mode 100644
index 000000000000..d53d58d4ea05
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_MERGE_H__
+#define __MDP_REG_MERGE_H__
+
+#define VPP_MERGE_ENABLE (0x000)
+#define VPP_MERGE_CFG_0 (0x010)
+#define VPP_MERGE_CFG_4 (0x020)
+#define VPP_MERGE_CFG_12 (0x040)
+#define VPP_MERGE_CFG_24 (0x070)
+#define VPP_MERGE_CFG_25 (0x074)
+
+#define VPP_MERGE_ENABLE_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_0_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_4_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_12_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_24_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_25_MASK (0xFFFFFFFF)
+#endif
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h b/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
new file mode 100644
index 000000000000..35aa10c763bd
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_OVL_H__
+#define __MDP_REG_OVL_H__
+
+#define OVL_EN (0x00c)
+#define OVL_ROI_SIZE (0x020)
+#define OVL_DATAPATH_CON (0x024)
+#define OVL_SRC_CON (0x02c)
+#define OVL_L0_CON (0x030)
+#define OVL_L0_SRC_SIZE (0x038)
+
+#define OVL_DATAPATH_CON_MASK (0x0FFFFFFF)
+#define OVL_EN_MASK (0xB07D07B1)
+#define OVL_L0_CON_MASK (0xFFFFFFFF)
+#define OVL_L0_SRC_SIZE_MASK (0x1FFF1FFF)
+#define OVL_ROI_SIZE_MASK (0x1FFF1FFF)
+#define OVL_SRC_CON_MASK (0x0000031F)
+
+#endif //__MDP_REG_OVL_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h b/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
new file mode 100644
index 000000000000..f4d6d06a74be
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_PAD_H__
+#define __MDP_REG_PAD_H__
+
+#define VPP_PADDING0_PADDING_CON (0x000)
+#define VPP_PADDING0_PADDING_PIC_SIZE (0x004)
+#define VPP_PADDING0_W_PADDING_SIZE (0x008)
+#define VPP_PADDING0_H_PADDING_SIZE (0x00c)
+
+#define VPP_PADDING0_PADDING_CON_MASK (0x00000007)
+#define VPP_PADDING0_PADDING_PIC_SIZE_MASK (0xFFFFFFFF)
+#define VPP_PADDING0_W_PADDING_SIZE_MASK (0x1FFF1FFF)
+#define VPP_PADDING0_H_PADDING_SIZE_MASK (0x1FFF1FFF)
+
+#endif // __MDP_REG_PAD_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h b/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
index 59d9aae40be6..06dea03ae029 100644
--- a/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
@@ -12,12 +12,14 @@
#define MDP_RDMA_CON 0x020
#define MDP_RDMA_GMCIF_CON 0x028
#define MDP_RDMA_SRC_CON 0x030
+#define MDP_RDMA_COMP_CON 0x038
#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
#define MDP_RDMA_MF_SRC_SIZE 0x070
#define MDP_RDMA_MF_CLIP_SIZE 0x078
#define MDP_RDMA_MF_OFFSET_1 0x080
#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL 0x098
#define MDP_RDMA_SRC_END_0 0x100
#define MDP_RDMA_SRC_END_1 0x108
#define MDP_RDMA_SRC_END_2 0x110
@@ -25,7 +27,20 @@
#define MDP_RDMA_SRC_OFFSET_1 0x120
#define MDP_RDMA_SRC_OFFSET_2 0x128
#define MDP_RDMA_SRC_OFFSET_0_P 0x148
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
#define MDP_RDMA_TRANSFORM_0 0x200
+#define MDP_RDMA_DMABUF_CON_0 0x240
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248
+#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
#define MDP_RDMA_RESV_DUMMY_0 0x2a0
#define MDP_RDMA_MON_STA_1 0x408
#define MDP_RDMA_SRC_BASE_0 0xf00
@@ -40,12 +55,14 @@
#define MDP_RDMA_CON_MASK 0x00001110
#define MDP_RDMA_GMCIF_CON_MASK 0xfffb3771
#define MDP_RDMA_SRC_CON_MASK 0xf3ffffff
+#define MDP_RDMA_COMP_CON_MASK 0xffffc000
#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK 0x001fffff
#define MDP_RDMA_MF_SRC_SIZE_MASK 0x1fff1fff
#define MDP_RDMA_MF_CLIP_SIZE_MASK 0x1fff1fff
#define MDP_RDMA_MF_OFFSET_1_MASK 0x003f001f
#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL_MASK 0x007fffff
#define MDP_RDMA_SRC_END_0_MASK 0xffffffff
#define MDP_RDMA_SRC_END_1_MASK 0xffffffff
#define MDP_RDMA_SRC_END_2_MASK 0xffffffff
@@ -53,7 +70,21 @@
#define MDP_RDMA_SRC_OFFSET_1_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff
+#define MDP_RDMA_SRC_OFFSET_HP_MASK 0xffffffff
#define MDP_RDMA_TRANSFORM_0_MASK 0xff110777
+#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff
+
#define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff
#define MDP_RDMA_MON_STA_1_MASK 0xffffffff
#define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h b/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
index 051fdb020741..942fd4393eba 100644
--- a/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
@@ -20,6 +20,7 @@
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034
+#define RSZ_ETC_CONTROL 0x22c
/* MASK */
#define PRZ_ENABLE_MASK 0x00010001
@@ -35,5 +36,6 @@
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff
+#define RSZ_ETC_CONTROL_MASK 0xff770000
#endif // __MDP_REG_RSZ_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h b/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
new file mode 100644
index 000000000000..7907266ac7c7
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_TDSHP_H__
+#define __MDP_REG_TDSHP_H__
+
+#define MDP_HIST_CFG_00 (0x064)
+#define MDP_HIST_CFG_01 (0x068)
+#define MDP_TDSHP_CTRL (0x100)
+#define MDP_TDSHP_CFG (0x110)
+#define MDP_TDSHP_INPUT_SIZE (0x120)
+#define MDP_TDSHP_OUTPUT_OFFSET (0x124)
+#define MDP_TDSHP_OUTPUT_SIZE (0x128)
+#define MDP_LUMA_HIST_INIT_00 (0x200)
+#define MDP_LUMA_HIST_INIT_01 (0x204)
+#define MDP_LUMA_HIST_INIT_02 (0x208)
+#define MDP_LUMA_HIST_INIT_03 (0x20C)
+#define MDP_LUMA_HIST_INIT_04 (0x210)
+#define MDP_LUMA_HIST_INIT_05 (0x214)
+#define MDP_LUMA_HIST_INIT_06 (0x218)
+#define MDP_LUMA_HIST_INIT_07 (0x21C)
+#define MDP_LUMA_HIST_INIT_08 (0x220)
+#define MDP_LUMA_HIST_INIT_09 (0x224)
+#define MDP_LUMA_HIST_INIT_10 (0x228)
+#define MDP_LUMA_HIST_INIT_11 (0x22C)
+#define MDP_LUMA_HIST_INIT_12 (0x230)
+#define MDP_LUMA_HIST_INIT_13 (0x234)
+#define MDP_LUMA_HIST_INIT_14 (0x238)
+#define MDP_LUMA_HIST_INIT_15 (0x23C)
+#define MDP_LUMA_HIST_INIT_16 (0x240)
+#define MDP_LUMA_SUM_INIT (0x244)
+#define MDP_DC_TWO_D_W1_RESULT_INIT (0x260)
+#define MDP_CONTOUR_HIST_INIT_00 (0x398)
+#define MDP_CONTOUR_HIST_INIT_01 (0x39C)
+#define MDP_CONTOUR_HIST_INIT_02 (0x3A0)
+#define MDP_CONTOUR_HIST_INIT_03 (0x3A4)
+#define MDP_CONTOUR_HIST_INIT_04 (0x3A8)
+#define MDP_CONTOUR_HIST_INIT_05 (0x3AC)
+#define MDP_CONTOUR_HIST_INIT_06 (0x3B0)
+#define MDP_CONTOUR_HIST_INIT_07 (0x3B4)
+#define MDP_CONTOUR_HIST_INIT_08 (0x3B8)
+#define MDP_CONTOUR_HIST_INIT_09 (0x3BC)
+#define MDP_CONTOUR_HIST_INIT_10 (0x3C0)
+#define MDP_CONTOUR_HIST_INIT_11 (0x3C4)
+#define MDP_CONTOUR_HIST_INIT_12 (0x3C8)
+#define MDP_CONTOUR_HIST_INIT_13 (0x3CC)
+#define MDP_CONTOUR_HIST_INIT_14 (0x3D0)
+#define MDP_CONTOUR_HIST_INIT_15 (0x3D4)
+#define MDP_CONTOUR_HIST_INIT_16 (0x3D8)
+
+// MASK
+#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF)
+#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF)
+#define MDP_LUMA_HIST_00_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_01_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_02_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_03_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_04_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_05_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_06_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_07_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_08_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_09_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_10_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_11_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_12_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_13_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_14_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_15_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_16_MASK (0x07FFFFFF)
+#define MDP_TDSHP_CTRL_MASK (0x07)
+#define MDP_TDSHP_CFG_MASK (0x03F7)
+#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF)
+#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_LUMA_HIST_INIT_00_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_01_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_02_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_03_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_04_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_05_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_06_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_07_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_08_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_09_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_10_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_11_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_12_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_13_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_14_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_15_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_16_MASK (0x07FFFFFF)
+#define MDP_LUMA_SUM_INIT_MASK (0xFFFFFFFF)
+#define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF)
+#define MDP_CONTOUR_HIST_INIT_00_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_01_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_02_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_03_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_04_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_05_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_06_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_07_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_08_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_09_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_10_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_11_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_12_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_13_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_14_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_15_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_16_MASK (0x07FFFFFF)
+
+#endif // __MDP_REG_TDSHP_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h b/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
index 39b8785f89eb..81a7c46c1aef 100644
--- a/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
@@ -11,23 +11,32 @@
#define VIDO_MAIN_BUF_SIZE 0x008
#define VIDO_SOFT_RST 0x010
#define VIDO_SOFT_RST_STAT 0x014
+#define VIDO_INT 0x01c
#define VIDO_CROP_OFST 0x020
#define VIDO_TAR_SIZE 0x024
+#define VIDO_FRAME_SIZE 0x028
#define VIDO_OFST_ADDR 0x02c
#define VIDO_STRIDE 0x030
+#define VIDO_BKGD 0x034
#define VIDO_OFST_ADDR_C 0x038
#define VIDO_STRIDE_C 0x03c
+#define VIDO_CTRL_2 0x048
#define VIDO_DITHER 0x054
#define VIDO_STRIDE_V 0x06c
#define VIDO_OFST_ADDR_V 0x068
#define VIDO_RSV_1 0x070
+#define VIDO_DMA_PREULTRA 0x074
#define VIDO_IN_SIZE 0x078
#define VIDO_ROT_EN 0x07c
#define VIDO_FIFO_TEST 0x080
#define VIDO_MAT_CTRL 0x084
+#define VIDO_PVRIC 0x0d8
+#define VIDO_SCAN_10BIT 0x0dc
+#define VIDO_PENDING_ZERO 0x0e0
#define VIDO_BASE_ADDR 0xf00
#define VIDO_BASE_ADDR_C 0xf04
#define VIDO_BASE_ADDR_V 0xf08
+#define VIDO_AFBC_YUVTRANS 0xf2c
/* MASK */
#define VIDO_CTRL_MASK 0xf530711f
@@ -36,6 +45,7 @@
#define VIDO_SOFT_RST_STAT_MASK 0x00000001
#define VIDO_TAR_SIZE_MASK 0x1fff1fff
#define VIDO_CROP_OFST_MASK 0x1fff1fff
+#define VIDO_INT_MASK 0x00000007
#define VIDO_OFST_ADDR_MASK 0x0fffffff
#define VIDO_STRIDE_MASK 0x0000ffff
#define VIDO_OFST_ADDR_C_MASK 0x0fffffff
@@ -51,5 +61,13 @@
#define VIDO_BASE_ADDR_MASK 0xffffffff
#define VIDO_BASE_ADDR_C_MASK 0xffffffff
#define VIDO_BASE_ADDR_V_MASK 0xffffffff
+#define VIDO_DMA_PREULTRA_MASK 0x00ffffff
+#define VIDO_FRAME_SIZE_MASK 0xffffffff
+#define VIDO_BKGD_MASK 0xffffffff
+#define VIDO_CTRL_2_MASK 0x0000000f
+#define VIDO_PVRIC_MASK 0x00000003
+#define VIDO_SCAN_10BIT_MASK 0x0000000f
+#define VIDO_PENDING_ZERO_MASK 0x07ffffff
+#define VIDO_AFBC_YUVTRANS_MASK 0x00000001
#endif // __MDP_REG_WROT_H__
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index fdf072e48238..8ca9c7e325e1 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -15,6 +15,14 @@
#include "mdp_reg_rdma.h"
#include "mdp_reg_ccorr.h"
#include "mdp_reg_rsz.h"
+#include "mdp_reg_fg.h"
+#include "mdp_reg_aal.h"
+#include "mdp_reg_tdshp.h"
+#include "mdp_reg_hdr.h"
+#include "mdp_reg_color.h"
+#include "mdp_reg_ovl.h"
+#include "mdp_reg_pad.h"
+#include "mdp_reg_merge.h"
#include "mdp_reg_wrot.h"
#include "mdp_reg_wdma.h"
#include "mdp_reg_isp.h"
@@ -107,7 +115,10 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
{
const struct mdp_rdma_data *rdma = &ctx->param->rdma;
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ u32 width = ctx->input->buffer.format.width;
+ u32 height = ctx->input->buffer.format.height;
u32 colorformat = ctx->input->buffer.format.colorformat;
+ u32 write_mask = 0;
bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat);
bool en_ufo = MDP_COLOR_IS_UFP(colorformat);
phys_addr_t base = ctx->comp->reg_base;
@@ -132,7 +143,7 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, rdma->src_ctrl,
0x03C8FE0F);
- if (mdp_cfg)
+ if (mdp_cfg) {
if (mdp_cfg->rdma_support_10bit && en_ufo) {
/* Setup source buffer base */
MM_REG_WRITE(cmd, subsys_id,
@@ -148,8 +159,47 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
rdma->mf_bkgd_in_pxl, 0x001FFFFF);
}
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, rdma->control,
- 0x1110);
+ if (mdp_cfg->rdma_support_extend_ufo)
+ write_mask |= 0xB0000000;
+
+ if (mdp_cfg->rdma_support_afbc)
+ write_mask |= 0x0603000;
+
+ if (mdp_cfg->rdma_support_hyfbc &&
+ (MDP_COLOR_IS_HYFBC_COMPRESS(colorformat))) {
+ /* Setup source buffer base */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y,
+ rdma->ufo_dec_y, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C,
+ rdma->ufo_dec_c, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL,
+ ((width + 31) >> 5) << 5, 0x1FFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL,
+ ((height + 7) >> 3) << 3, 0x1FFFFF);
+
+ /* Setup Compression Control */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON,
+ rdma->comp_ctrl, write_mask);
+ } else if (mdp_cfg->rdma_support_afbc &&
+ (MDP_COLOR_IS_COMPRESS(colorformat))) {
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL,
+ ((width + 31) >> 5) << 5, 0x1FFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL,
+ ((height + 7) >> 3) << 3, 0x1FFFFF);
+
+ /* Setup Compression Control */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON,
+ rdma->comp_ctrl, write_mask);
+ } else {
+ /* Setup Compression Control */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON,
+ rdma->comp_ctrl, write_mask);
+ }
+ }
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON,
+ rdma->control, 0x1130);
+
/* Setup source buffer base */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, rdma->iova[0],
0xFFFFFFFF);
@@ -173,6 +223,29 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0,
rdma->transform, 0x0F110000);
+ if (mdp_cfg->rdma_esl_setting) {
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0,
+ rdma->dmabuf_con0, 0x0FFF00FF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0,
+ rdma->ultra_th_high_con0, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0,
+ rdma->ultra_th_low_con0, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1,
+ rdma->dmabuf_con1, 0x0F7F007F);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1,
+ rdma->ultra_th_high_con1, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1,
+ rdma->ultra_th_low_con1, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2,
+ rdma->dmabuf_con2, 0x0F3F003F);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2,
+ rdma->ultra_th_high_con2, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2,
+ rdma->ultra_th_low_con2, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3,
+ rdma->dmabuf_con3, 0x0F3F003F);
+ }
+
return 0;
}
@@ -189,7 +262,18 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx,
u8 subsys_id = ctx->comp->subsys_id;
/* Enable RDMA */
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0));
+ MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0));
+
+ if (mdp_cfg->rdma_support_afbc ||
+ mdp_cfg->rdma_support_hyfbc) {
+ if (MDP_COLOR_IS_COMPRESS(colorformat) ||
+ MDP_COLOR_IS_HYFBC_COMPRESS(colorformat)) {
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P,
+ subfrm->in_tile_xleft, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_HP,
+ subfrm->in_tile_ytop, 0xFFFFFFFF);
+ }
+ }
/* Set Y pixel offset */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0,
@@ -234,15 +318,27 @@ static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
u8 subsys_id = ctx->comp->subsys_id;
int evt = -1;
- if (id == MDP_COMP_RDMA0)
+ switch (id) {
+ case MDP_COMP_RDMA0:
evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA0_DONE);
- else
- dev_err(dev, "Do not support RDMA1_DONE event\n");
+ break;
+ case MDP_COMP_RDMA1:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA1_DONE);
+ break;
+ case MDP_COMP_RDMA2:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA2_DONE);
+ break;
+ case MDP_COMP_RDMA3:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA3_DONE);
+ break;
+ default:
+ dev_err(dev, "Invalid Engine!\n");
+ }
if (evt > 0)
MM_REG_WAIT(cmd, evt);
/* Disable RDMA */
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
+ MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
return 0;
}
@@ -256,6 +352,75 @@ static const struct mdp_comp_ops rdma_ops = {
.post_process = NULL,
};
+static const struct mdp_comp_ops split_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = NULL,
+ .config_frame = NULL,
+ .config_subfrm = NULL,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static const struct mdp_comp_ops stitch_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = NULL,
+ .config_frame = NULL,
+ .config_subfrm = NULL,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_fg(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER,
+ (0x00000001 << 2), 0x00000004);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER,
+ 0x00000000, 0x00000004);
+
+ return 0;
+}
+
+static int config_fg_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_fg_data *fg = &ctx->param->fg;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, fg->ctrl_0, 0x1);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, fg->ck_en, 0x7);
+ return 0;
+}
+
+static int config_fg_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_fg_subfrm *subfrm = &ctx->param->fg.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, subfrm->info_0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, subfrm->info_1, 0xFFFFFFFF);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops fg_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_fg,
+ .config_frame = config_fg_frame,
+ .config_subfrm = config_fg_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
static int init_rsz(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
@@ -274,9 +439,13 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx,
const struct v4l2_rect *compose)
{
const struct mdp_rsz_data *rsz = &ctx->param->rsz;
+ const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ if (mdp_cfg && mdp_cfg->rsz_etc_control)
+ MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF);
+
if (ctx->param->frame.bypass) {
/* Disable RSZ */
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0));
@@ -363,6 +532,473 @@ static const struct mdp_comp_ops rsz_ops = {
.post_process = NULL,
};
+static int init_aal(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ // Always set MDP_AAL enable to 1
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, 0x1, 0x1);
+
+ return 0;
+}
+
+static int config_aal_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_aal_data *aal = &ctx->param->aal;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, aal->cfg_main, 0x80);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, aal->cfg, 0x1);
+
+ return 0;
+}
+
+static int config_aal_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_aal_subfrm *subfrm = &ctx->param->aal.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE,
+ subfrm->src, MDP_AAL_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET,
+ subfrm->clip_ofst, 0x00FF00FF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE,
+ subfrm->clip, MDP_AAL_OUTPUT_SIZE_MASK);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops aal_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_aal,
+ .config_frame = config_aal_frame,
+ .config_subfrm = config_aal_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_hdr(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ // Always set MDP_HDR enable to 1
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, 1, 0x1);
+
+ return 0;
+}
+
+static int config_hdr_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_hdr_data *hdr = &ctx->param->hdr;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP,
+ hdr->top, 0x30000000);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY,
+ hdr->relay, 0x1);
+
+ return 0;
+}
+
+static int config_hdr_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_hdr_subfrm *subfrm = &ctx->param->hdr.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS,
+ subfrm->win_size, MDP_HDR_TILE_POS_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0,
+ subfrm->src, 0x1FFF1FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1,
+ subfrm->clip_ofst0, 0x1FFF1FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2,
+ subfrm->clip_ofst1, 0x1FFF1FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0,
+ subfrm->hist_ctrl_0, 0x00003FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1,
+ subfrm->hist_ctrl_1, 0x00003FFF);
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP,
+ subfrm->hdr_top, 0x00000060);
+ // enable hist_clr_en
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR,
+ subfrm->hist_addr, 0x00000200);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops hdr_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_hdr,
+ .config_frame = config_hdr_frame,
+ .config_subfrm = config_hdr_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static void reset_luma_hist(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ // reset LUMA HIST
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_00, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_01, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_02, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_03, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_04, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_05, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_06, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_07, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_08, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_09, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_10, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_11, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_12, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_13, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_14, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_15, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_16, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_SUM_INIT, 0, 0xFFFFFFFF);
+
+ if (mdp_cfg && mdp_cfg->tdshp_1_1) {
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF);
+ }
+
+ if (mdp_cfg && mdp_cfg->tdshp_dyn_contrast_version == 2) {
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_00, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_01, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_02, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_03, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_04, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_05, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_06, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_07, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_08, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_09, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_10, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_11, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_12, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_13, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_14, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_15, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_16, 0, 0xFFFFFFFF);
+ }
+}
+
+static int init_tdshp(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, 0x00000001,
+ 0x00000001);
+ // Enable fifo
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, 0x00000002,
+ 0x00000002);
+ reset_luma_hist(ctx, cmd);
+
+ return 0;
+}
+
+static int config_tdshp_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_tdshp_data *tdshp = &ctx->param->tdshp;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, tdshp->cfg, 0x00000001);
+
+ return 0;
+}
+
+static int config_tdshp_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_tdshp_subfrm *subfrm = &ctx->param->tdshp.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE,
+ subfrm->src, MDP_TDSHP_INPUT_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET,
+ subfrm->clip_ofst, 0x00FF00FF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE,
+ subfrm->clip, MDP_TDSHP_OUTPUT_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00,
+ subfrm->hist_cfg_0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01,
+ subfrm->hist_cfg_1, 0xFFFFFFFF);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops tdshp_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_tdshp,
+ .config_frame = config_tdshp_frame,
+ .config_subfrm = config_tdshp_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_color(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_START, 0x1, 0x3);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF);
+
+ // R2Y/Y2R are disabled in MDP
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_CM1_EN, 0x0, 0x1);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_CM2_EN, 0x0, 0x1);
+
+ //enable interrupt
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_INTEN, 0x00000007, 0x00000007);
+
+ //Set 10bit->8bit Rounding
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_OUT_SEL, 0x333, 0x333);
+
+ return 0;
+}
+
+static int config_color_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_color_data *color = &ctx->param->color;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_START, color->start, DISP_COLOR_START_MASK);
+
+ return 0;
+}
+
+static int config_color_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_color_subfrm *subfrm = &ctx->param->color.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, DISP_COLOR_INTERNAL_IP_WIDTH,
+ subfrm->in_hsize, 0x00003FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, DISP_COLOR_INTERNAL_IP_HEIGHT,
+ subfrm->in_vsize, 0x00003FFF);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops color_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_color,
+ .config_frame = config_color_frame,
+ .config_subfrm = config_color_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_ovl(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_EN,
+ 0x1, OVL_EN_MASK);
+ //Relay Mode
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_SRC_CON,
+ 0x200, OVL_SRC_CON_MASK);
+ //Connect OVL, enable smi_id mode
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_DATAPATH_CON,
+ 0x1, OVL_DATAPATH_CON_MASK);
+
+ return 0;
+}
+
+static int config_ovl_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_ovl_data *ovl = &ctx->param->ovl;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ //Layer0 for PQ-direct-in
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_L0_CON,
+ ovl->L0_con, 0x30000000);
+ //Enable Layer0
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_SRC_CON,
+ ovl->src_con, 0x1);
+
+ return 0;
+}
+
+static int config_ovl_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_ovl_subfrm *subfrm = &ctx->param->ovl.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ //Setup Layer0 source size
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_L0_SRC_SIZE,
+ subfrm->L0_src_size, OVL_L0_SRC_SIZE_MASK);
+ //Setup ROI size (output size)
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_ROI_SIZE,
+ subfrm->roi_size, OVL_ROI_SIZE_MASK);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops ovl_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_ovl,
+ .config_frame = config_ovl_frame,
+ .config_subfrm = config_ovl_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_pad(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_PADDING_CON,
+ 0x2, VPP_PADDING0_PADDING_CON_MASK);
+ //Clear padding area
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_W_PADDING_SIZE,
+ 0x0, VPP_PADDING0_W_PADDING_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_H_PADDING_SIZE,
+ 0x0, VPP_PADDING0_H_PADDING_SIZE_MASK);
+
+ return 0;
+}
+
+static int config_pad_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ return 0;
+}
+
+static int config_pad_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_pad_subfrm *subfrm = &ctx->param->pad.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_PADDING_PIC_SIZE,
+ subfrm->pic_size, VPP_PADDING0_PADDING_CON_MASK);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops pad_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_pad,
+ .config_frame = config_pad_frame,
+ .config_subfrm = config_pad_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_tcc(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ return 0;
+}
+
+static int config_tcc_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ return 0;
+}
+
+static int config_tcc_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ return 0;
+}
+
+static const struct mdp_comp_ops tcc_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_tcc,
+ .config_frame = config_tcc_frame,
+ .config_subfrm = config_tcc_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
static int init_wrot(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
@@ -371,6 +1007,8 @@ static int init_wrot(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
/* Reset WROT */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0));
MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0));
+ /* Reset setting */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0));
MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0));
return 0;
@@ -384,6 +1022,8 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ bool comp;
+ u32 colorformat = ctx->outputs[0]->buffer.format.colorformat;
/* Write frame base address */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0],
@@ -392,9 +1032,38 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
0xFFFFFFFF);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, wrot->iova[2],
0xFFFFFFFF);
+
+ if (mdp_cfg) {
+ if (mdp_cfg->wrot_support_afbc) {
+ comp = MDP_COLOR_IS_COMPRESS(colorformat);
+ if (comp) {
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_FRAME_SIZE,
+ wrot->framesize, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_AFBC_YUVTRANS,
+ wrot->afbc_yuvtrans, 0x1);
+ }
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PVRIC, wrot->pvric, 0x03);
+ }
+
+ if (mdp_cfg->wrot_support_10bit) {
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT,
+ wrot->scan_10bit, 0x0000000F);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO,
+ wrot->pending_zero, 0x04000000);
+ }
+ if (mdp_cfg->mdp_version_6885)
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2,
+ wrot->bit_number, 0x00000007);
+ }
+
/* Write frame related registers */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, wrot->control,
0xF131510F);
+
+ /* Write pre-ultra threshold */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, wrot->pre_ultra,
+ 0x00FFFFFF);
+
/* Write frame Y pitch */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, wrot->stride[0],
0x0000FFFF);
@@ -447,7 +1116,6 @@ static int config_wrot_subfrm(struct mdp_comp_ctx *ctx,
0x1FFF1FFF);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, subfrm->clip_ofst,
0x1FFF1FFF);
-
MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
subfrm->main_buf, 0x1FFF7F00);
@@ -466,11 +1134,22 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
u8 subsys_id = ctx->comp->subsys_id;
int evt = -1;
- if (id == MDP_COMP_WROT0)
+ switch (id) {
+ case MDP_COMP_WROT0:
evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT0_DONE);
- else
- dev_err(dev, "Do not support WROT1_DONE event\n");
-
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT1_DONE);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT2_DONE);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT3_DONE);
+ break;
+ default:
+ dev_err(dev, "Invalid Engine!\n");
+ }
if (evt > 0)
MM_REG_WAIT(cmd, evt);
--
2.18.0
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 08/14] media: platform: mtk-mdp3: Add engine setting for MT8195
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add engine setting and related header files for MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mdp_reg_aal.h | 24 +
.../media/platform/mtk-mdp3/mdp_reg_color.h | 29 +
drivers/media/platform/mtk-mdp3/mdp_reg_fg.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h | 31 +
.../media/platform/mtk-mdp3/mdp_reg_merge.h | 23 +
drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h | 24 +
drivers/media/platform/mtk-mdp3/mdp_reg_pad.h | 20 +
.../media/platform/mtk-mdp3/mdp_reg_rdma.h | 31 +
drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 2 +
.../media/platform/mtk-mdp3/mdp_reg_tdshp.h | 116 +++
.../media/platform/mtk-mdp3/mdp_reg_wrot.h | 18 +
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 705 +++++++++++++++++-
12 files changed, 1033 insertions(+), 13 deletions(-)
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_color.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h b/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
new file mode 100644
index 000000000000..2275a06fbdf9
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_aal.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_AAL_H__
+#define __MDP_REG_AAL_H__
+
+#define MDP_AAL_EN (0x000)
+#define MDP_AAL_CFG (0x020)
+#define MDP_AAL_SIZE (0x030)
+#define MDP_AAL_OUTPUT_SIZE (0x034)
+#define MDP_AAL_OUTPUT_OFFSET (0x038)
+#define MDP_AAL_CFG_MAIN (0x200)
+
+#define MDP_AAL_EN_MASK (0x01)
+#define MDP_AAL_CFG_MASK (0x70FF00B3)
+#define MDP_AAL_SIZE_MASK (0x1FFF1FFF)
+#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF)
+#define MDP_AAL_CFG_MAIN_MASK (0x0FE)
+
+#endif // __MDP_REG_AAL_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_color.h b/drivers/media/platform/mtk-mdp3/mdp_reg_color.h
new file mode 100644
index 000000000000..54d917a20362
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_color.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_COLOR_H__
+#define __MDP_REG_COLOR_H__
+
+#define DISP_COLOR_WIN_X_MAIN (0x40C)
+#define DISP_COLOR_WIN_Y_MAIN (0x410)
+#define DISP_COLOR_START (0xC00)
+#define DISP_COLOR_INTEN (0xC04)
+#define DISP_COLOR_OUT_SEL (0xC0C)
+#define DISP_COLOR_INTERNAL_IP_WIDTH (0xC50)
+#define DISP_COLOR_INTERNAL_IP_HEIGHT (0xC54)
+#define DISP_COLOR_CM1_EN (0xC60)
+#define DISP_COLOR_CM2_EN (0xCA0)
+// MASK
+#define DISP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF)
+#define DISP_COLOR_WIN_Y_MAIN_MASK (0xFFFFFFFF)
+#define DISP_COLOR_START_MASK (0x0FF013F)
+#define DISP_COLOR_INTEN_MASK (0x07)
+#define DISP_COLOR_OUT_SEL_MASK (0x0777)
+#define DISP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF)
+#define DISP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF)
+#define DISP_COLOR_CM1_EN_MASK (0x03)
+#define DISP_COLOR_CM2_EN_MASK (0x017)
+#endif // __MDP_REG_COLOR_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h b/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
new file mode 100644
index 000000000000..34f68554c0bb
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_fg.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_FG_H__
+#define __MDP_REG_FG_H__
+
+#define MDP_FG_TRIGGER (0x0)
+#define MDP_FG_FG_CTRL_0 (0x20)
+#define MDP_FG_FG_CK_EN (0x24)
+#define MDP_FG_TILE_INFO_0 (0x418)
+#define MDP_FG_TILE_INFO_1 (0x41c)
+
+/* MASK */
+#define MDP_FG_TRIGGER_MASK (0x00000007)
+#define MDP_FG_FG_CTRL_0_MASK (0x00000033)
+#define MDP_FG_FG_CK_EN_MASK (0x0000000F)
+#define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF)
+#define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF)
+
+#endif //__MDP_REG_FG_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h b/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
new file mode 100644
index 000000000000..06d0d3a6a139
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_hdr.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_HDR_H__
+#define __MDP_REG_HDR_H__
+
+#define MDP_HDR_TOP (0x000)
+#define MDP_HDR_RELAY (0x004)
+#define MDP_HDR_SIZE_0 (0x014)
+#define MDP_HDR_SIZE_1 (0x018)
+#define MDP_HDR_SIZE_2 (0x01C)
+#define MDP_HDR_HIST_CTRL_0 (0x020)
+#define MDP_HDR_HIST_CTRL_1 (0x024)
+#define MDP_HDR_HIST_ADDR (0x0DC)
+#define MDP_HDR_TILE_POS (0x118)
+
+// MASK
+#define MDP_HDR_RELAY_MASK (0x01)
+#define MDP_HDR_TOP_MASK (0xFF0FEB6D)
+#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF)
+#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF)
+#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF)
+#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F)
+#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF)
+
+#endif // __MDP_REG_HDR_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h b/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
new file mode 100644
index 000000000000..d53d58d4ea05
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_merge.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_MERGE_H__
+#define __MDP_REG_MERGE_H__
+
+#define VPP_MERGE_ENABLE (0x000)
+#define VPP_MERGE_CFG_0 (0x010)
+#define VPP_MERGE_CFG_4 (0x020)
+#define VPP_MERGE_CFG_12 (0x040)
+#define VPP_MERGE_CFG_24 (0x070)
+#define VPP_MERGE_CFG_25 (0x074)
+
+#define VPP_MERGE_ENABLE_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_0_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_4_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_12_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_24_MASK (0xFFFFFFFF)
+#define VPP_MERGE_CFG_25_MASK (0xFFFFFFFF)
+#endif
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h b/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
new file mode 100644
index 000000000000..35aa10c763bd
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_ovl.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_OVL_H__
+#define __MDP_REG_OVL_H__
+
+#define OVL_EN (0x00c)
+#define OVL_ROI_SIZE (0x020)
+#define OVL_DATAPATH_CON (0x024)
+#define OVL_SRC_CON (0x02c)
+#define OVL_L0_CON (0x030)
+#define OVL_L0_SRC_SIZE (0x038)
+
+#define OVL_DATAPATH_CON_MASK (0x0FFFFFFF)
+#define OVL_EN_MASK (0xB07D07B1)
+#define OVL_L0_CON_MASK (0xFFFFFFFF)
+#define OVL_L0_SRC_SIZE_MASK (0x1FFF1FFF)
+#define OVL_ROI_SIZE_MASK (0x1FFF1FFF)
+#define OVL_SRC_CON_MASK (0x0000031F)
+
+#endif //__MDP_REG_OVL_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h b/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
new file mode 100644
index 000000000000..f4d6d06a74be
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_pad.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_PAD_H__
+#define __MDP_REG_PAD_H__
+
+#define VPP_PADDING0_PADDING_CON (0x000)
+#define VPP_PADDING0_PADDING_PIC_SIZE (0x004)
+#define VPP_PADDING0_W_PADDING_SIZE (0x008)
+#define VPP_PADDING0_H_PADDING_SIZE (0x00c)
+
+#define VPP_PADDING0_PADDING_CON_MASK (0x00000007)
+#define VPP_PADDING0_PADDING_PIC_SIZE_MASK (0xFFFFFFFF)
+#define VPP_PADDING0_W_PADDING_SIZE_MASK (0x1FFF1FFF)
+#define VPP_PADDING0_H_PADDING_SIZE_MASK (0x1FFF1FFF)
+
+#endif // __MDP_REG_PAD_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h b/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
index 59d9aae40be6..06dea03ae029 100644
--- a/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
@@ -12,12 +12,14 @@
#define MDP_RDMA_CON 0x020
#define MDP_RDMA_GMCIF_CON 0x028
#define MDP_RDMA_SRC_CON 0x030
+#define MDP_RDMA_COMP_CON 0x038
#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
#define MDP_RDMA_MF_SRC_SIZE 0x070
#define MDP_RDMA_MF_CLIP_SIZE 0x078
#define MDP_RDMA_MF_OFFSET_1 0x080
#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL 0x098
#define MDP_RDMA_SRC_END_0 0x100
#define MDP_RDMA_SRC_END_1 0x108
#define MDP_RDMA_SRC_END_2 0x110
@@ -25,7 +27,20 @@
#define MDP_RDMA_SRC_OFFSET_1 0x120
#define MDP_RDMA_SRC_OFFSET_2 0x128
#define MDP_RDMA_SRC_OFFSET_0_P 0x148
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
#define MDP_RDMA_TRANSFORM_0 0x200
+#define MDP_RDMA_DMABUF_CON_0 0x240
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248
+#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
#define MDP_RDMA_RESV_DUMMY_0 0x2a0
#define MDP_RDMA_MON_STA_1 0x408
#define MDP_RDMA_SRC_BASE_0 0xf00
@@ -40,12 +55,14 @@
#define MDP_RDMA_CON_MASK 0x00001110
#define MDP_RDMA_GMCIF_CON_MASK 0xfffb3771
#define MDP_RDMA_SRC_CON_MASK 0xf3ffffff
+#define MDP_RDMA_COMP_CON_MASK 0xffffc000
#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK 0x001fffff
#define MDP_RDMA_MF_SRC_SIZE_MASK 0x1fff1fff
#define MDP_RDMA_MF_CLIP_SIZE_MASK 0x1fff1fff
#define MDP_RDMA_MF_OFFSET_1_MASK 0x003f001f
#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL_MASK 0x007fffff
#define MDP_RDMA_SRC_END_0_MASK 0xffffffff
#define MDP_RDMA_SRC_END_1_MASK 0xffffffff
#define MDP_RDMA_SRC_END_2_MASK 0xffffffff
@@ -53,7 +70,21 @@
#define MDP_RDMA_SRC_OFFSET_1_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff
#define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff
+#define MDP_RDMA_SRC_OFFSET_HP_MASK 0xffffffff
#define MDP_RDMA_TRANSFORM_0_MASK 0xff110777
+#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff
+#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff
+
#define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff
#define MDP_RDMA_MON_STA_1_MASK 0xffffffff
#define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h b/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
index 051fdb020741..942fd4393eba 100644
--- a/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
@@ -20,6 +20,7 @@
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034
+#define RSZ_ETC_CONTROL 0x22c
/* MASK */
#define PRZ_ENABLE_MASK 0x00010001
@@ -35,5 +36,6 @@
#define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff
#define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff
#define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff
+#define RSZ_ETC_CONTROL_MASK 0xff770000
#endif // __MDP_REG_RSZ_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h b/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
new file mode 100644
index 000000000000..7907266ac7c7
--- /dev/null
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_tdshp.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
+ */
+
+#ifndef __MDP_REG_TDSHP_H__
+#define __MDP_REG_TDSHP_H__
+
+#define MDP_HIST_CFG_00 (0x064)
+#define MDP_HIST_CFG_01 (0x068)
+#define MDP_TDSHP_CTRL (0x100)
+#define MDP_TDSHP_CFG (0x110)
+#define MDP_TDSHP_INPUT_SIZE (0x120)
+#define MDP_TDSHP_OUTPUT_OFFSET (0x124)
+#define MDP_TDSHP_OUTPUT_SIZE (0x128)
+#define MDP_LUMA_HIST_INIT_00 (0x200)
+#define MDP_LUMA_HIST_INIT_01 (0x204)
+#define MDP_LUMA_HIST_INIT_02 (0x208)
+#define MDP_LUMA_HIST_INIT_03 (0x20C)
+#define MDP_LUMA_HIST_INIT_04 (0x210)
+#define MDP_LUMA_HIST_INIT_05 (0x214)
+#define MDP_LUMA_HIST_INIT_06 (0x218)
+#define MDP_LUMA_HIST_INIT_07 (0x21C)
+#define MDP_LUMA_HIST_INIT_08 (0x220)
+#define MDP_LUMA_HIST_INIT_09 (0x224)
+#define MDP_LUMA_HIST_INIT_10 (0x228)
+#define MDP_LUMA_HIST_INIT_11 (0x22C)
+#define MDP_LUMA_HIST_INIT_12 (0x230)
+#define MDP_LUMA_HIST_INIT_13 (0x234)
+#define MDP_LUMA_HIST_INIT_14 (0x238)
+#define MDP_LUMA_HIST_INIT_15 (0x23C)
+#define MDP_LUMA_HIST_INIT_16 (0x240)
+#define MDP_LUMA_SUM_INIT (0x244)
+#define MDP_DC_TWO_D_W1_RESULT_INIT (0x260)
+#define MDP_CONTOUR_HIST_INIT_00 (0x398)
+#define MDP_CONTOUR_HIST_INIT_01 (0x39C)
+#define MDP_CONTOUR_HIST_INIT_02 (0x3A0)
+#define MDP_CONTOUR_HIST_INIT_03 (0x3A4)
+#define MDP_CONTOUR_HIST_INIT_04 (0x3A8)
+#define MDP_CONTOUR_HIST_INIT_05 (0x3AC)
+#define MDP_CONTOUR_HIST_INIT_06 (0x3B0)
+#define MDP_CONTOUR_HIST_INIT_07 (0x3B4)
+#define MDP_CONTOUR_HIST_INIT_08 (0x3B8)
+#define MDP_CONTOUR_HIST_INIT_09 (0x3BC)
+#define MDP_CONTOUR_HIST_INIT_10 (0x3C0)
+#define MDP_CONTOUR_HIST_INIT_11 (0x3C4)
+#define MDP_CONTOUR_HIST_INIT_12 (0x3C8)
+#define MDP_CONTOUR_HIST_INIT_13 (0x3CC)
+#define MDP_CONTOUR_HIST_INIT_14 (0x3D0)
+#define MDP_CONTOUR_HIST_INIT_15 (0x3D4)
+#define MDP_CONTOUR_HIST_INIT_16 (0x3D8)
+
+// MASK
+#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF)
+#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF)
+#define MDP_LUMA_HIST_00_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_01_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_02_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_03_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_04_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_05_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_06_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_07_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_08_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_09_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_10_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_11_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_12_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_13_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_14_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_15_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_16_MASK (0x07FFFFFF)
+#define MDP_TDSHP_CTRL_MASK (0x07)
+#define MDP_TDSHP_CFG_MASK (0x03F7)
+#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF)
+#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF)
+#define MDP_LUMA_HIST_INIT_00_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_01_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_02_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_03_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_04_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_05_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_06_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_07_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_08_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_09_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_10_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_11_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_12_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_13_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_14_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_15_MASK (0x07FFFFFF)
+#define MDP_LUMA_HIST_INIT_16_MASK (0x07FFFFFF)
+#define MDP_LUMA_SUM_INIT_MASK (0xFFFFFFFF)
+#define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF)
+#define MDP_CONTOUR_HIST_INIT_00_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_01_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_02_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_03_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_04_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_05_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_06_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_07_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_08_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_09_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_10_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_11_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_12_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_13_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_14_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_15_MASK (0x07FFFFFF)
+#define MDP_CONTOUR_HIST_INIT_16_MASK (0x07FFFFFF)
+
+#endif // __MDP_REG_TDSHP_H__
diff --git a/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h b/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
index 39b8785f89eb..81a7c46c1aef 100644
--- a/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
+++ b/drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
@@ -11,23 +11,32 @@
#define VIDO_MAIN_BUF_SIZE 0x008
#define VIDO_SOFT_RST 0x010
#define VIDO_SOFT_RST_STAT 0x014
+#define VIDO_INT 0x01c
#define VIDO_CROP_OFST 0x020
#define VIDO_TAR_SIZE 0x024
+#define VIDO_FRAME_SIZE 0x028
#define VIDO_OFST_ADDR 0x02c
#define VIDO_STRIDE 0x030
+#define VIDO_BKGD 0x034
#define VIDO_OFST_ADDR_C 0x038
#define VIDO_STRIDE_C 0x03c
+#define VIDO_CTRL_2 0x048
#define VIDO_DITHER 0x054
#define VIDO_STRIDE_V 0x06c
#define VIDO_OFST_ADDR_V 0x068
#define VIDO_RSV_1 0x070
+#define VIDO_DMA_PREULTRA 0x074
#define VIDO_IN_SIZE 0x078
#define VIDO_ROT_EN 0x07c
#define VIDO_FIFO_TEST 0x080
#define VIDO_MAT_CTRL 0x084
+#define VIDO_PVRIC 0x0d8
+#define VIDO_SCAN_10BIT 0x0dc
+#define VIDO_PENDING_ZERO 0x0e0
#define VIDO_BASE_ADDR 0xf00
#define VIDO_BASE_ADDR_C 0xf04
#define VIDO_BASE_ADDR_V 0xf08
+#define VIDO_AFBC_YUVTRANS 0xf2c
/* MASK */
#define VIDO_CTRL_MASK 0xf530711f
@@ -36,6 +45,7 @@
#define VIDO_SOFT_RST_STAT_MASK 0x00000001
#define VIDO_TAR_SIZE_MASK 0x1fff1fff
#define VIDO_CROP_OFST_MASK 0x1fff1fff
+#define VIDO_INT_MASK 0x00000007
#define VIDO_OFST_ADDR_MASK 0x0fffffff
#define VIDO_STRIDE_MASK 0x0000ffff
#define VIDO_OFST_ADDR_C_MASK 0x0fffffff
@@ -51,5 +61,13 @@
#define VIDO_BASE_ADDR_MASK 0xffffffff
#define VIDO_BASE_ADDR_C_MASK 0xffffffff
#define VIDO_BASE_ADDR_V_MASK 0xffffffff
+#define VIDO_DMA_PREULTRA_MASK 0x00ffffff
+#define VIDO_FRAME_SIZE_MASK 0xffffffff
+#define VIDO_BKGD_MASK 0xffffffff
+#define VIDO_CTRL_2_MASK 0x0000000f
+#define VIDO_PVRIC_MASK 0x00000003
+#define VIDO_SCAN_10BIT_MASK 0x0000000f
+#define VIDO_PENDING_ZERO_MASK 0x07ffffff
+#define VIDO_AFBC_YUVTRANS_MASK 0x00000001
#endif // __MDP_REG_WROT_H__
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index fdf072e48238..8ca9c7e325e1 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -15,6 +15,14 @@
#include "mdp_reg_rdma.h"
#include "mdp_reg_ccorr.h"
#include "mdp_reg_rsz.h"
+#include "mdp_reg_fg.h"
+#include "mdp_reg_aal.h"
+#include "mdp_reg_tdshp.h"
+#include "mdp_reg_hdr.h"
+#include "mdp_reg_color.h"
+#include "mdp_reg_ovl.h"
+#include "mdp_reg_pad.h"
+#include "mdp_reg_merge.h"
#include "mdp_reg_wrot.h"
#include "mdp_reg_wdma.h"
#include "mdp_reg_isp.h"
@@ -107,7 +115,10 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
{
const struct mdp_rdma_data *rdma = &ctx->param->rdma;
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ u32 width = ctx->input->buffer.format.width;
+ u32 height = ctx->input->buffer.format.height;
u32 colorformat = ctx->input->buffer.format.colorformat;
+ u32 write_mask = 0;
bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat);
bool en_ufo = MDP_COLOR_IS_UFP(colorformat);
phys_addr_t base = ctx->comp->reg_base;
@@ -132,7 +143,7 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, rdma->src_ctrl,
0x03C8FE0F);
- if (mdp_cfg)
+ if (mdp_cfg) {
if (mdp_cfg->rdma_support_10bit && en_ufo) {
/* Setup source buffer base */
MM_REG_WRITE(cmd, subsys_id,
@@ -148,8 +159,47 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
rdma->mf_bkgd_in_pxl, 0x001FFFFF);
}
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, rdma->control,
- 0x1110);
+ if (mdp_cfg->rdma_support_extend_ufo)
+ write_mask |= 0xB0000000;
+
+ if (mdp_cfg->rdma_support_afbc)
+ write_mask |= 0x0603000;
+
+ if (mdp_cfg->rdma_support_hyfbc &&
+ (MDP_COLOR_IS_HYFBC_COMPRESS(colorformat))) {
+ /* Setup source buffer base */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y,
+ rdma->ufo_dec_y, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C,
+ rdma->ufo_dec_c, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL,
+ ((width + 31) >> 5) << 5, 0x1FFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL,
+ ((height + 7) >> 3) << 3, 0x1FFFFF);
+
+ /* Setup Compression Control */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON,
+ rdma->comp_ctrl, write_mask);
+ } else if (mdp_cfg->rdma_support_afbc &&
+ (MDP_COLOR_IS_COMPRESS(colorformat))) {
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL,
+ ((width + 31) >> 5) << 5, 0x1FFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PXL,
+ ((height + 7) >> 3) << 3, 0x1FFFFF);
+
+ /* Setup Compression Control */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON,
+ rdma->comp_ctrl, write_mask);
+ } else {
+ /* Setup Compression Control */
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_COMP_CON,
+ rdma->comp_ctrl, write_mask);
+ }
+ }
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON,
+ rdma->control, 0x1130);
+
/* Setup source buffer base */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, rdma->iova[0],
0xFFFFFFFF);
@@ -173,6 +223,29 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx,
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0,
rdma->transform, 0x0F110000);
+ if (mdp_cfg->rdma_esl_setting) {
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0,
+ rdma->dmabuf_con0, 0x0FFF00FF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0,
+ rdma->ultra_th_high_con0, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0,
+ rdma->ultra_th_low_con0, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1,
+ rdma->dmabuf_con1, 0x0F7F007F);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1,
+ rdma->ultra_th_high_con1, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1,
+ rdma->ultra_th_low_con1, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2,
+ rdma->dmabuf_con2, 0x0F3F003F);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2,
+ rdma->ultra_th_high_con2, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2,
+ rdma->ultra_th_low_con2, 0x3FFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3,
+ rdma->dmabuf_con3, 0x0F3F003F);
+ }
+
return 0;
}
@@ -189,7 +262,18 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx,
u8 subsys_id = ctx->comp->subsys_id;
/* Enable RDMA */
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0));
+ MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0));
+
+ if (mdp_cfg->rdma_support_afbc ||
+ mdp_cfg->rdma_support_hyfbc) {
+ if (MDP_COLOR_IS_COMPRESS(colorformat) ||
+ MDP_COLOR_IS_HYFBC_COMPRESS(colorformat)) {
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P,
+ subfrm->in_tile_xleft, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_HP,
+ subfrm->in_tile_ytop, 0xFFFFFFFF);
+ }
+ }
/* Set Y pixel offset */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0,
@@ -234,15 +318,27 @@ static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
u8 subsys_id = ctx->comp->subsys_id;
int evt = -1;
- if (id == MDP_COMP_RDMA0)
+ switch (id) {
+ case MDP_COMP_RDMA0:
evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA0_DONE);
- else
- dev_err(dev, "Do not support RDMA1_DONE event\n");
+ break;
+ case MDP_COMP_RDMA1:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA1_DONE);
+ break;
+ case MDP_COMP_RDMA2:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA2_DONE);
+ break;
+ case MDP_COMP_RDMA3:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA3_DONE);
+ break;
+ default:
+ dev_err(dev, "Invalid Engine!\n");
+ }
if (evt > 0)
MM_REG_WAIT(cmd, evt);
/* Disable RDMA */
- MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
+ MM_REG_WRITE_MASK(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0));
return 0;
}
@@ -256,6 +352,75 @@ static const struct mdp_comp_ops rdma_ops = {
.post_process = NULL,
};
+static const struct mdp_comp_ops split_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = NULL,
+ .config_frame = NULL,
+ .config_subfrm = NULL,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static const struct mdp_comp_ops stitch_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = NULL,
+ .config_frame = NULL,
+ .config_subfrm = NULL,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_fg(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER,
+ (0x00000001 << 2), 0x00000004);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER,
+ 0x00000000, 0x00000004);
+
+ return 0;
+}
+
+static int config_fg_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_fg_data *fg = &ctx->param->fg;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, fg->ctrl_0, 0x1);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, fg->ck_en, 0x7);
+ return 0;
+}
+
+static int config_fg_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_fg_subfrm *subfrm = &ctx->param->fg.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, subfrm->info_0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, subfrm->info_1, 0xFFFFFFFF);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops fg_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_fg,
+ .config_frame = config_fg_frame,
+ .config_subfrm = config_fg_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
static int init_rsz(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
@@ -274,9 +439,13 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx,
const struct v4l2_rect *compose)
{
const struct mdp_rsz_data *rsz = &ctx->param->rsz;
+ const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ if (mdp_cfg && mdp_cfg->rsz_etc_control)
+ MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF);
+
if (ctx->param->frame.bypass) {
/* Disable RSZ */
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0));
@@ -363,6 +532,473 @@ static const struct mdp_comp_ops rsz_ops = {
.post_process = NULL,
};
+static int init_aal(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ // Always set MDP_AAL enable to 1
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, 0x1, 0x1);
+
+ return 0;
+}
+
+static int config_aal_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_aal_data *aal = &ctx->param->aal;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, aal->cfg_main, 0x80);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, aal->cfg, 0x1);
+
+ return 0;
+}
+
+static int config_aal_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_aal_subfrm *subfrm = &ctx->param->aal.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE,
+ subfrm->src, MDP_AAL_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET,
+ subfrm->clip_ofst, 0x00FF00FF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE,
+ subfrm->clip, MDP_AAL_OUTPUT_SIZE_MASK);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops aal_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_aal,
+ .config_frame = config_aal_frame,
+ .config_subfrm = config_aal_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_hdr(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ // Always set MDP_HDR enable to 1
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, 1, 0x1);
+
+ return 0;
+}
+
+static int config_hdr_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_hdr_data *hdr = &ctx->param->hdr;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP,
+ hdr->top, 0x30000000);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY,
+ hdr->relay, 0x1);
+
+ return 0;
+}
+
+static int config_hdr_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_hdr_subfrm *subfrm = &ctx->param->hdr.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS,
+ subfrm->win_size, MDP_HDR_TILE_POS_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0,
+ subfrm->src, 0x1FFF1FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1,
+ subfrm->clip_ofst0, 0x1FFF1FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2,
+ subfrm->clip_ofst1, 0x1FFF1FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0,
+ subfrm->hist_ctrl_0, 0x00003FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1,
+ subfrm->hist_ctrl_1, 0x00003FFF);
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP,
+ subfrm->hdr_top, 0x00000060);
+ // enable hist_clr_en
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR,
+ subfrm->hist_addr, 0x00000200);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops hdr_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_hdr,
+ .config_frame = config_hdr_frame,
+ .config_subfrm = config_hdr_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static void reset_luma_hist(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ // reset LUMA HIST
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_00, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_01, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_02, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_03, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_04, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_05, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_06, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_07, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_08, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_09, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_10, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_11, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_12, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_13, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_14, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_15, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_HIST_INIT_16, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_LUMA_SUM_INIT, 0, 0xFFFFFFFF);
+
+ if (mdp_cfg && mdp_cfg->tdshp_1_1) {
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF);
+ }
+
+ if (mdp_cfg && mdp_cfg->tdshp_dyn_contrast_version == 2) {
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_00, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_01, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_02, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_03, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_04, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_05, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_06, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_07, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_08, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_09, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_10, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_11, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_12, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_13, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_14, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_15, 0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ MDP_CONTOUR_HIST_INIT_16, 0, 0xFFFFFFFF);
+ }
+}
+
+static int init_tdshp(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, 0x00000001,
+ 0x00000001);
+ // Enable fifo
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, 0x00000002,
+ 0x00000002);
+ reset_luma_hist(ctx, cmd);
+
+ return 0;
+}
+
+static int config_tdshp_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_tdshp_data *tdshp = &ctx->param->tdshp;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, tdshp->cfg, 0x00000001);
+
+ return 0;
+}
+
+static int config_tdshp_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_tdshp_subfrm *subfrm = &ctx->param->tdshp.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE,
+ subfrm->src, MDP_TDSHP_INPUT_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET,
+ subfrm->clip_ofst, 0x00FF00FF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE,
+ subfrm->clip, MDP_TDSHP_OUTPUT_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00,
+ subfrm->hist_cfg_0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01,
+ subfrm->hist_cfg_1, 0xFFFFFFFF);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops tdshp_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_tdshp,
+ .config_frame = config_tdshp_frame,
+ .config_subfrm = config_tdshp_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_color(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_START, 0x1, 0x3);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF);
+
+ // R2Y/Y2R are disabled in MDP
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_CM1_EN, 0x0, 0x1);
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_CM2_EN, 0x0, 0x1);
+
+ //enable interrupt
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_INTEN, 0x00000007, 0x00000007);
+
+ //Set 10bit->8bit Rounding
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_OUT_SEL, 0x333, 0x333);
+
+ return 0;
+}
+
+static int config_color_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_color_data *color = &ctx->param->color;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base,
+ DISP_COLOR_START, color->start, DISP_COLOR_START_MASK);
+
+ return 0;
+}
+
+static int config_color_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_color_subfrm *subfrm = &ctx->param->color.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, DISP_COLOR_INTERNAL_IP_WIDTH,
+ subfrm->in_hsize, 0x00003FFF);
+ MM_REG_WRITE(cmd, subsys_id, base, DISP_COLOR_INTERNAL_IP_HEIGHT,
+ subfrm->in_vsize, 0x00003FFF);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops color_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_color,
+ .config_frame = config_color_frame,
+ .config_subfrm = config_color_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_ovl(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_EN,
+ 0x1, OVL_EN_MASK);
+ //Relay Mode
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_SRC_CON,
+ 0x200, OVL_SRC_CON_MASK);
+ //Connect OVL, enable smi_id mode
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_DATAPATH_CON,
+ 0x1, OVL_DATAPATH_CON_MASK);
+
+ return 0;
+}
+
+static int config_ovl_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ const struct mdp_ovl_data *ovl = &ctx->param->ovl;
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ //Layer0 for PQ-direct-in
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_L0_CON,
+ ovl->L0_con, 0x30000000);
+ //Enable Layer0
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_SRC_CON,
+ ovl->src_con, 0x1);
+
+ return 0;
+}
+
+static int config_ovl_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_ovl_subfrm *subfrm = &ctx->param->ovl.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ //Setup Layer0 source size
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_L0_SRC_SIZE,
+ subfrm->L0_src_size, OVL_L0_SRC_SIZE_MASK);
+ //Setup ROI size (output size)
+ MM_REG_WRITE(cmd, subsys_id, base, OVL_ROI_SIZE,
+ subfrm->roi_size, OVL_ROI_SIZE_MASK);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops ovl_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_ovl,
+ .config_frame = config_ovl_frame,
+ .config_subfrm = config_ovl_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_pad(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_PADDING_CON,
+ 0x2, VPP_PADDING0_PADDING_CON_MASK);
+ //Clear padding area
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_W_PADDING_SIZE,
+ 0x0, VPP_PADDING0_W_PADDING_SIZE_MASK);
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_H_PADDING_SIZE,
+ 0x0, VPP_PADDING0_H_PADDING_SIZE_MASK);
+
+ return 0;
+}
+
+static int config_pad_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ return 0;
+}
+
+static int config_pad_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ const struct mdp_pad_subfrm *subfrm = &ctx->param->pad.subfrms[index];
+ phys_addr_t base = ctx->comp->reg_base;
+ u16 subsys_id = ctx->comp->subsys_id;
+
+ MM_REG_WRITE(cmd, subsys_id, base, VPP_PADDING0_PADDING_PIC_SIZE,
+ subfrm->pic_size, VPP_PADDING0_PADDING_CON_MASK);
+
+ return 0;
+}
+
+static const struct mdp_comp_ops pad_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_pad,
+ .config_frame = config_pad_frame,
+ .config_subfrm = config_pad_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
+
+static int init_tcc(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
+{
+ return 0;
+}
+
+static int config_tcc_frame(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd,
+ const struct v4l2_rect *compose)
+{
+ return 0;
+}
+
+static int config_tcc_subfrm(struct mdp_comp_ctx *ctx,
+ struct mmsys_cmdq_cmd *cmd, u32 index)
+{
+ return 0;
+}
+
+static const struct mdp_comp_ops tcc_ops = {
+ .get_comp_flag = get_comp_flag,
+ .init_comp = init_tcc,
+ .config_frame = config_tcc_frame,
+ .config_subfrm = config_tcc_subfrm,
+ .wait_comp_event = NULL,
+ .advance_subfrm = NULL,
+ .post_process = NULL,
+};
static int init_wrot(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
@@ -371,6 +1007,8 @@ static int init_wrot(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
/* Reset WROT */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0));
MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0));
+ /* Reset setting */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0));
MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0));
return 0;
@@ -384,6 +1022,8 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ bool comp;
+ u32 colorformat = ctx->outputs[0]->buffer.format.colorformat;
/* Write frame base address */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0],
@@ -392,9 +1032,38 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
0xFFFFFFFF);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, wrot->iova[2],
0xFFFFFFFF);
+
+ if (mdp_cfg) {
+ if (mdp_cfg->wrot_support_afbc) {
+ comp = MDP_COLOR_IS_COMPRESS(colorformat);
+ if (comp) {
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_FRAME_SIZE,
+ wrot->framesize, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_AFBC_YUVTRANS,
+ wrot->afbc_yuvtrans, 0x1);
+ }
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PVRIC, wrot->pvric, 0x03);
+ }
+
+ if (mdp_cfg->wrot_support_10bit) {
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT,
+ wrot->scan_10bit, 0x0000000F);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO,
+ wrot->pending_zero, 0x04000000);
+ }
+ if (mdp_cfg->mdp_version_6885)
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2,
+ wrot->bit_number, 0x00000007);
+ }
+
/* Write frame related registers */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, wrot->control,
0xF131510F);
+
+ /* Write pre-ultra threshold */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, wrot->pre_ultra,
+ 0x00FFFFFF);
+
/* Write frame Y pitch */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, wrot->stride[0],
0x0000FFFF);
@@ -447,7 +1116,6 @@ static int config_wrot_subfrm(struct mdp_comp_ctx *ctx,
0x1FFF1FFF);
MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, subfrm->clip_ofst,
0x1FFF1FFF);
-
MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
subfrm->main_buf, 0x1FFF7F00);
@@ -466,11 +1134,22 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
u8 subsys_id = ctx->comp->subsys_id;
int evt = -1;
- if (id == MDP_COMP_WROT0)
+ switch (id) {
+ case MDP_COMP_WROT0:
evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT0_DONE);
- else
- dev_err(dev, "Do not support WROT1_DONE event\n");
-
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT1_DONE);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT2_DONE);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT3_DONE);
+ break;
+ default:
+ dev_err(dev, "Invalid Engine!\n");
+ }
if (evt > 0)
MM_REG_WAIT(cmd, evt);
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 09/14] media: platform: mtk-mdp3: Add support MT8195
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add support MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 438 ++++++++++++++++--
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 345 +++++++++++++-
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 3 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 67 ++-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 2 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 6 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 86 +++-
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 2 +
8 files changed, 883 insertions(+), 66 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index 879a120f78d9..ce9326cc790f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -5,12 +5,15 @@
*/
#include <linux/platform_device.h>
+#include <linux/kernel.h>
#include "mtk-mdp3-cmdq.h"
#include "mtk-mdp3-comp.h"
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS
+#define BYTE_PER_MB_Y (4)
+#define BYTE_PER_MB_C (2)
struct mdp_path {
struct mdp_dev *mdp_dev;
@@ -26,12 +29,18 @@ struct mdp_path {
((ctx)->comp->ops && (ctx)->comp->ops->op)
#define call_op(ctx, op, ...) \
(has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0)
-
struct mdp_path_subfrm {
s32 mutex_id;
u32 mutex_mod;
+ u32 mutex_mod2;
s32 sofs[MDP_PATH_MAX_COMPS];
u32 num_sofs;
+
+ s32 mutex2_id;
+ u32 mutex2_mod;
+ u32 mutex2_mod2;
+ s32 sof2s[MDP_PATH_MAX_COMPS];
+ u32 num_sof2s;
};
static bool is_output_disable(const struct img_compparam *param, u32 count)
@@ -76,8 +85,11 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
- s32 mutex_id = -1;
+ struct mtk_mutex **mutex2 = path->mdp_dev->mdp_mutex2;
+ s32 mutex_id = MDP_PIPE_NONE;
+ s32 mutex2_id = MDP_PIPE_NONE;
u32 mutex_sof = 0;
+ u32 mutex2_sof = 0;
int index, j;
enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
@@ -85,57 +97,225 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
memset(subfrm, 0, sizeof(*subfrm));
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
public_id = path->comps[index].comp->public_id;
switch (public_id) {
- case MDP_COMP_AAL0:
+ case MDP_COMP_ISP_IMGI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI);
+ mutex_id = data->pipe_info[j].mutex_id;
+ break;
+ case MDP_COMP_WPEI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_CCORR0:
+ case MDP_COMP_WPEI2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_WDMA:
+ case MDP_COMP_RDMA0:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0;
break;
- case MDP_COMP_WROT0:
+ case MDP_COMP_VPP1_SOUT:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_VPP1_SOUT);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0;
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
break;
- case MDP_COMP_TDSHP0:
+ case MDP_COMP_FG0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0;
break;
- case MDP_COMP_RSZ1:
+ case MDP_COMP_STITCH:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1;
break;
case MDP_COMP_RSZ0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ0;
break;
- case MDP_COMP_RDMA0:
- j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_TDSHP0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0;
break;
- case MDP_COMP_ISP_IMGI:
- j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_COLOR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_WPEI:
- j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_OVL0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_WPEI2:
- j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_PAD0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_TCC0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_CCORR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_WDMA:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA;
+ break;
+ case MDP_COMP_WROT0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0;
+ break;
+ case MDP_COMP_SPLIT:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_SPLIT);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_SPLIT;
+ mutex2_sof = data->pipe_info[j].sof;
+ break;
+ case MDP_COMP_SPLIT2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_SPLIT2);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_SPLIT2;
+ mutex2_sof = data->pipe_info[j].sof;
+ break;
+ case MDP_COMP_RDMA1:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA1);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA1;
+ break;
+ case MDP_COMP_RDMA2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA2);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA2;
+ break;
+ case MDP_COMP_RDMA3:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA3);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA3;
+ break;
+ case MDP_COMP_VPP0_SOUT:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_VPP0_SOUT);
+ mutex2_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_TCC1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_FG1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_FG2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_FG3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_RSZ1:
+ if (data->comp_data[public_id].mutex.mmsys_id) {
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ1;
+ } else {
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1;
+ }
+ break;
+ case MDP_COMP_RSZ2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ2;
+ break;
+ case MDP_COMP_RSZ3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ3;
+ break;
+ case MDP_COMP_TDSHP1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP1;
+ break;
+ case MDP_COMP_TDSHP2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP2;
+ break;
+ case MDP_COMP_TDSHP3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP3;
+ break;
+ case MDP_COMP_COLOR1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_COLOR2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_COLOR3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_OVL1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_PAD1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_PAD2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_PAD3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_WROT1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT1;
+ break;
+ case MDP_COMP_WROT2:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT2;
+ break;
+ case MDP_COMP_WROT3:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT3;
+ break;
+ case MDP_COMP_VDO0DL0:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_VDO1DL0:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_VDO0DL1:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_VDO1DL1:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
break;
default:
break;
@@ -143,17 +323,23 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
}
subfrm->mutex_id = mutex_id;
- if (-1 == mutex_id) {
+ subfrm->mutex2_id = mutex2_id;
+
+ if (mutex_id == MDP_PIPE_NONE && mutex2_id == MDP_PIPE_NONE) {
dev_err(dev, "No mutex assigned");
return -EINVAL;
}
/* Set mutex modules */
- if (subfrm->mutex_mod) {
+ if (subfrm->mutex_mod || subfrm->mutex_mod2) {
mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
- 0, mutex_sof, cmd);
+ subfrm->mutex_mod2, mutex_sof, cmd);
}
+ if (subfrm->mutex2_mod || subfrm->mutex2_mod2) {
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id], subfrm->mutex2_mod,
+ subfrm->mutex2_mod2, mutex2_sof, cmd);
+ }
return 0;
}
@@ -163,14 +349,16 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
{
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
+ struct mtk_mutex **mutex2 = path->mdp_dev->mdp_mutex2;
s32 mutex_id = subfrm->mutex_id;
+ s32 mutex2_id = subfrm->mutex2_id;
- if (-1 == mutex_id) {
+ if (mutex_id == MDP_PIPE_NONE && mutex2_id == MDP_PIPE_NONE) {
dev_err(dev, "Incorrect mutex id");
return -EINVAL;
}
- if (subfrm->mutex_mod) {
+ if (subfrm->mutex_mod || subfrm->mutex_mod2) {
int index, evt;
/* Wait WROT SRAM shared to DISP RDMA */
@@ -235,6 +423,71 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
MM_REG_WAIT(cmd, evt);
}
}
+
+ if (subfrm->mutex2_mod || subfrm->mutex2_mod2) {
+ int index, evt;
+
+ /* Clear SOF event for each engine */
+ for (index = 0; index < subfrm->num_sof2s; index++) {
+ switch (subfrm->sof2s[index]) {
+ case MDP_COMP_RDMA1:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA1_SOF);
+ break;
+ case MDP_COMP_RDMA2:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA2_SOF);
+ break;
+ case MDP_COMP_RDMA3:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA3_SOF);
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT1_SOF);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT2_SOF);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT3_SOF);
+ break;
+ default:
+ evt = -1;
+ break;
+ }
+ if (evt > 0)
+ MM_REG_CLEAR(cmd, evt);
+ }
+
+ /* Enable the mutex */
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+
+ /* Wait SOF events and clear mutex modules (optional) */
+ for (index = 0; index < subfrm->num_sof2s; index++) {
+ switch (subfrm->sof2s[index]) {
+ case MDP_COMP_RDMA1:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA1_SOF);
+ break;
+ case MDP_COMP_RDMA2:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA2_SOF);
+ break;
+ case MDP_COMP_RDMA3:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA3_SOF);
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT1_SOF);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT2_SOF);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT3_SOF);
+ break;
+ default:
+ evt = -1;
+ break;
+ }
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
+ }
+ }
return 0;
}
@@ -247,6 +500,9 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path)
return -EINVAL;
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ret = mdp_comp_ctx_init(mdp, &path->comps[index],
&config->components[index],
path->param);
@@ -276,13 +532,21 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
/* Enable mux settings */
for (index = 0; index < ctrl->num_sets; index++) {
set = &ctrl->sets[index];
- mmsys_dev = path->mdp_dev->mdp_mmsys;
+ if (data->mdp_cfg->mdp_version_8195) {
+ if (set->vpp_id)
+ mmsys_dev = path->mdp_dev->mdp_mmsys2;
+ else
+ mmsys_dev = path->mdp_dev->mdp_mmsys;
+ }
mtk_mmsys_write_reg_by_cmdq(mmsys_dev, cmd,
set->reg, set->value, 0xFFFFFFFF);
}
/* Config sub-frame information */
for (index = (config->num_components - 1); index >= 0; index--) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
@@ -296,6 +560,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
return ret;
/* Wait components done */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
@@ -305,6 +572,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
}
/* Advance to the next sub-frame */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, advance_subfrm, cmd, count);
if (ret)
@@ -313,7 +583,12 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
/* Disable mux settings */
for (index = 0; index < ctrl->num_sets; index++) {
set = &ctrl->sets[index];
- mmsys_dev = path->mdp_dev->mdp_mmsys;
+ if (data->mdp_cfg->mdp_version_8195) {
+ if (set->vpp_id)
+ mmsys_dev = path->mdp_dev->mdp_mmsys2;
+ else
+ mmsys_dev = path->mdp_dev->mdp_mmsys;
+ }
mtk_mmsys_write_reg_by_cmdq(mmsys_dev, cmd,
set->reg, 0, 0xFFFFFFFF);
@@ -332,6 +607,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
/* Config path frame */
/* Reset components */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, init_comp, cmd);
if (ret)
@@ -342,6 +620,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
const struct v4l2_rect *compose =
path->composes[ctx->param->outputs[0]];
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, config_frame, cmd, compose);
if (ret)
@@ -356,6 +637,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
}
/* Post processing information */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, post_process, cmd);
if (ret)
@@ -364,6 +648,60 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
return 0;
}
+static int mdp_hyfbc_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
+ struct mdp_path *path, struct mdp_cmdq_param *param)
+{
+ struct device *dev = &mdp->pdev->dev;
+ const struct img_config *config = path->config;
+ struct mdp_m2m_ctx *ctx;
+ struct mdp_comp_ctx *comp_ctx = &path->comps[0];
+ const struct mdp_rdma_data *rdma = &comp_ctx->param->rdma;
+ struct hyfbc_init_info hyfbc;
+ struct mdp_frame *frame;
+ u32 wrot_id;
+ int ret;
+
+ ctx = (struct mdp_m2m_ctx *)param->mdp_ctx;
+ frame = &ctx->curr_param.output;
+
+ if (!MDP_COLOR_IS_HYFBC_COMPRESS(frame->mdp_fmt->mdp_color) ||
+ frame->format.fmt.pix_mp.width % 32 == 0)
+ return 0;
+
+ // First engine should be rdma engine
+ if (!is_rdma(mdp, config->components[0].type)) {
+ dev_dbg(dev, "Not RDMA engine id, end patch.");
+ return 0;
+ }
+
+ wrot_id = config->components[(config->num_components - 1)].type;
+
+ hyfbc.is10b = (MDP_COLOR_IS_10BIT(frame->mdp_fmt->mdp_color));
+ hyfbc.width_in_mb = DIV_ROUND_UP(frame->format.fmt.pix_mp.width, 16);
+ hyfbc.height_in_mb = DIV_ROUND_UP(frame->format.fmt.pix_mp.height, 16);
+ hyfbc.w_stride_in_mb = DIV_ROUND_UP(ALIGN(frame->stride.width, 32), 16);
+ hyfbc.h_stride_in_mb = DIV_ROUND_UP(ALIGN(frame->stride.height, 32), 16);
+ hyfbc.byte_per_mb = BYTE_PER_MB_Y;
+ hyfbc.pa_base = rdma->ufo_dec_y;
+
+ ret = mdp_hyfbc_init(mdp, cmd, &hyfbc, wrot_id);
+ if (ret) {
+ dev_err(dev, "mdp_hyfbc_init: y patch fail.");
+ return ret;
+ }
+
+ hyfbc.byte_per_mb = BYTE_PER_MB_C;
+ hyfbc.pa_base = rdma->ufo_dec_c;
+
+ ret = mdp_hyfbc_init(mdp, cmd, &hyfbc, wrot_id);
+ if (ret) {
+ dev_err(dev, "mdp_hyfbc_init: c patch fail.");
+ return ret;
+ }
+
+ return 0;
+}
+
static void mdp_auto_release_work(struct work_struct *work)
{
struct mdp_cmdq_cb_param *cb_param;
@@ -376,6 +714,10 @@ static void mdp_auto_release_work(struct work_struct *work)
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -419,6 +761,11 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
dev_err(dev, "%s:queue_work fail!\n", __func__);
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -481,8 +828,22 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
- for (i = 0; i < param->config->num_components; i++)
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_prepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ for (i = 0; i < param->config->num_components; i++) {
+ if (is_dummy_engine(mdp, path->config->components[i].type))
+ continue;
+
mdp_comp_clock_on(&mdp->pdev->dev, path->comps[i].comp);
+ }
+
+ if (mdp->mdp_data->mdp_cfg->mdp_version_8195) {
+ ret = mdp_hyfbc_config(mdp, &cmd, path, param);
+ if (ret)
+ goto err_destroy_pkt;
+ }
ret = mdp_path_config(mdp, &cmd, path);
if (ret) {
@@ -503,9 +864,13 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
goto err_destroy_pkt;
}
- for (i = 0; i < param->config->num_components; i++)
+ for (i = 0; i < param->config->num_components; i++) {
+ if (is_dummy_engine(mdp, path->config->components[i].type))
+ continue;
+
memcpy(&comps[i], path->comps[i].comp,
sizeof(struct mdp_comp));
+ }
cb_param->mdp = mdp;
cb_param->user_cmdq_cb = param->cmdq_cb;
cb_param->user_cb_data = param->cb_data;
@@ -528,6 +893,11 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
err_clock_off:
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
err_destroy_pkt:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index 8ca9c7e325e1..3d5cbd0e3805 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -27,6 +27,10 @@
#include "mdp_reg_wdma.h"
#include "mdp_reg_isp.h"
+#define is_wrot(id) \
+ ((mdp)->mdp_data->comp_data[id].match.type == MDP_COMP_TYPE_WROT)
+#define byte2pixel(byte) ((byte) / 2)
+
s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
{
if (!mdp_dev)
@@ -57,6 +61,20 @@ enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 inner_id)
return public_id;
}
+bool is_dummy_engine(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id public_id = get_comp_public_id(mdp_dev, inner_id);
+
+ return (mdp_dev->mdp_data->comp_data[public_id].match.type == MDP_COMP_TYPE_DUMMY);
+}
+
+bool is_rdma(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id public_id = get_comp_public_id(mdp_dev, inner_id);
+
+ return (mdp_dev->mdp_data->comp_data[public_id].match.type == MDP_COMP_TYPE_RDMA);
+}
+
static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ctx *ctx)
{
if (!ctx)
@@ -423,14 +441,40 @@ static const struct mdp_comp_ops fg_ops = {
static int init_rsz(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
+ const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 value, mask, alias_id;
/* Reset RSZ */
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16));
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16));
/* Enable RSZ */
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0));
+
+ if (mdp_cfg && mdp_cfg->mdp_version_8195) {
+ const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data;
+
+ value = (1 << 25);
+ mask = (1 << 25);
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_2ND_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+
+ value = (1 << 4 | 1 << 5);
+ mask = (1 << 4 | 1 << 5);
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_1ST_DIS1];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_2ND_DIS1];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+ }
return 0;
}
@@ -501,6 +545,48 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx,
MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, subfrm->clip,
0xFFFFFFFF);
+ if (mdp_cfg && mdp_cfg->mdp_version_8195) {
+ struct mdp_comp *merge;
+ const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data;
+ enum mtk_mdp_comp_id id = ctx->comp->public_id;
+ u32 alias_id;
+
+ switch (id) {
+ case MDP_COMP_RSZ2:
+ merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE2];
+
+ alias_id = data->config_table[CONFIG_SVPP2_BUF_BF_RSZ_SWITCH];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id,
+ subfrm->rsz_switch, 0xFFFFFFFF);
+ break;
+ case MDP_COMP_RSZ3:
+ merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE3];
+
+ alias_id = data->config_table[CONFIG_SVPP3_BUF_BF_RSZ_SWITCH];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id,
+ subfrm->rsz_switch, 0xFFFFFFFF);
+ break;
+ default:
+ goto subfrm_done;
+ }
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_0, subfrm->merge_cfg, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_4, subfrm->merge_cfg, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_24, subfrm->merge_cfg, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_25, subfrm->merge_cfg, 0xFFFFFFFF);
+
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_12, 0x1, 0xFFFFFFFF); // bypass mode
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_ENABLE, 0x1, 0xFFFFFFFF);
+ }
+
+subfrm_done:
return 0;
}
@@ -1020,10 +1106,12 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
{
const struct mdp_wrot_data *wrot = &ctx->param->wrot;
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
bool comp;
u32 colorformat = ctx->outputs[0]->buffer.format.colorformat;
+ u32 alias_id;
/* Write frame base address */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0],
@@ -1084,11 +1172,36 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
if (wrot->fifo_test != 0)
MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST,
wrot->fifo_test, 0xFFF);
- /* Filter enable */
- if (mdp_cfg && mdp_cfg->wrot_filter_constraint)
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
- wrot->filter, 0x77);
-
+ if (mdp_cfg) {
+ /* Filter enable */
+ if (mdp_cfg->wrot_filter_constraint)
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
+ wrot->filter, 0x77);
+
+ if (mdp_cfg->mdp_version_8195) {
+ /* Turn off WROT dma dcm */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN,
+ (0x1 << 23) + (0x1 << 20), 0x900000);
+
+ if (wrot->vpp02vpp1) {
+ // Disable DCM (VPP02VPP1_RELAY)
+ alias_id = data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys,
+ cmd, alias_id, 0x4000,
+ 0xFFFFFFFF);
+ // Set default size
+ alias_id = data->config_table[CONFIG_VPP0_DL_IRELAY_WR];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, 0x0,
+ 0xFFFFFFFF);
+ } else {
+ alias_id = data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys,
+ cmd, alias_id, 0x0,
+ 0xFFFFFFFF);
+ }
+ }
+ }
return 0;
}
@@ -1566,17 +1679,30 @@ static const struct mdp_comp_ops camin_ops = {
};
static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = {
- [MDP_COMP_TYPE_RDMA] = &rdma_ops,
- [MDP_COMP_TYPE_RSZ] = &rsz_ops,
- [MDP_COMP_TYPE_WROT] = &wrot_ops,
- [MDP_COMP_TYPE_WDMA] = &wdma_ops,
- [MDP_COMP_TYPE_PATH1] = NULL,
- [MDP_COMP_TYPE_PATH2] = NULL,
- [MDP_COMP_TYPE_CCORR] = &ccorr_ops,
- [MDP_COMP_TYPE_IMGI] = &imgi_ops,
- [MDP_COMP_TYPE_EXTO] = NULL,
- [MDP_COMP_TYPE_DL_PATH1] = &camin_ops,
- [MDP_COMP_TYPE_DL_PATH2] = &camin_ops,
+ [MDP_COMP_TYPE_WPEI] = &camin_ops,
+ [MDP_COMP_TYPE_SPLIT] = &split_ops,
+ [MDP_COMP_TYPE_STITCH] = &stitch_ops,
+ [MDP_COMP_TYPE_RDMA] = &rdma_ops,
+ [MDP_COMP_TYPE_FG] = &fg_ops,
+ [MDP_COMP_TYPE_HDR] = &hdr_ops,
+ [MDP_COMP_TYPE_AAL] = &aal_ops,
+ [MDP_COMP_TYPE_RSZ] = &rsz_ops,
+ [MDP_COMP_TYPE_TDSHP] = &tdshp_ops,
+ [MDP_COMP_TYPE_COLOR] = &color_ops,
+ [MDP_COMP_TYPE_OVL] = &ovl_ops,
+ [MDP_COMP_TYPE_PAD] = &pad_ops,
+ [MDP_COMP_TYPE_TCC] = &tcc_ops,
+ [MDP_COMP_TYPE_WROT] = &wrot_ops,
+ [MDP_COMP_TYPE_WDMA] = &wdma_ops,
+ [MDP_COMP_TYPE_MERGE] = NULL,
+ [MDP_COMP_TYPE_PATH1] = NULL,
+ [MDP_COMP_TYPE_PATH2] = NULL,
+ [MDP_COMP_TYPE_CCORR] = &ccorr_ops,
+ [MDP_COMP_TYPE_IMGI] = &imgi_ops,
+ [MDP_COMP_TYPE_EXTO] = NULL,
+ [MDP_COMP_TYPE_DL_PATH1] = &camin_ops,
+ [MDP_COMP_TYPE_DL_PATH2] = &camin_ops,
+ [MDP_COMP_TYPE_DUMMY] = NULL,
};
static const struct of_device_id mdp_comp_dt_ids[] = {
@@ -2070,3 +2196,190 @@ int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
ctx->outputs[i] = &frame->outputs[param->outputs[i]];
return 0;
}
+
+int mdp_hyfbc_init(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
+ struct hyfbc_init_info *hyfbc, u32 wrot)
+{
+ struct mtk_mutex **mutex = mdp->mdp_mutex;
+ struct mtk_mutex **mutex2 = mdp->mdp_mutex2;
+ enum mtk_mdp_comp_id mtk_wrot = MDP_COMP_NONE;
+ phys_addr_t base;
+ u16 subsys_id;
+ u32 offset;
+ u32 mutex_id;
+ u32 mutex2_id;
+ u32 alias_id;
+ int evt;
+
+ mtk_wrot = get_comp_public_id(mdp, wrot);
+ if (!is_wrot(mtk_wrot)) {
+ dev_err(&mdp->pdev->dev, "Invalid wrot inner id %d", wrot);
+ return -EINVAL;
+ }
+
+ base = mdp->comp[mtk_wrot]->reg_base;
+ subsys_id = mdp->comp[mtk_wrot]->subsys_id;
+ offset = hyfbc->width_in_mb * hyfbc->byte_per_mb;
+
+ /* Reset WROT */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST,
+ 0x01, 0x00000001);
+ MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT,
+ 0x01, 0x00000001);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST,
+ 0x00, 0x00000001);
+ MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT,
+ 0x00, 0x00000001);
+
+ /* Write frame base address */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR,
+ (hyfbc->pa_base + offset), 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C,
+ 0x0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V,
+ 0x0, 0xFFFFFFFF);
+
+ /* Write frame related registers */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL,
+ 0x5020, 0xF131512F);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BKGD,
+ ((hyfbc->is10b) ? 0xC8E438 : 0x18f4f8), 0xFFFFFFFF);
+
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT,
+ 0x0, 0x0000000F);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO,
+ 0x0, 0x04000000);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2,
+ 0x0, 0x00000007);
+
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PVRIC,
+ 0x0, 0x03);
+ /* Write pre-ultra threshold */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA,
+ 0x8804c, 0x00FFFFFF);
+ /* Write frame Y pitch */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE,
+ (hyfbc->w_stride_in_mb * hyfbc->byte_per_mb), 0x0000FFFF);
+ /* Write frame UV pitch */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C,
+ 0x0, 0x0000FFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V,
+ 0x0, 0x0000FFFF);
+ /* Write matrix control */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL,
+ 0x60, 0x000000F3);
+
+ /* Set the fixed ALPHA as 0xFF */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER,
+ 0xFF000000, 0xFF000000);
+ /* Set VIDO_EOL_SEL */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1,
+ 0x80000000, 0x80000000);
+ /* Set VIDO_FIFO_TEST */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST,
+ 0x200, 0x00000FFF);
+
+ /* Filter enable */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
+ 0x0, 0x00000077);
+
+ /* Turn off WROT dma dcm */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN,
+ (0x1 << 23) + (0x1 << 20), 0x00900000);
+
+ alias_id = mdp->mdp_data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(mdp->mdp_mmsys, cmd,
+ alias_id, 0x0, 0xFFFFFFFF);
+
+ /* Set mutex modules */
+ switch (mtk_wrot) {
+ case MDP_COMP_WROT0:
+ mutex_id = 2;
+ mtk_mutex_add_mod_by_cmdq(mutex[mutex_id],
+ 0x800, 0x0, 0x0, cmd);
+ break;
+ case MDP_COMP_WROT1:
+ mutex2_id = 1;
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id],
+ 0x80000000, 0x0, 0x0, cmd);
+ break;
+ case MDP_COMP_WROT2:
+ mutex2_id = 2;
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id],
+ 0x0, 0x1, 0x0, cmd);
+ break;
+ case MDP_COMP_WROT3:
+ mutex2_id = 3;
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id],
+ 0x0, 0x2, 0x0, cmd);
+ break;
+ default:
+ break;
+ }
+
+ /* Write Y pixel offset */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR,
+ 0x0, 0x0FFFFFFF);
+ /* Write U pixel offset */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C,
+ 0x0, 0x0FFFFFFF);
+ /* Write V pixel offset */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V,
+ 0x0, 0x0FFFFFFF);
+ /* Write source size */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE,
+ (hyfbc->height_in_mb << 16) | byte2pixel(hyfbc->byte_per_mb), 0xFFFFFFFF);
+ /* Write target size */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE,
+ (hyfbc->height_in_mb << 16) | byte2pixel(hyfbc->byte_per_mb), 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, 0x0,
+ 0xFFFFFFFF);
+
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
+ ((byte2pixel(hyfbc->byte_per_mb) << 16) | 0x400), 0xFFFF7F00);
+
+ /* Enable WROT */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x01, 0x00000001);
+
+ switch (mtk_wrot) {
+ case MDP_COMP_WROT0:
+ evt = mdp_get_event_idx(mdp, WROT0_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex[mutex_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT0_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(mdp, WROT1_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT1_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(mdp, WROT2_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT2_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(mdp, WROT3_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT3_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ default:
+ break;
+ }
+
+ /* Disable WROT */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x00, 0x00000001);
+
+ return 0;
+}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
index 05a60771d4bc..391e9014dc99 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
@@ -222,7 +222,8 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num);
int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_compparam *param,
const struct img_ipi_frameparam *frame);
-
+int mdp_hyfbc_init(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
+ struct hyfbc_init_info *hyfbc, u32 wrot);
int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event);
#endif /* __MTK_MDP3_COMP_H__ */
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index bef8da6fff1c..d8161be8c556 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -44,6 +44,9 @@ static const struct of_device_id mdp_of_ids[] = {
{ .compatible = "mediatek,mt8183-mdp3",
.data = &mt8183_mdp_driver_data,
},
+ { .compatible = "mediatek,mt8195-mdp3",
+ .data = &mt8195_mdp_driver_data,
+ },
{},
};
MODULE_DEVICE_TABLE(of, mdp_of_ids);
@@ -150,7 +153,7 @@ static int mdp_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mdp_dev *mdp;
struct device_node *mdp_node;
- struct platform_device *mm_pdev;
+ struct platform_device *mm_pdev, *mm_pdev2;
u32 event_ofst;
int ret, i, mutex_id;
@@ -162,13 +165,28 @@ static int mdp_probe(struct platform_device *pdev)
mdp->pdev = pdev;
mdp->mdp_data = of_device_get_match_data(&pdev->dev);
+
+ if (of_get_property(pdev->dev.of_node, "dma-ranges", NULL))
+ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
+
mm_pdev = __get_pdev_by_name(pdev, "mediatek,mmsys");
if (!mm_pdev) {
- ret = -ENODEV;
- goto err_return;
+ if (mdp->mdp_data->mdp_cfg->support_multi_larb) {
+ platform_set_drvdata(pdev, mdp);
+ goto success_return;
+ } else {
+ ret = -ENODEV;
+ goto err_return;
+ }
}
mdp->mdp_mmsys = &mm_pdev->dev;
+ mm_pdev2 = __get_pdev_by_name(pdev, "mediatek,mmsys2");
+ if (!mm_pdev2)
+ dev_err(dev, "Failed to get mdp mmsys2\n");
+ else
+ mdp->mdp_mmsys2 = &mm_pdev2->dev;
+
mdp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,mm-mutex", 0);
if (!mdp_node) {
ret = -ENODEV;
@@ -200,17 +218,43 @@ static int mdp_probe(struct platform_device *pdev)
goto err_return;
}
+ mdp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,mm-mutex2", 0);
+ if (!mdp_node) {
+ dev_err(dev, "Failed to get mdp mm-mutex2\n");
+ } else {
+ mm_pdev2 = of_find_device_by_node(mdp_node);
+ of_node_put(mdp_node);
+ if (WARN_ON(!mm_pdev2)) {
+ ret = -ENODEV;
+ goto err_return;
+ }
+ }
+
for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) {
mutex_id = mdp->mdp_data->pipe_info[i].mutex_id;
- if (mdp->mdp_mutex[mutex_id])
- continue;
-
- mdp->mdp_mutex[mutex_id] =
- mtk_mutex_mdp_get(&mm_pdev->dev, mdp->mdp_data->pipe_info[i].pipe_id);
- if (!mdp->mdp_mutex[mutex_id]) {
- ret = -ENODEV;
- goto err_return;
+ if (mdp->mdp_data->pipe_info[i].mmsys_id != 0) {
+ if (mdp->mdp_mutex2[mutex_id])
+ continue;
+ mdp->mdp_mutex2[mutex_id] =
+ mtk_mutex_mdp_get(&mm_pdev2->dev,
+ mdp->mdp_data->pipe_info[i].pipe_id);
+
+ if (!mdp->mdp_mutex2[mutex_id]) {
+ ret = -ENODEV;
+ goto err_return;
+ }
+ } else {
+ if (mdp->mdp_mutex[mutex_id])
+ continue;
+ mdp->mdp_mutex[mutex_id] =
+ mtk_mutex_mdp_get(&mm_pdev->dev,
+ mdp->mdp_data->pipe_info[i].pipe_id);
+
+ if (!mdp->mdp_mutex[mutex_id]) {
+ ret = -ENODEV;
+ goto err_return;
+ }
}
}
@@ -273,6 +317,7 @@ static int mdp_probe(struct platform_device *pdev)
goto err_unregister_device;
}
+success_return:
dev_dbg(dev, "mdp-%d registered successfully\n", pdev->id);
return 0;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index c668e317f947..8ee70763a18f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -60,7 +60,9 @@ struct mtk_mdp_driver_data {
struct mdp_dev {
struct platform_device *pdev;
struct device *mdp_mmsys;
+ struct device *mdp_mmsys2;
struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX];
+ struct mtk_mutex *mdp_mutex2[MDP_PIPE_MAX];
struct mdp_comp *comp[MDP_MAX_COMP_COUNT];
const struct mtk_mdp_driver_data *mdp_data;
s32 event[MDP_MAX_EVENT_COUNT];
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index ca1c19c41950..1e749bb2b338 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -90,6 +90,7 @@ static void mdp_m2m_worker(struct work_struct *work)
param.type = ctx->curr_param.type;
param.num_inputs = 1;
param.num_outputs = 1;
+ param.frame_change = (ctx->frame_count[MDP_M2M_SRC] == 0);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
@@ -328,6 +329,11 @@ static int mdp_m2m_s_fmt_mplane(struct file *file, void *fh,
ctx->curr_param.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
ctx->curr_param.quant = f->fmt.pix_mp.quantization;
ctx->curr_param.xfer_func = f->fmt.pix_mp.xfer_func;
+
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(fmt->mdp_color)) {
+ frame->stride.width = ((f->fmt.pix_mp.width + 63) >> 6) << 6;
+ frame->stride.height = ((f->fmt.pix_mp.height + 31) >> 5) << 5;
+ }
} else {
capture->compose.left = 0;
capture->compose.top = 0;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index 83e91735202b..8c2b74c67273 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -147,6 +147,47 @@ int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f)
return 0;
}
+static u32 mdp_fmt_get_hyfbc_plane_size(u32 width,
+ u32 height, u32 color, unsigned int plane)
+{
+ u32 y_data_size = 0;
+ u32 c_data_size = 0;
+ u32 y_header_size = 0;
+ u32 c_header_size = 0;
+ u32 y_data_ofst = 0;
+ u32 c_data_ofst = 0;
+ u32 c_header_ofst = 0;
+
+ y_data_size = (((width + 63) >> 6) << 6) * (((height + 63) >> 6) << 6);
+ y_header_size = y_data_size >> 6;
+ if (MDP_COLOR_IS_10BIT_PACKED(color))
+ y_data_size = (y_data_size * 6) >> 2;
+
+ c_data_size = y_data_size >> 1;
+ c_header_size = (((y_header_size >> 1) + 63) >> 6) << 6;
+
+ // Setup source buffer base
+ y_data_ofst = ((y_header_size + 4095) >> 12) << 12; // align 4k
+ c_data_ofst = ((y_data_ofst + y_data_size + c_header_size + 4095) >> 12) << 12; // align 4k
+ c_header_ofst = c_data_ofst - c_header_size;
+
+ if (plane == 0)
+ return c_header_ofst;
+ else
+ return (c_data_ofst + c_data_size);
+}
+
+static u32 mdp_fmt_get_afbc_plane_size(u32 width, u32 height, u32 color)
+{
+ u32 align_w = ((width + 31) >> 5) << 5;
+ u32 align_h = ((height + 31) >> 5) << 5;
+
+ if (MDP_COLOR_IS_10BIT_PACKED(color))
+ return ((align_w >> 4) * (align_h >> 4) * (16 + 512));
+ else
+ return ((align_w >> 4) * (align_h >> 4) * (16 + 384));
+}
+
const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
struct mdp_frameparam *param,
u32 ctx_id)
@@ -211,11 +252,17 @@ const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
bpl = min_bpl;
si = (bpl * pix_mp->height * fmt->depth[i]) / fmt->row_depth[i];
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(fmt->mdp_color)) {
+ si = mdp_fmt_get_hyfbc_plane_size(pix_mp->width,
+ pix_mp->height, fmt->mdp_color, i);
+ } else if (MDP_COLOR_IS_COMPRESS(fmt->mdp_color)) {
+ si = mdp_fmt_get_afbc_plane_size(pix_mp->width,
+ pix_mp->height, fmt->mdp_color);
+ }
+
pix_mp->plane_fmt[i].bytesperline = bpl;
if (pix_mp->plane_fmt[i].sizeimage < si)
pix_mp->plane_fmt[i].sizeimage = si;
- dev_dbg(dev, "%d: p%u, bpl:%u (%u), sizeimage:%u (%u)", ctx_id,
- i, bpl, min_bpl, pix_mp->plane_fmt[i].sizeimage, si);
}
return fmt;
@@ -324,8 +371,14 @@ static u32 mdp_fmt_get_stride(const struct mdp_format *fmt,
enum mdp_color c = fmt->mdp_color;
u32 stride;
- stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c))
- / fmt->row_depth[0];
+ if (MDP_COLOR_IS_COMPRESS(c)) {
+ bytesperline = ((bytesperline + 31) >> 5) << 5;
+ stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c))
+ / fmt->row_depth[0];
+ } else {
+ stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c))
+ / fmt->row_depth[0];
+ }
if (plane == 0)
return stride;
if (plane < MDP_COLOR_GET_PLANE_COUNT(c)) {
@@ -398,6 +451,19 @@ static void mdp_prepare_buffer(struct img_image_buffer *b,
mdp_fmt_get_plane_size(frame->mdp_fmt, stride,
pix_mp->height, i) -
vb->planes[i].data_offset;
+
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_hyfbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat, i);
+ } else if (MDP_COLOR_IS_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_afbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat);
+ }
+
b->iova[i] = vb2_dma_contig_plane_dma_addr(vb, i) +
vb->planes[i].data_offset;
}
@@ -409,6 +475,18 @@ static void mdp_prepare_buffer(struct img_image_buffer *b,
b->format.plane_fmt[i].size =
mdp_fmt_get_plane_size(frame->mdp_fmt, stride,
pix_mp->height, i);
+
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_hyfbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat, i);
+ } else if (MDP_COLOR_IS_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_afbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat);
+ }
b->iova[i] = b->iova[i - 1] + b->format.plane_fmt[i - 1].size;
}
b->usage = frame->usage;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 4a25f86bfaa5..1ef32b747233 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -355,6 +355,8 @@ struct mdp_frame {
u32 dre:1;
u32 sharpness:1;
u32 dither:1;
+ /* H and V stride, only for HYFBC format */
+ struct v4l2_rect stride;
};
static inline bool mdp_target_is_crop(u32 target)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 09/14] media: platform: mtk-mdp3: Add support MT8195
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add support MT8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 438 ++++++++++++++++--
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 345 +++++++++++++-
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 3 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 67 ++-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 2 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 6 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 86 +++-
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 2 +
8 files changed, 883 insertions(+), 66 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index 879a120f78d9..ce9326cc790f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -5,12 +5,15 @@
*/
#include <linux/platform_device.h>
+#include <linux/kernel.h>
#include "mtk-mdp3-cmdq.h"
#include "mtk-mdp3-comp.h"
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS
+#define BYTE_PER_MB_Y (4)
+#define BYTE_PER_MB_C (2)
struct mdp_path {
struct mdp_dev *mdp_dev;
@@ -26,12 +29,18 @@ struct mdp_path {
((ctx)->comp->ops && (ctx)->comp->ops->op)
#define call_op(ctx, op, ...) \
(has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0)
-
struct mdp_path_subfrm {
s32 mutex_id;
u32 mutex_mod;
+ u32 mutex_mod2;
s32 sofs[MDP_PATH_MAX_COMPS];
u32 num_sofs;
+
+ s32 mutex2_id;
+ u32 mutex2_mod;
+ u32 mutex2_mod2;
+ s32 sof2s[MDP_PATH_MAX_COMPS];
+ u32 num_sof2s;
};
static bool is_output_disable(const struct img_compparam *param, u32 count)
@@ -76,8 +85,11 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
- s32 mutex_id = -1;
+ struct mtk_mutex **mutex2 = path->mdp_dev->mdp_mutex2;
+ s32 mutex_id = MDP_PIPE_NONE;
+ s32 mutex2_id = MDP_PIPE_NONE;
u32 mutex_sof = 0;
+ u32 mutex2_sof = 0;
int index, j;
enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;
@@ -85,57 +97,225 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
memset(subfrm, 0, sizeof(*subfrm));
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
public_id = path->comps[index].comp->public_id;
switch (public_id) {
- case MDP_COMP_AAL0:
+ case MDP_COMP_ISP_IMGI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI);
+ mutex_id = data->pipe_info[j].mutex_id;
+ break;
+ case MDP_COMP_WPEI:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_CCORR0:
+ case MDP_COMP_WPEI2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_WDMA:
+ case MDP_COMP_RDMA0:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0;
break;
- case MDP_COMP_WROT0:
+ case MDP_COMP_VPP1_SOUT:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_VPP1_SOUT);
+ mutex_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0;
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
break;
- case MDP_COMP_TDSHP0:
+ case MDP_COMP_FG0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0;
break;
- case MDP_COMP_RSZ1:
+ case MDP_COMP_STITCH:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1;
break;
case MDP_COMP_RSZ0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ0;
break;
- case MDP_COMP_RDMA0:
- j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_TDSHP0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
- subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0;
break;
- case MDP_COMP_ISP_IMGI:
- j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_COLOR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_WPEI:
- j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_OVL0:
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
break;
- case MDP_COMP_WPEI2:
- j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2);
- mutex_id = data->pipe_info[j].mutex_id;
+ case MDP_COMP_PAD0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_TCC0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_CCORR0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_WDMA:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA;
+ break;
+ case MDP_COMP_WROT0:
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0;
+ break;
+ case MDP_COMP_SPLIT:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_SPLIT);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_SPLIT;
+ mutex2_sof = data->pipe_info[j].sof;
+ break;
+ case MDP_COMP_SPLIT2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_SPLIT2);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_SPLIT2;
+ mutex2_sof = data->pipe_info[j].sof;
+ break;
+ case MDP_COMP_RDMA1:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA1);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA1;
+ break;
+ case MDP_COMP_RDMA2:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA2);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA2;
+ break;
+ case MDP_COMP_RDMA3:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA3);
+ mutex2_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RDMA3;
+ break;
+ case MDP_COMP_VPP0_SOUT:
+ j = mdp_get_mutex_idx(data, MDP_PIPE_VPP0_SOUT);
+ mutex2_id = data->pipe_info[j].mutex_id;
subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_TCC1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_FG1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_FG2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_FG3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_HDR3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_AAL3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_RSZ1:
+ if (data->comp_data[public_id].mutex.mmsys_id) {
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ1;
+ } else {
+ subfrm->mutex_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1;
+ }
+ break;
+ case MDP_COMP_RSZ2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ2;
+ break;
+ case MDP_COMP_RSZ3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_RSZ3;
+ break;
+ case MDP_COMP_TDSHP1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP1;
+ break;
+ case MDP_COMP_TDSHP2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP2;
+ break;
+ case MDP_COMP_TDSHP3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_TDSHP3;
+ break;
+ case MDP_COMP_COLOR1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_COLOR2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_COLOR3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_OVL1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_PAD1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_PAD2:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_PAD3:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ break;
+ case MDP_COMP_WROT1:
+ subfrm->mutex2_mod |= data->comp_data[public_id].mutex.mod;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT1;
+ break;
+ case MDP_COMP_WROT2:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT2;
+ break;
+ case MDP_COMP_WROT3:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ subfrm->sof2s[subfrm->num_sof2s++] = MDP_COMP_WROT3;
+ break;
+ case MDP_COMP_VDO0DL0:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_VDO1DL0:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_VDO0DL1:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
+ break;
+ case MDP_COMP_VDO1DL1:
+ subfrm->mutex2_mod2 |= data->comp_data[public_id].mutex.mod2;
break;
default:
break;
@@ -143,17 +323,23 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
}
subfrm->mutex_id = mutex_id;
- if (-1 == mutex_id) {
+ subfrm->mutex2_id = mutex2_id;
+
+ if (mutex_id == MDP_PIPE_NONE && mutex2_id == MDP_PIPE_NONE) {
dev_err(dev, "No mutex assigned");
return -EINVAL;
}
/* Set mutex modules */
- if (subfrm->mutex_mod) {
+ if (subfrm->mutex_mod || subfrm->mutex_mod2) {
mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm->mutex_mod,
- 0, mutex_sof, cmd);
+ subfrm->mutex_mod2, mutex_sof, cmd);
}
+ if (subfrm->mutex2_mod || subfrm->mutex2_mod2) {
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id], subfrm->mutex2_mod,
+ subfrm->mutex2_mod2, mutex2_sof, cmd);
+ }
return 0;
}
@@ -163,14 +349,16 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
{
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
+ struct mtk_mutex **mutex2 = path->mdp_dev->mdp_mutex2;
s32 mutex_id = subfrm->mutex_id;
+ s32 mutex2_id = subfrm->mutex2_id;
- if (-1 == mutex_id) {
+ if (mutex_id == MDP_PIPE_NONE && mutex2_id == MDP_PIPE_NONE) {
dev_err(dev, "Incorrect mutex id");
return -EINVAL;
}
- if (subfrm->mutex_mod) {
+ if (subfrm->mutex_mod || subfrm->mutex_mod2) {
int index, evt;
/* Wait WROT SRAM shared to DISP RDMA */
@@ -235,6 +423,71 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
MM_REG_WAIT(cmd, evt);
}
}
+
+ if (subfrm->mutex2_mod || subfrm->mutex2_mod2) {
+ int index, evt;
+
+ /* Clear SOF event for each engine */
+ for (index = 0; index < subfrm->num_sof2s; index++) {
+ switch (subfrm->sof2s[index]) {
+ case MDP_COMP_RDMA1:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA1_SOF);
+ break;
+ case MDP_COMP_RDMA2:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA2_SOF);
+ break;
+ case MDP_COMP_RDMA3:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA3_SOF);
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT1_SOF);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT2_SOF);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT3_SOF);
+ break;
+ default:
+ evt = -1;
+ break;
+ }
+ if (evt > 0)
+ MM_REG_CLEAR(cmd, evt);
+ }
+
+ /* Enable the mutex */
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+
+ /* Wait SOF events and clear mutex modules (optional) */
+ for (index = 0; index < subfrm->num_sof2s; index++) {
+ switch (subfrm->sof2s[index]) {
+ case MDP_COMP_RDMA1:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA1_SOF);
+ break;
+ case MDP_COMP_RDMA2:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA2_SOF);
+ break;
+ case MDP_COMP_RDMA3:
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA3_SOF);
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT1_SOF);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT2_SOF);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(path->mdp_dev, WROT3_SOF);
+ break;
+ default:
+ evt = -1;
+ break;
+ }
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
+ }
+ }
return 0;
}
@@ -247,6 +500,9 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path)
return -EINVAL;
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ret = mdp_comp_ctx_init(mdp, &path->comps[index],
&config->components[index],
path->param);
@@ -276,13 +532,21 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
/* Enable mux settings */
for (index = 0; index < ctrl->num_sets; index++) {
set = &ctrl->sets[index];
- mmsys_dev = path->mdp_dev->mdp_mmsys;
+ if (data->mdp_cfg->mdp_version_8195) {
+ if (set->vpp_id)
+ mmsys_dev = path->mdp_dev->mdp_mmsys2;
+ else
+ mmsys_dev = path->mdp_dev->mdp_mmsys;
+ }
mtk_mmsys_write_reg_by_cmdq(mmsys_dev, cmd,
set->reg, set->value, 0xFFFFFFFF);
}
/* Config sub-frame information */
for (index = (config->num_components - 1); index >= 0; index--) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
@@ -296,6 +560,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
return ret;
/* Wait components done */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
@@ -305,6 +572,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
}
/* Advance to the next sub-frame */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(path->mdp_dev, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, advance_subfrm, cmd, count);
if (ret)
@@ -313,7 +583,12 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
/* Disable mux settings */
for (index = 0; index < ctrl->num_sets; index++) {
set = &ctrl->sets[index];
- mmsys_dev = path->mdp_dev->mdp_mmsys;
+ if (data->mdp_cfg->mdp_version_8195) {
+ if (set->vpp_id)
+ mmsys_dev = path->mdp_dev->mdp_mmsys2;
+ else
+ mmsys_dev = path->mdp_dev->mdp_mmsys;
+ }
mtk_mmsys_write_reg_by_cmdq(mmsys_dev, cmd,
set->reg, 0, 0xFFFFFFFF);
@@ -332,6 +607,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
/* Config path frame */
/* Reset components */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, init_comp, cmd);
if (ret)
@@ -342,6 +620,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
const struct v4l2_rect *compose =
path->composes[ctx->param->outputs[0]];
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, config_frame, cmd, compose);
if (ret)
@@ -356,6 +637,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
}
/* Post processing information */
for (index = 0; index < config->num_components; index++) {
+ if (is_dummy_engine(mdp, config->components[index].type))
+ continue;
+
ctx = &path->comps[index];
ret = call_op(ctx, post_process, cmd);
if (ret)
@@ -364,6 +648,60 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
return 0;
}
+static int mdp_hyfbc_config(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
+ struct mdp_path *path, struct mdp_cmdq_param *param)
+{
+ struct device *dev = &mdp->pdev->dev;
+ const struct img_config *config = path->config;
+ struct mdp_m2m_ctx *ctx;
+ struct mdp_comp_ctx *comp_ctx = &path->comps[0];
+ const struct mdp_rdma_data *rdma = &comp_ctx->param->rdma;
+ struct hyfbc_init_info hyfbc;
+ struct mdp_frame *frame;
+ u32 wrot_id;
+ int ret;
+
+ ctx = (struct mdp_m2m_ctx *)param->mdp_ctx;
+ frame = &ctx->curr_param.output;
+
+ if (!MDP_COLOR_IS_HYFBC_COMPRESS(frame->mdp_fmt->mdp_color) ||
+ frame->format.fmt.pix_mp.width % 32 == 0)
+ return 0;
+
+ // First engine should be rdma engine
+ if (!is_rdma(mdp, config->components[0].type)) {
+ dev_dbg(dev, "Not RDMA engine id, end patch.");
+ return 0;
+ }
+
+ wrot_id = config->components[(config->num_components - 1)].type;
+
+ hyfbc.is10b = (MDP_COLOR_IS_10BIT(frame->mdp_fmt->mdp_color));
+ hyfbc.width_in_mb = DIV_ROUND_UP(frame->format.fmt.pix_mp.width, 16);
+ hyfbc.height_in_mb = DIV_ROUND_UP(frame->format.fmt.pix_mp.height, 16);
+ hyfbc.w_stride_in_mb = DIV_ROUND_UP(ALIGN(frame->stride.width, 32), 16);
+ hyfbc.h_stride_in_mb = DIV_ROUND_UP(ALIGN(frame->stride.height, 32), 16);
+ hyfbc.byte_per_mb = BYTE_PER_MB_Y;
+ hyfbc.pa_base = rdma->ufo_dec_y;
+
+ ret = mdp_hyfbc_init(mdp, cmd, &hyfbc, wrot_id);
+ if (ret) {
+ dev_err(dev, "mdp_hyfbc_init: y patch fail.");
+ return ret;
+ }
+
+ hyfbc.byte_per_mb = BYTE_PER_MB_C;
+ hyfbc.pa_base = rdma->ufo_dec_c;
+
+ ret = mdp_hyfbc_init(mdp, cmd, &hyfbc, wrot_id);
+ if (ret) {
+ dev_err(dev, "mdp_hyfbc_init: c patch fail.");
+ return ret;
+ }
+
+ return 0;
+}
+
static void mdp_auto_release_work(struct work_struct *work)
{
struct mdp_cmdq_cb_param *cb_param;
@@ -376,6 +714,10 @@ static void mdp_auto_release_work(struct work_struct *work)
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -419,6 +761,11 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
dev_err(dev, "%s:queue_work fail!\n", __func__);
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -481,8 +828,22 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
- for (i = 0; i < param->config->num_components; i++)
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_prepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ for (i = 0; i < param->config->num_components; i++) {
+ if (is_dummy_engine(mdp, path->config->components[i].type))
+ continue;
+
mdp_comp_clock_on(&mdp->pdev->dev, path->comps[i].comp);
+ }
+
+ if (mdp->mdp_data->mdp_cfg->mdp_version_8195) {
+ ret = mdp_hyfbc_config(mdp, &cmd, path, param);
+ if (ret)
+ goto err_destroy_pkt;
+ }
ret = mdp_path_config(mdp, &cmd, path);
if (ret) {
@@ -503,9 +864,13 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
goto err_destroy_pkt;
}
- for (i = 0; i < param->config->num_components; i++)
+ for (i = 0; i < param->config->num_components; i++) {
+ if (is_dummy_engine(mdp, path->config->components[i].type))
+ continue;
+
memcpy(&comps[i], path->comps[i].comp,
sizeof(struct mdp_comp));
+ }
cb_param->mdp = mdp;
cb_param->user_cmdq_cb = param->cmdq_cb;
cb_param->user_cb_data = param->cb_data;
@@ -528,6 +893,11 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
err_clock_off:
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
err_destroy_pkt:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index 8ca9c7e325e1..3d5cbd0e3805 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -27,6 +27,10 @@
#include "mdp_reg_wdma.h"
#include "mdp_reg_isp.h"
+#define is_wrot(id) \
+ ((mdp)->mdp_data->comp_data[id].match.type == MDP_COMP_TYPE_WROT)
+#define byte2pixel(byte) ((byte) / 2)
+
s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
{
if (!mdp_dev)
@@ -57,6 +61,20 @@ enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 inner_id)
return public_id;
}
+bool is_dummy_engine(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id public_id = get_comp_public_id(mdp_dev, inner_id);
+
+ return (mdp_dev->mdp_data->comp_data[public_id].match.type == MDP_COMP_TYPE_DUMMY);
+}
+
+bool is_rdma(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id public_id = get_comp_public_id(mdp_dev, inner_id);
+
+ return (mdp_dev->mdp_data->comp_data[public_id].match.type == MDP_COMP_TYPE_RDMA);
+}
+
static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ctx *ctx)
{
if (!ctx)
@@ -423,14 +441,40 @@ static const struct mdp_comp_ops fg_ops = {
static int init_rsz(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
+ const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ u32 value, mask, alias_id;
/* Reset RSZ */
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16));
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16));
/* Enable RSZ */
MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0));
+
+ if (mdp_cfg && mdp_cfg->mdp_version_8195) {
+ const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data;
+
+ value = (1 << 25);
+ mask = (1 << 25);
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_2ND_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+
+ value = (1 << 4 | 1 << 5);
+ mask = (1 << 4 | 1 << 5);
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_1ST_DIS1];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+
+ alias_id = data->config_table[CONFIG_VPP1_HW_DCM_2ND_DIS1];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, value, mask);
+ }
return 0;
}
@@ -501,6 +545,48 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx,
MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, subfrm->clip,
0xFFFFFFFF);
+ if (mdp_cfg && mdp_cfg->mdp_version_8195) {
+ struct mdp_comp *merge;
+ const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data;
+ enum mtk_mdp_comp_id id = ctx->comp->public_id;
+ u32 alias_id;
+
+ switch (id) {
+ case MDP_COMP_RSZ2:
+ merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE2];
+
+ alias_id = data->config_table[CONFIG_SVPP2_BUF_BF_RSZ_SWITCH];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id,
+ subfrm->rsz_switch, 0xFFFFFFFF);
+ break;
+ case MDP_COMP_RSZ3:
+ merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE3];
+
+ alias_id = data->config_table[CONFIG_SVPP3_BUF_BF_RSZ_SWITCH];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id,
+ subfrm->rsz_switch, 0xFFFFFFFF);
+ break;
+ default:
+ goto subfrm_done;
+ }
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_0, subfrm->merge_cfg, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_4, subfrm->merge_cfg, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_24, subfrm->merge_cfg, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_25, subfrm->merge_cfg, 0xFFFFFFFF);
+
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_CFG_12, 0x1, 0xFFFFFFFF); // bypass mode
+ MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base,
+ VPP_MERGE_ENABLE, 0x1, 0xFFFFFFFF);
+ }
+
+subfrm_done:
return 0;
}
@@ -1020,10 +1106,12 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
{
const struct mdp_wrot_data *wrot = &ctx->param->wrot;
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
+ const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
bool comp;
u32 colorformat = ctx->outputs[0]->buffer.format.colorformat;
+ u32 alias_id;
/* Write frame base address */
MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0],
@@ -1084,11 +1172,36 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx,
if (wrot->fifo_test != 0)
MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST,
wrot->fifo_test, 0xFFF);
- /* Filter enable */
- if (mdp_cfg && mdp_cfg->wrot_filter_constraint)
- MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
- wrot->filter, 0x77);
-
+ if (mdp_cfg) {
+ /* Filter enable */
+ if (mdp_cfg->wrot_filter_constraint)
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
+ wrot->filter, 0x77);
+
+ if (mdp_cfg->mdp_version_8195) {
+ /* Turn off WROT dma dcm */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN,
+ (0x1 << 23) + (0x1 << 20), 0x900000);
+
+ if (wrot->vpp02vpp1) {
+ // Disable DCM (VPP02VPP1_RELAY)
+ alias_id = data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys,
+ cmd, alias_id, 0x4000,
+ 0xFFFFFFFF);
+ // Set default size
+ alias_id = data->config_table[CONFIG_VPP0_DL_IRELAY_WR];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys2,
+ cmd, alias_id, 0x0,
+ 0xFFFFFFFF);
+ } else {
+ alias_id = data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(ctx->comp->mdp_dev->mdp_mmsys,
+ cmd, alias_id, 0x0,
+ 0xFFFFFFFF);
+ }
+ }
+ }
return 0;
}
@@ -1566,17 +1679,30 @@ static const struct mdp_comp_ops camin_ops = {
};
static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = {
- [MDP_COMP_TYPE_RDMA] = &rdma_ops,
- [MDP_COMP_TYPE_RSZ] = &rsz_ops,
- [MDP_COMP_TYPE_WROT] = &wrot_ops,
- [MDP_COMP_TYPE_WDMA] = &wdma_ops,
- [MDP_COMP_TYPE_PATH1] = NULL,
- [MDP_COMP_TYPE_PATH2] = NULL,
- [MDP_COMP_TYPE_CCORR] = &ccorr_ops,
- [MDP_COMP_TYPE_IMGI] = &imgi_ops,
- [MDP_COMP_TYPE_EXTO] = NULL,
- [MDP_COMP_TYPE_DL_PATH1] = &camin_ops,
- [MDP_COMP_TYPE_DL_PATH2] = &camin_ops,
+ [MDP_COMP_TYPE_WPEI] = &camin_ops,
+ [MDP_COMP_TYPE_SPLIT] = &split_ops,
+ [MDP_COMP_TYPE_STITCH] = &stitch_ops,
+ [MDP_COMP_TYPE_RDMA] = &rdma_ops,
+ [MDP_COMP_TYPE_FG] = &fg_ops,
+ [MDP_COMP_TYPE_HDR] = &hdr_ops,
+ [MDP_COMP_TYPE_AAL] = &aal_ops,
+ [MDP_COMP_TYPE_RSZ] = &rsz_ops,
+ [MDP_COMP_TYPE_TDSHP] = &tdshp_ops,
+ [MDP_COMP_TYPE_COLOR] = &color_ops,
+ [MDP_COMP_TYPE_OVL] = &ovl_ops,
+ [MDP_COMP_TYPE_PAD] = &pad_ops,
+ [MDP_COMP_TYPE_TCC] = &tcc_ops,
+ [MDP_COMP_TYPE_WROT] = &wrot_ops,
+ [MDP_COMP_TYPE_WDMA] = &wdma_ops,
+ [MDP_COMP_TYPE_MERGE] = NULL,
+ [MDP_COMP_TYPE_PATH1] = NULL,
+ [MDP_COMP_TYPE_PATH2] = NULL,
+ [MDP_COMP_TYPE_CCORR] = &ccorr_ops,
+ [MDP_COMP_TYPE_IMGI] = &imgi_ops,
+ [MDP_COMP_TYPE_EXTO] = NULL,
+ [MDP_COMP_TYPE_DL_PATH1] = &camin_ops,
+ [MDP_COMP_TYPE_DL_PATH2] = &camin_ops,
+ [MDP_COMP_TYPE_DUMMY] = NULL,
};
static const struct of_device_id mdp_comp_dt_ids[] = {
@@ -2070,3 +2196,190 @@ int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
ctx->outputs[i] = &frame->outputs[param->outputs[i]];
return 0;
}
+
+int mdp_hyfbc_init(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
+ struct hyfbc_init_info *hyfbc, u32 wrot)
+{
+ struct mtk_mutex **mutex = mdp->mdp_mutex;
+ struct mtk_mutex **mutex2 = mdp->mdp_mutex2;
+ enum mtk_mdp_comp_id mtk_wrot = MDP_COMP_NONE;
+ phys_addr_t base;
+ u16 subsys_id;
+ u32 offset;
+ u32 mutex_id;
+ u32 mutex2_id;
+ u32 alias_id;
+ int evt;
+
+ mtk_wrot = get_comp_public_id(mdp, wrot);
+ if (!is_wrot(mtk_wrot)) {
+ dev_err(&mdp->pdev->dev, "Invalid wrot inner id %d", wrot);
+ return -EINVAL;
+ }
+
+ base = mdp->comp[mtk_wrot]->reg_base;
+ subsys_id = mdp->comp[mtk_wrot]->subsys_id;
+ offset = hyfbc->width_in_mb * hyfbc->byte_per_mb;
+
+ /* Reset WROT */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST,
+ 0x01, 0x00000001);
+ MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT,
+ 0x01, 0x00000001);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST,
+ 0x00, 0x00000001);
+ MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT,
+ 0x00, 0x00000001);
+
+ /* Write frame base address */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR,
+ (hyfbc->pa_base + offset), 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C,
+ 0x0, 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V,
+ 0x0, 0xFFFFFFFF);
+
+ /* Write frame related registers */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL,
+ 0x5020, 0xF131512F);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_BKGD,
+ ((hyfbc->is10b) ? 0xC8E438 : 0x18f4f8), 0xFFFFFFFF);
+
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT,
+ 0x0, 0x0000000F);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO,
+ 0x0, 0x04000000);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2,
+ 0x0, 0x00000007);
+
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_PVRIC,
+ 0x0, 0x03);
+ /* Write pre-ultra threshold */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA,
+ 0x8804c, 0x00FFFFFF);
+ /* Write frame Y pitch */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE,
+ (hyfbc->w_stride_in_mb * hyfbc->byte_per_mb), 0x0000FFFF);
+ /* Write frame UV pitch */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C,
+ 0x0, 0x0000FFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V,
+ 0x0, 0x0000FFFF);
+ /* Write matrix control */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL,
+ 0x60, 0x000000F3);
+
+ /* Set the fixed ALPHA as 0xFF */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER,
+ 0xFF000000, 0xFF000000);
+ /* Set VIDO_EOL_SEL */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1,
+ 0x80000000, 0x80000000);
+ /* Set VIDO_FIFO_TEST */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST,
+ 0x200, 0x00000FFF);
+
+ /* Filter enable */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
+ 0x0, 0x00000077);
+
+ /* Turn off WROT dma dcm */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN,
+ (0x1 << 23) + (0x1 << 20), 0x00900000);
+
+ alias_id = mdp->mdp_data->config_table[CONFIG_VPP0_HW_DCM_1ST_DIS0];
+ mtk_mmsys_mdp_write_config(mdp->mdp_mmsys, cmd,
+ alias_id, 0x0, 0xFFFFFFFF);
+
+ /* Set mutex modules */
+ switch (mtk_wrot) {
+ case MDP_COMP_WROT0:
+ mutex_id = 2;
+ mtk_mutex_add_mod_by_cmdq(mutex[mutex_id],
+ 0x800, 0x0, 0x0, cmd);
+ break;
+ case MDP_COMP_WROT1:
+ mutex2_id = 1;
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id],
+ 0x80000000, 0x0, 0x0, cmd);
+ break;
+ case MDP_COMP_WROT2:
+ mutex2_id = 2;
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id],
+ 0x0, 0x1, 0x0, cmd);
+ break;
+ case MDP_COMP_WROT3:
+ mutex2_id = 3;
+ mtk_mutex_add_mod_by_cmdq(mutex2[mutex2_id],
+ 0x0, 0x2, 0x0, cmd);
+ break;
+ default:
+ break;
+ }
+
+ /* Write Y pixel offset */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR,
+ 0x0, 0x0FFFFFFF);
+ /* Write U pixel offset */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C,
+ 0x0, 0x0FFFFFFF);
+ /* Write V pixel offset */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V,
+ 0x0, 0x0FFFFFFF);
+ /* Write source size */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE,
+ (hyfbc->height_in_mb << 16) | byte2pixel(hyfbc->byte_per_mb), 0xFFFFFFFF);
+ /* Write target size */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE,
+ (hyfbc->height_in_mb << 16) | byte2pixel(hyfbc->byte_per_mb), 0xFFFFFFFF);
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, 0x0,
+ 0xFFFFFFFF);
+
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE,
+ ((byte2pixel(hyfbc->byte_per_mb) << 16) | 0x400), 0xFFFF7F00);
+
+ /* Enable WROT */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x01, 0x00000001);
+
+ switch (mtk_wrot) {
+ case MDP_COMP_WROT0:
+ evt = mdp_get_event_idx(mdp, WROT0_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex[mutex_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT0_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ case MDP_COMP_WROT1:
+ evt = mdp_get_event_idx(mdp, WROT1_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT1_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ case MDP_COMP_WROT2:
+ evt = mdp_get_event_idx(mdp, WROT2_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT2_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ case MDP_COMP_WROT3:
+ evt = mdp_get_event_idx(mdp, WROT3_SOF);
+ MM_REG_CLEAR(cmd, evt);
+ mtk_mutex_enable_by_cmdq(mutex2[mutex2_id], cmd);
+ MM_REG_WAIT(cmd, evt);
+ evt = mdp_get_event_idx(mdp, WROT3_DONE);
+ MM_REG_WAIT(cmd, evt);
+ break;
+ default:
+ break;
+ }
+
+ /* Disable WROT */
+ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x00, 0x00000001);
+
+ return 0;
+}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
index 05a60771d4bc..391e9014dc99 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
@@ -222,7 +222,8 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num);
int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_compparam *param,
const struct img_ipi_frameparam *frame);
-
+int mdp_hyfbc_init(struct mdp_dev *mdp, struct mmsys_cmdq_cmd *cmd,
+ struct hyfbc_init_info *hyfbc, u32 wrot);
int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event);
#endif /* __MTK_MDP3_COMP_H__ */
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index bef8da6fff1c..d8161be8c556 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -44,6 +44,9 @@ static const struct of_device_id mdp_of_ids[] = {
{ .compatible = "mediatek,mt8183-mdp3",
.data = &mt8183_mdp_driver_data,
},
+ { .compatible = "mediatek,mt8195-mdp3",
+ .data = &mt8195_mdp_driver_data,
+ },
{},
};
MODULE_DEVICE_TABLE(of, mdp_of_ids);
@@ -150,7 +153,7 @@ static int mdp_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mdp_dev *mdp;
struct device_node *mdp_node;
- struct platform_device *mm_pdev;
+ struct platform_device *mm_pdev, *mm_pdev2;
u32 event_ofst;
int ret, i, mutex_id;
@@ -162,13 +165,28 @@ static int mdp_probe(struct platform_device *pdev)
mdp->pdev = pdev;
mdp->mdp_data = of_device_get_match_data(&pdev->dev);
+
+ if (of_get_property(pdev->dev.of_node, "dma-ranges", NULL))
+ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
+
mm_pdev = __get_pdev_by_name(pdev, "mediatek,mmsys");
if (!mm_pdev) {
- ret = -ENODEV;
- goto err_return;
+ if (mdp->mdp_data->mdp_cfg->support_multi_larb) {
+ platform_set_drvdata(pdev, mdp);
+ goto success_return;
+ } else {
+ ret = -ENODEV;
+ goto err_return;
+ }
}
mdp->mdp_mmsys = &mm_pdev->dev;
+ mm_pdev2 = __get_pdev_by_name(pdev, "mediatek,mmsys2");
+ if (!mm_pdev2)
+ dev_err(dev, "Failed to get mdp mmsys2\n");
+ else
+ mdp->mdp_mmsys2 = &mm_pdev2->dev;
+
mdp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,mm-mutex", 0);
if (!mdp_node) {
ret = -ENODEV;
@@ -200,17 +218,43 @@ static int mdp_probe(struct platform_device *pdev)
goto err_return;
}
+ mdp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,mm-mutex2", 0);
+ if (!mdp_node) {
+ dev_err(dev, "Failed to get mdp mm-mutex2\n");
+ } else {
+ mm_pdev2 = of_find_device_by_node(mdp_node);
+ of_node_put(mdp_node);
+ if (WARN_ON(!mm_pdev2)) {
+ ret = -ENODEV;
+ goto err_return;
+ }
+ }
+
for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) {
mutex_id = mdp->mdp_data->pipe_info[i].mutex_id;
- if (mdp->mdp_mutex[mutex_id])
- continue;
-
- mdp->mdp_mutex[mutex_id] =
- mtk_mutex_mdp_get(&mm_pdev->dev, mdp->mdp_data->pipe_info[i].pipe_id);
- if (!mdp->mdp_mutex[mutex_id]) {
- ret = -ENODEV;
- goto err_return;
+ if (mdp->mdp_data->pipe_info[i].mmsys_id != 0) {
+ if (mdp->mdp_mutex2[mutex_id])
+ continue;
+ mdp->mdp_mutex2[mutex_id] =
+ mtk_mutex_mdp_get(&mm_pdev2->dev,
+ mdp->mdp_data->pipe_info[i].pipe_id);
+
+ if (!mdp->mdp_mutex2[mutex_id]) {
+ ret = -ENODEV;
+ goto err_return;
+ }
+ } else {
+ if (mdp->mdp_mutex[mutex_id])
+ continue;
+ mdp->mdp_mutex[mutex_id] =
+ mtk_mutex_mdp_get(&mm_pdev->dev,
+ mdp->mdp_data->pipe_info[i].pipe_id);
+
+ if (!mdp->mdp_mutex[mutex_id]) {
+ ret = -ENODEV;
+ goto err_return;
+ }
}
}
@@ -273,6 +317,7 @@ static int mdp_probe(struct platform_device *pdev)
goto err_unregister_device;
}
+success_return:
dev_dbg(dev, "mdp-%d registered successfully\n", pdev->id);
return 0;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index c668e317f947..8ee70763a18f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -60,7 +60,9 @@ struct mtk_mdp_driver_data {
struct mdp_dev {
struct platform_device *pdev;
struct device *mdp_mmsys;
+ struct device *mdp_mmsys2;
struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX];
+ struct mtk_mutex *mdp_mutex2[MDP_PIPE_MAX];
struct mdp_comp *comp[MDP_MAX_COMP_COUNT];
const struct mtk_mdp_driver_data *mdp_data;
s32 event[MDP_MAX_EVENT_COUNT];
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index ca1c19c41950..1e749bb2b338 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -90,6 +90,7 @@ static void mdp_m2m_worker(struct work_struct *work)
param.type = ctx->curr_param.type;
param.num_inputs = 1;
param.num_outputs = 1;
+ param.frame_change = (ctx->frame_count[MDP_M2M_SRC] == 0);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
@@ -328,6 +329,11 @@ static int mdp_m2m_s_fmt_mplane(struct file *file, void *fh,
ctx->curr_param.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;
ctx->curr_param.quant = f->fmt.pix_mp.quantization;
ctx->curr_param.xfer_func = f->fmt.pix_mp.xfer_func;
+
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(fmt->mdp_color)) {
+ frame->stride.width = ((f->fmt.pix_mp.width + 63) >> 6) << 6;
+ frame->stride.height = ((f->fmt.pix_mp.height + 31) >> 5) << 5;
+ }
} else {
capture->compose.left = 0;
capture->compose.top = 0;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index 83e91735202b..8c2b74c67273 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -147,6 +147,47 @@ int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f)
return 0;
}
+static u32 mdp_fmt_get_hyfbc_plane_size(u32 width,
+ u32 height, u32 color, unsigned int plane)
+{
+ u32 y_data_size = 0;
+ u32 c_data_size = 0;
+ u32 y_header_size = 0;
+ u32 c_header_size = 0;
+ u32 y_data_ofst = 0;
+ u32 c_data_ofst = 0;
+ u32 c_header_ofst = 0;
+
+ y_data_size = (((width + 63) >> 6) << 6) * (((height + 63) >> 6) << 6);
+ y_header_size = y_data_size >> 6;
+ if (MDP_COLOR_IS_10BIT_PACKED(color))
+ y_data_size = (y_data_size * 6) >> 2;
+
+ c_data_size = y_data_size >> 1;
+ c_header_size = (((y_header_size >> 1) + 63) >> 6) << 6;
+
+ // Setup source buffer base
+ y_data_ofst = ((y_header_size + 4095) >> 12) << 12; // align 4k
+ c_data_ofst = ((y_data_ofst + y_data_size + c_header_size + 4095) >> 12) << 12; // align 4k
+ c_header_ofst = c_data_ofst - c_header_size;
+
+ if (plane == 0)
+ return c_header_ofst;
+ else
+ return (c_data_ofst + c_data_size);
+}
+
+static u32 mdp_fmt_get_afbc_plane_size(u32 width, u32 height, u32 color)
+{
+ u32 align_w = ((width + 31) >> 5) << 5;
+ u32 align_h = ((height + 31) >> 5) << 5;
+
+ if (MDP_COLOR_IS_10BIT_PACKED(color))
+ return ((align_w >> 4) * (align_h >> 4) * (16 + 512));
+ else
+ return ((align_w >> 4) * (align_h >> 4) * (16 + 384));
+}
+
const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
struct mdp_frameparam *param,
u32 ctx_id)
@@ -211,11 +252,17 @@ const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
bpl = min_bpl;
si = (bpl * pix_mp->height * fmt->depth[i]) / fmt->row_depth[i];
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(fmt->mdp_color)) {
+ si = mdp_fmt_get_hyfbc_plane_size(pix_mp->width,
+ pix_mp->height, fmt->mdp_color, i);
+ } else if (MDP_COLOR_IS_COMPRESS(fmt->mdp_color)) {
+ si = mdp_fmt_get_afbc_plane_size(pix_mp->width,
+ pix_mp->height, fmt->mdp_color);
+ }
+
pix_mp->plane_fmt[i].bytesperline = bpl;
if (pix_mp->plane_fmt[i].sizeimage < si)
pix_mp->plane_fmt[i].sizeimage = si;
- dev_dbg(dev, "%d: p%u, bpl:%u (%u), sizeimage:%u (%u)", ctx_id,
- i, bpl, min_bpl, pix_mp->plane_fmt[i].sizeimage, si);
}
return fmt;
@@ -324,8 +371,14 @@ static u32 mdp_fmt_get_stride(const struct mdp_format *fmt,
enum mdp_color c = fmt->mdp_color;
u32 stride;
- stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c))
- / fmt->row_depth[0];
+ if (MDP_COLOR_IS_COMPRESS(c)) {
+ bytesperline = ((bytesperline + 31) >> 5) << 5;
+ stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c))
+ / fmt->row_depth[0];
+ } else {
+ stride = (bytesperline * MDP_COLOR_BITS_PER_PIXEL(c))
+ / fmt->row_depth[0];
+ }
if (plane == 0)
return stride;
if (plane < MDP_COLOR_GET_PLANE_COUNT(c)) {
@@ -398,6 +451,19 @@ static void mdp_prepare_buffer(struct img_image_buffer *b,
mdp_fmt_get_plane_size(frame->mdp_fmt, stride,
pix_mp->height, i) -
vb->planes[i].data_offset;
+
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_hyfbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat, i);
+ } else if (MDP_COLOR_IS_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_afbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat);
+ }
+
b->iova[i] = vb2_dma_contig_plane_dma_addr(vb, i) +
vb->planes[i].data_offset;
}
@@ -409,6 +475,18 @@ static void mdp_prepare_buffer(struct img_image_buffer *b,
b->format.plane_fmt[i].size =
mdp_fmt_get_plane_size(frame->mdp_fmt, stride,
pix_mp->height, i);
+
+ if (MDP_COLOR_IS_HYFBC_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_hyfbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat, i);
+ } else if (MDP_COLOR_IS_COMPRESS(b->format.colorformat)) {
+ b->format.plane_fmt[i].size =
+ mdp_fmt_get_afbc_plane_size(pix_mp->width,
+ pix_mp->height,
+ b->format.colorformat);
+ }
b->iova[i] = b->iova[i - 1] + b->format.plane_fmt[i - 1].size;
}
b->usage = frame->usage;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 4a25f86bfaa5..1ef32b747233 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -355,6 +355,8 @@ struct mdp_frame {
u32 dre:1;
u32 sharpness:1;
u32 dither:1;
+ /* H and V stride, only for HYFBC format */
+ struct v4l2_rect stride;
};
static inline bool mdp_target_is_crop(u32 target)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 10/14] media: platform: mtk-mdp3: Add dual pipe feature support
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add dual pipe feature which uses two svpp to execute dma
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mt8195_mdp.h | 1 +
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 245 +++++++++++-------
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 4 +
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 21 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 11 +-
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 5 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 18 ++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 4 +
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 2 +-
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 1 +
10 files changed, 214 insertions(+), 98 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mt8195_mdp.h b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
index f69bc86bcd1e..dc9454cfd33a 100644
--- a/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
+++ b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
@@ -24,6 +24,7 @@ static const struct mdp_platform_config mt8195_plat_cfg = {
.mdp_version_6885 = true,
.gce_event_offset = 0,
.support_multi_larb = true,
+ .support_dual_pipe = true,
};
enum mt8195_mdp_comp_id {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index ce9326cc790f..86b7d83be22c 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -29,6 +29,9 @@ struct mdp_path {
((ctx)->comp->ops && (ctx)->comp->ops->op)
#define call_op(ctx, op, ...) \
(has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0)
+#define get_pipe_num(scenario) \
+ ((scenario) == MDP_STREAM_TYPE_DUAL_BITBLT ? 2 : 1)
+
struct mdp_path_subfrm {
s32 mutex_id;
u32 mutex_mod;
@@ -707,25 +710,31 @@ static void mdp_auto_release_work(struct work_struct *work)
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
int i;
+ bool finalize;
cb_param = container_of(work, struct mdp_cmdq_cb_param,
auto_release_work);
mdp = cb_param->mdp;
+ finalize = cb_param->finalize;
- i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
- mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+ if (finalize) {
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
- i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
- if (i >= 0)
- mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+ }
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
kfree(cb_param->comps);
kfree(cb_param);
- atomic_dec(&mdp->job_count);
- wake_up(&mdp->callback_wq);
+ if (finalize) {
+ atomic_dec(&mdp->job_count);
+ wake_up(&mdp->callback_wq);
+ }
}
static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
@@ -744,7 +753,13 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
mdp = cb_param->mdp;
dev = &mdp->pdev->dev;
- if (cb_param->mdp_ctx)
+ if (cb_param->dualpipe)
+ cb_param->finalize =
+ (atomic_dec_and_test(&mdp->cmdq_count[cb_param->cmdq_user]));
+ else
+ cb_param->finalize = true;
+
+ if (cb_param->finalize && cb_param->mdp_ctx)
mdp_m2m_job_finish(cb_param->mdp_ctx);
if (cb_param->user_cmdq_cb) {
@@ -779,52 +794,62 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
{
- struct mmsys_cmdq_cmd cmd;
- struct mdp_path *path = NULL;
- struct mdp_cmdq_cb_param *cb_param = NULL;
- struct mdp_comp *comps = NULL;
+ struct mmsys_cmdq_cmd cmd[MDP_DUAL_PIPE];
+ struct mdp_path *paths[MDP_DUAL_PIPE] = {NULL};
+ struct mdp_cmdq_cb_param *cb_param[MDP_DUAL_PIPE] = {NULL};
+ struct mdp_comp *comps[MDP_DUAL_PIPE] = {NULL};
struct device *dev = &mdp->pdev->dev;
- int i, ret;
+
+ enum mdp_stream_type scenario = param->param->type;
+ int i, j, ret;
if (atomic_read(&mdp->suspended))
return -ECANCELED;
atomic_inc(&mdp->job_count);
- cmd.pkt = cmdq_pkt_create(mdp->cmdq_clt, SZ_16K);
- if (IS_ERR(cmd.pkt)) {
- atomic_dec(&mdp->job_count);
- wake_up(&mdp->callback_wq);
- return PTR_ERR(cmd.pkt);
+ /* Prepare cmdq pkt */
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ cmd[i].pkt = cmdq_pkt_create(mdp->cmdq_clt[i], SZ_16K);
+ if (IS_ERR(cmd[i].pkt)) {
+ ret = PTR_ERR(cmd[i].pkt);
+ dev_err(dev, "%s path %d cmdq_pkt_create error\n", __func__, i);
+ goto err_destroy_pkt;
+ }
+ cmd[i].event = &mdp->event[0];
}
- cmd.event = &mdp->event[0];
- path = kzalloc(sizeof(*path), GFP_KERNEL);
- if (!path) {
- ret = -ENOMEM;
- goto err_destroy_pkt;
- }
+ /* Prepare path info */
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ paths[i] = kzalloc(sizeof(*paths[i]), GFP_KERNEL);
+ if (!paths[i]) {
+ ret = -ENOMEM;
+ dev_err(dev, "%s alloc paths error\n", __func__);
+ goto err_destroy_paths;
+ }
- path->mdp_dev = mdp;
- path->config = param->config;
- path->param = param->param;
- for (i = 0; i < param->param->num_outputs; i++) {
- path->bounds[i].left = 0;
- path->bounds[i].top = 0;
- path->bounds[i].width =
- param->param->outputs[i].buffer.format.width;
- path->bounds[i].height =
- param->param->outputs[i].buffer.format.height;
- path->composes[i] = param->composes[i] ?
- param->composes[i] : &path->bounds[i];
- }
+ paths[i]->mdp_dev = mdp;
+ paths[i]->config = ¶m->config[i];
+ paths[i]->param = param->param;
+ for (j = 0; j < param->param->num_outputs; j++) {
+ paths[i]->bounds[j].left = 0;
+ paths[i]->bounds[j].top = 0;
+ paths[i]->bounds[j].width =
+ param->param->outputs[j].buffer.format.width;
+ paths[i]->bounds[j].height =
+ param->param->outputs[j].buffer.format.height;
+ paths[i]->composes[j] = param->composes[j] ?
+ param->composes[j] : &paths[i]->bounds[j];
+ }
- ret = mdp_path_ctx_init(mdp, path);
- if (ret) {
- dev_err(dev, "mdp_path_ctx_init error\n");
- goto err_destroy_pkt;
+ ret = mdp_path_ctx_init(mdp, paths[i]);
+ if (ret) {
+ dev_err(dev, "%s mdp_path_ctx_init error at path %d\n", __func__, i);
+ goto err_destroy_paths;
+ }
}
+ /* Setup clock and cmdq buffer */
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
@@ -832,64 +857,94 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
if (i >= 0)
mtk_mutex_prepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
- for (i = 0; i < param->config->num_components; i++) {
- if (is_dummy_engine(mdp, path->config->components[i].type))
- continue;
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ for (j = 0; j < param->config[i].num_components; j++) {
+ if (is_dummy_engine(mdp, paths[i]->config->components[j].type))
+ continue;
- mdp_comp_clock_on(&mdp->pdev->dev, path->comps[i].comp);
+ mdp_comp_clock_on(&mdp->pdev->dev, paths[i]->comps[j].comp);
+ }
}
if (mdp->mdp_data->mdp_cfg->mdp_version_8195) {
- ret = mdp_hyfbc_config(mdp, &cmd, path, param);
- if (ret)
- goto err_destroy_pkt;
+ ret = mdp_hyfbc_config(mdp, &cmd[0], paths[0], param);
+ if (ret) {
+ dev_err(dev, "%s mdp_hyfbc_config error\n", __func__);
+ goto err_clock_off;
+ }
}
- ret = mdp_path_config(mdp, &cmd, path);
- if (ret) {
- dev_err(dev, "mdp_path_config error\n");
- goto err_destroy_pkt;
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ ret = mdp_path_config(mdp, &cmd[i], paths[i]);
+ if (ret) {
+ dev_err(dev, "path %d mdp_path_config error\n", i);
+ goto err_clock_off;
+ }
}
- cb_param = kzalloc(sizeof(*cb_param), GFP_KERNEL);
- if (!cb_param) {
- ret = -ENOMEM;
- goto err_destroy_pkt;
- }
+ /* Prepare cmdq callback info */
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ cb_param[i] = kzalloc(sizeof(*cb_param[i]), GFP_KERNEL);
+ if (!cb_param[i]) {
+ ret = -ENOMEM;
+ dev_err(dev, "%s path %d alloc cb_param error\n", __func__, i);
+ goto err_destroy_cb_param;
+ }
- comps = kcalloc(param->config->num_components, sizeof(*comps),
- GFP_KERNEL);
- if (!comps) {
- ret = -ENOMEM;
- goto err_destroy_pkt;
- }
+ comps[i] = kcalloc(param->config[i].num_components,
+ sizeof(struct mdp_comp), GFP_KERNEL);
+ if (!comps[i]) {
+ ret = -ENOMEM;
+ dev_err(dev, "%s path %d alloc comps error\n", __func__, i);
+ goto err_destroy_cb_param;
+ }
- for (i = 0; i < param->config->num_components; i++) {
- if (is_dummy_engine(mdp, path->config->components[i].type))
- continue;
+ for (j = 0; j < param->config[i].num_components; j++) {
+ if (is_dummy_engine(mdp, paths[i]->config->components[j].type))
+ continue;
- memcpy(&comps[i], path->comps[i].comp,
- sizeof(struct mdp_comp));
- }
- cb_param->mdp = mdp;
- cb_param->user_cmdq_cb = param->cmdq_cb;
- cb_param->user_cb_data = param->cb_data;
- cb_param->pkt = cmd.pkt;
- cb_param->comps = comps;
- cb_param->num_comps = param->config->num_components;
- cb_param->mdp_ctx = param->mdp_ctx;
-
- cmdq_pkt_finalize(cmd.pkt);
- ret = cmdq_pkt_flush_async(cmd.pkt,
- mdp_handle_cmdq_callback,
- (void *)cb_param);
- if (ret) {
- dev_err(dev, "cmdq_pkt_flush_async fail!\n");
- goto err_clock_off;
+ memcpy(&comps[i][j], paths[i]->comps[j].comp,
+ sizeof(struct mdp_comp));
+ }
+ cb_param[i]->mdp = mdp;
+ cb_param[i]->user_cmdq_cb = param->cmdq_cb;
+ cb_param[i]->user_cb_data = param->cb_data;
+ cb_param[i]->pkt = cmd[i].pkt;
+ cb_param[i]->comps = comps[i];
+ cb_param[i]->num_comps = param->config[i].num_components;
+ cb_param[i]->mdp_ctx = param->mdp_ctx;
+ cb_param[i]->cmdq_user = param->cmdq_user;
+ cb_param[i]->dualpipe = (get_pipe_num(scenario) > 1 ? true : false);
+ }
+
+ /* Flush cmdq */
+ if (atomic_read(&mdp->cmdq_count[param->cmdq_user]))
+ dev_dbg(dev, "%s: Warning: cmdq_count:%d !\n", __func__,
+ atomic_read(&mdp->cmdq_count[param->cmdq_user]));
+
+ atomic_set(&mdp->cmdq_count[param->cmdq_user], get_pipe_num(scenario));
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ cmdq_pkt_finalize(cmd[i].pkt);
+
+ ret = cmdq_pkt_flush_async(cmd[i].pkt,
+ mdp_handle_cmdq_callback,
+ (void *)cb_param[i]);
+ if (ret) {
+ dev_err(dev, "pkt %d cmdq_pkt_flush_async fail!\n", i);
+ goto err_destroy_cmdq_request;
+ }
+ kfree(paths[i]);
}
- kfree(path);
+
return 0;
+err_destroy_cmdq_request:
+ atomic_set(&mdp->cmdq_count[param->cmdq_user], 0);
+err_destroy_cb_param:
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ kfree(comps[i]);
+ kfree(cb_param[i]);
+ }
err_clock_off:
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
@@ -898,15 +953,22 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
if (i >= 0)
mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
- mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
- cb_param->num_comps);
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ for (j = 0; j < param->config[i].num_components; j++) {
+ if (is_dummy_engine(mdp, paths[i]->config->components[j].type) == false)
+ mdp_comp_clock_off(&mdp->pdev->dev, paths[i]->comps[j].comp);
+ }
+ }
+err_destroy_paths:
+ for (i = 0; i < get_pipe_num(scenario); i++)
+ kfree(paths[i]);
err_destroy_pkt:
- cmdq_pkt_destroy(cmd.pkt);
+ for (i = 0; i < get_pipe_num(scenario); i++)
+ if (!IS_ERR(cmd[i].pkt))
+ cmdq_pkt_destroy(cmd[i].pkt);
+
atomic_dec(&mdp->job_count);
wake_up(&mdp->callback_wq);
- kfree(comps);
- kfree(cb_param);
- kfree(path);
return ret;
}
@@ -923,6 +985,7 @@ int mdp_cmdq_sendtask(struct platform_device *pdev, struct img_config *config,
.composes[0] = compose,
.cmdq_cb = cmdq_cb,
.cb_data = cb_data,
+ .cmdq_user = MDP_CMDQ_DL,
};
return mdp_cmdq_send(mdp, &task);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
index 16933507333b..7e6ad3760677 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
@@ -26,6 +26,7 @@ struct mdp_cmdq_param {
void (*cmdq_cb)(struct cmdq_cb_data data);
void *cb_data;
void *mdp_ctx;
+ u32 cmdq_user;
};
struct mdp_cmdq_cb_param {
@@ -37,6 +38,9 @@ struct mdp_cmdq_cb_param {
struct mdp_comp *comps;
u8 num_comps;
void *mdp_ctx;
+ u32 cmdq_user;
+ bool finalize;
+ bool dualpipe;
};
struct mdp_dev;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index d8161be8c556..495a6aa3a759 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -292,12 +292,20 @@ static int mdp_probe(struct platform_device *pdev)
mutex_init(&mdp->vpu_lock);
mutex_init(&mdp->m2m_lock);
- mdp->cmdq_clt = cmdq_mbox_create(dev, 0);
- if (IS_ERR(mdp->cmdq_clt)) {
- ret = PTR_ERR(mdp->cmdq_clt);
+ mdp->cmdq_clt[0] = cmdq_mbox_create(dev, 0);
+ if (IS_ERR(mdp->cmdq_clt[0])) {
+ ret = PTR_ERR(mdp->cmdq_clt[0]);
goto err_put_scp;
}
+ if (mdp->mdp_data->mdp_cfg->support_dual_pipe) {
+ mdp->cmdq_clt[1] = cmdq_mbox_create(dev, 1);
+ if (IS_ERR(mdp->cmdq_clt[1])) {
+ ret = PTR_ERR(mdp->cmdq_clt[1]);
+ goto err_mbox_destroy;
+ }
+ }
+
init_waitqueue_head(&mdp->callback_wq);
ida_init(&mdp->mdp_ida);
platform_set_drvdata(pdev, mdp);
@@ -308,7 +316,7 @@ static int mdp_probe(struct platform_device *pdev)
if (ret) {
dev_err(dev, "Failed to register v4l2 device\n");
ret = -EINVAL;
- goto err_mbox_destroy;
+ goto err_dual_mbox_destroy;
}
ret = mdp_m2m_device_register(mdp);
@@ -323,8 +331,11 @@ static int mdp_probe(struct platform_device *pdev)
err_unregister_device:
v4l2_device_unregister(&mdp->v4l2_dev);
+err_dual_mbox_destroy:
+ if (mdp->mdp_data->mdp_cfg->support_dual_pipe)
+ cmdq_mbox_destroy(mdp->cmdq_clt[1]);
err_mbox_destroy:
- cmdq_mbox_destroy(mdp->cmdq_clt);
+ cmdq_mbox_destroy(mdp->cmdq_clt[0]);
err_put_scp:
scp_put(mdp->scp);
err_destroy_clock_wq:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index 8ee70763a18f..0fb932ad3560 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -15,6 +15,7 @@
#include "mtk-mdp3-vpu.h"
#define MDP_MODULE_NAME "mtk-mdp3"
+#define MDP_DUAL_PIPE 2
enum mdp_buffer_usage {
MDP_BUFFER_USAGE_HW_READ,
@@ -24,6 +25,12 @@ enum mdp_buffer_usage {
MDP_BUFFER_USAGE_WPE,
};
+enum mdp_cmdq_usage {
+ MDP_CMDQ_V4L2,
+ MDP_CMDQ_DL,
+ MDP_CMDQ_NUM
+};
+
struct mdp_platform_config {
bool rdma_support_10bit;
bool rdma_rsz1_sram_sharing;
@@ -43,6 +50,7 @@ struct mdp_platform_config {
u8 tdshp_dyn_contrast_version;
u32 gce_event_offset;
bool support_multi_larb;
+ bool support_dual_pipe;
};
struct mtk_mdp_driver_data {
@@ -77,7 +85,7 @@ struct mdp_dev {
s32 vpu_count;
u32 id_count;
struct ida mdp_ida;
- struct cmdq_client *cmdq_clt;
+ struct cmdq_client *cmdq_clt[MDP_DUAL_PIPE];
wait_queue_head_t callback_wq;
struct v4l2_device v4l2_dev;
@@ -87,6 +95,7 @@ struct mdp_dev {
struct mutex m2m_lock;
atomic_t suspended;
atomic_t job_count;
+ atomic_t cmdq_count[MDP_CMDQ_NUM];
};
struct mdp_pipe_info {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index 1e749bb2b338..72a1864d880c 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -95,6 +95,10 @@ static void mdp_m2m_worker(struct work_struct *work)
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
mdp_set_src_config(¶m.inputs[0], frame, &src_vb->vb2_buf);
+ mdp_set_scenario(ctx->mdp_dev, ¶m, frame);
+ if (param.frame_change)
+ dev_info(&ctx->mdp_dev->pdev->dev,
+ "MDP Scenario: %d\n", param.type);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
@@ -115,6 +119,7 @@ static void mdp_m2m_worker(struct work_struct *work)
task.cmdq_cb = NULL;
task.cb_data = NULL;
task.mdp_ctx = ctx;
+ task.cmdq_user = MDP_CMDQ_V4L2;
ret = mdp_cmdq_send(ctx->mdp_dev, &task);
if (ret) {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index 8c2b74c67273..c0a7e3569853 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -11,6 +11,8 @@
#include "mtk-mdp3-regs.h"
#include "mtk-mdp3-m2m.h"
+#define FHD (1920 * 1080)
+
static const struct mdp_format *mdp_formats;
static u32 format_len;
@@ -427,6 +429,22 @@ static u32 mdp_fmt_get_plane_size(const struct mdp_format *fmt,
return 0;
}
+void mdp_set_scenario(struct mdp_dev *mdp,
+ struct img_ipi_frameparam *param,
+ struct mdp_frame *frame)
+{
+ u32 width = frame->format.fmt.pix_mp.width;
+ u32 height = frame->format.fmt.pix_mp.height;
+
+ if (!mdp)
+ return;
+
+ if (mdp->mdp_data->mdp_cfg->support_dual_pipe) {
+ if ((width * height) >= FHD)
+ param->type = MDP_STREAM_TYPE_DUAL_BITBLT;
+ }
+}
+
static void mdp_prepare_buffer(struct img_image_buffer *b,
struct mdp_frame *frame, struct vb2_buffer *vb)
{
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 1ef32b747233..3547ce10948f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -10,6 +10,7 @@
#include <linux/videodev2.h>
#include <media/videobuf2-core.h>
#include "mtk-img-ipi.h"
+#include "mtk-mdp3-cmdq.h"
/*
* MDP native color code
@@ -407,6 +408,9 @@ int mdp_try_crop(struct mdp_m2m_ctx *ctx, struct v4l2_rect *r,
int mdp_check_scaling_ratio(const struct v4l2_rect *crop,
const struct v4l2_rect *compose, s32 rotation,
const struct mdp_limit *limit);
+void mdp_set_scenario(struct mdp_dev *mdp,
+ struct img_ipi_frameparam *param,
+ struct mdp_frame *frame);
void mdp_set_src_config(struct img_input *in,
struct mdp_frame *frame, struct vb2_buffer *vb);
void mdp_set_dst_config(struct img_output *out,
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
index fc008d96c7c0..035fa3e55335 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
@@ -10,7 +10,7 @@
#include "mtk-mdp3-core.h"
#define MDP_VPU_MESSAGE_TIMEOUT 500U
-#define vpu_alloc_size 0x600000
+#define vpu_alloc_size 0x7F8000
static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
{
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
index e831070b44d0..3140d2925a1a 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
@@ -39,6 +39,7 @@ struct mdp_ipi_deinit_msg {
enum mdp_config_id {
MDP_DEV_M2M = 0,
+ MDP_DEV_M2M_2ND = 1,
MDP_CONFIG_POOL_SIZE /* ALWAYS keep at the end */
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 10/14] media: platform: mtk-mdp3: Add dual pipe feature support
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add dual pipe feature which uses two svpp to execute dma
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/media/platform/mtk-mdp3/mt8195_mdp.h | 1 +
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 245 +++++++++++-------
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 4 +
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 21 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 11 +-
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 5 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 18 ++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 4 +
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 2 +-
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 1 +
10 files changed, 214 insertions(+), 98 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mt8195_mdp.h b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
index f69bc86bcd1e..dc9454cfd33a 100644
--- a/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
+++ b/drivers/media/platform/mtk-mdp3/mt8195_mdp.h
@@ -24,6 +24,7 @@ static const struct mdp_platform_config mt8195_plat_cfg = {
.mdp_version_6885 = true,
.gce_event_offset = 0,
.support_multi_larb = true,
+ .support_dual_pipe = true,
};
enum mt8195_mdp_comp_id {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index ce9326cc790f..86b7d83be22c 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -29,6 +29,9 @@ struct mdp_path {
((ctx)->comp->ops && (ctx)->comp->ops->op)
#define call_op(ctx, op, ...) \
(has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0)
+#define get_pipe_num(scenario) \
+ ((scenario) == MDP_STREAM_TYPE_DUAL_BITBLT ? 2 : 1)
+
struct mdp_path_subfrm {
s32 mutex_id;
u32 mutex_mod;
@@ -707,25 +710,31 @@ static void mdp_auto_release_work(struct work_struct *work)
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
int i;
+ bool finalize;
cb_param = container_of(work, struct mdp_cmdq_cb_param,
auto_release_work);
mdp = cb_param->mdp;
+ finalize = cb_param->finalize;
- i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
- mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+ if (finalize) {
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
- i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
- if (i >= 0)
- mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+ }
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
kfree(cb_param->comps);
kfree(cb_param);
- atomic_dec(&mdp->job_count);
- wake_up(&mdp->callback_wq);
+ if (finalize) {
+ atomic_dec(&mdp->job_count);
+ wake_up(&mdp->callback_wq);
+ }
}
static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
@@ -744,7 +753,13 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
mdp = cb_param->mdp;
dev = &mdp->pdev->dev;
- if (cb_param->mdp_ctx)
+ if (cb_param->dualpipe)
+ cb_param->finalize =
+ (atomic_dec_and_test(&mdp->cmdq_count[cb_param->cmdq_user]));
+ else
+ cb_param->finalize = true;
+
+ if (cb_param->finalize && cb_param->mdp_ctx)
mdp_m2m_job_finish(cb_param->mdp_ctx);
if (cb_param->user_cmdq_cb) {
@@ -779,52 +794,62 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
{
- struct mmsys_cmdq_cmd cmd;
- struct mdp_path *path = NULL;
- struct mdp_cmdq_cb_param *cb_param = NULL;
- struct mdp_comp *comps = NULL;
+ struct mmsys_cmdq_cmd cmd[MDP_DUAL_PIPE];
+ struct mdp_path *paths[MDP_DUAL_PIPE] = {NULL};
+ struct mdp_cmdq_cb_param *cb_param[MDP_DUAL_PIPE] = {NULL};
+ struct mdp_comp *comps[MDP_DUAL_PIPE] = {NULL};
struct device *dev = &mdp->pdev->dev;
- int i, ret;
+
+ enum mdp_stream_type scenario = param->param->type;
+ int i, j, ret;
if (atomic_read(&mdp->suspended))
return -ECANCELED;
atomic_inc(&mdp->job_count);
- cmd.pkt = cmdq_pkt_create(mdp->cmdq_clt, SZ_16K);
- if (IS_ERR(cmd.pkt)) {
- atomic_dec(&mdp->job_count);
- wake_up(&mdp->callback_wq);
- return PTR_ERR(cmd.pkt);
+ /* Prepare cmdq pkt */
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ cmd[i].pkt = cmdq_pkt_create(mdp->cmdq_clt[i], SZ_16K);
+ if (IS_ERR(cmd[i].pkt)) {
+ ret = PTR_ERR(cmd[i].pkt);
+ dev_err(dev, "%s path %d cmdq_pkt_create error\n", __func__, i);
+ goto err_destroy_pkt;
+ }
+ cmd[i].event = &mdp->event[0];
}
- cmd.event = &mdp->event[0];
- path = kzalloc(sizeof(*path), GFP_KERNEL);
- if (!path) {
- ret = -ENOMEM;
- goto err_destroy_pkt;
- }
+ /* Prepare path info */
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ paths[i] = kzalloc(sizeof(*paths[i]), GFP_KERNEL);
+ if (!paths[i]) {
+ ret = -ENOMEM;
+ dev_err(dev, "%s alloc paths error\n", __func__);
+ goto err_destroy_paths;
+ }
- path->mdp_dev = mdp;
- path->config = param->config;
- path->param = param->param;
- for (i = 0; i < param->param->num_outputs; i++) {
- path->bounds[i].left = 0;
- path->bounds[i].top = 0;
- path->bounds[i].width =
- param->param->outputs[i].buffer.format.width;
- path->bounds[i].height =
- param->param->outputs[i].buffer.format.height;
- path->composes[i] = param->composes[i] ?
- param->composes[i] : &path->bounds[i];
- }
+ paths[i]->mdp_dev = mdp;
+ paths[i]->config = ¶m->config[i];
+ paths[i]->param = param->param;
+ for (j = 0; j < param->param->num_outputs; j++) {
+ paths[i]->bounds[j].left = 0;
+ paths[i]->bounds[j].top = 0;
+ paths[i]->bounds[j].width =
+ param->param->outputs[j].buffer.format.width;
+ paths[i]->bounds[j].height =
+ param->param->outputs[j].buffer.format.height;
+ paths[i]->composes[j] = param->composes[j] ?
+ param->composes[j] : &paths[i]->bounds[j];
+ }
- ret = mdp_path_ctx_init(mdp, path);
- if (ret) {
- dev_err(dev, "mdp_path_ctx_init error\n");
- goto err_destroy_pkt;
+ ret = mdp_path_ctx_init(mdp, paths[i]);
+ if (ret) {
+ dev_err(dev, "%s mdp_path_ctx_init error at path %d\n", __func__, i);
+ goto err_destroy_paths;
+ }
}
+ /* Setup clock and cmdq buffer */
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
@@ -832,64 +857,94 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
if (i >= 0)
mtk_mutex_prepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
- for (i = 0; i < param->config->num_components; i++) {
- if (is_dummy_engine(mdp, path->config->components[i].type))
- continue;
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ for (j = 0; j < param->config[i].num_components; j++) {
+ if (is_dummy_engine(mdp, paths[i]->config->components[j].type))
+ continue;
- mdp_comp_clock_on(&mdp->pdev->dev, path->comps[i].comp);
+ mdp_comp_clock_on(&mdp->pdev->dev, paths[i]->comps[j].comp);
+ }
}
if (mdp->mdp_data->mdp_cfg->mdp_version_8195) {
- ret = mdp_hyfbc_config(mdp, &cmd, path, param);
- if (ret)
- goto err_destroy_pkt;
+ ret = mdp_hyfbc_config(mdp, &cmd[0], paths[0], param);
+ if (ret) {
+ dev_err(dev, "%s mdp_hyfbc_config error\n", __func__);
+ goto err_clock_off;
+ }
}
- ret = mdp_path_config(mdp, &cmd, path);
- if (ret) {
- dev_err(dev, "mdp_path_config error\n");
- goto err_destroy_pkt;
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ ret = mdp_path_config(mdp, &cmd[i], paths[i]);
+ if (ret) {
+ dev_err(dev, "path %d mdp_path_config error\n", i);
+ goto err_clock_off;
+ }
}
- cb_param = kzalloc(sizeof(*cb_param), GFP_KERNEL);
- if (!cb_param) {
- ret = -ENOMEM;
- goto err_destroy_pkt;
- }
+ /* Prepare cmdq callback info */
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ cb_param[i] = kzalloc(sizeof(*cb_param[i]), GFP_KERNEL);
+ if (!cb_param[i]) {
+ ret = -ENOMEM;
+ dev_err(dev, "%s path %d alloc cb_param error\n", __func__, i);
+ goto err_destroy_cb_param;
+ }
- comps = kcalloc(param->config->num_components, sizeof(*comps),
- GFP_KERNEL);
- if (!comps) {
- ret = -ENOMEM;
- goto err_destroy_pkt;
- }
+ comps[i] = kcalloc(param->config[i].num_components,
+ sizeof(struct mdp_comp), GFP_KERNEL);
+ if (!comps[i]) {
+ ret = -ENOMEM;
+ dev_err(dev, "%s path %d alloc comps error\n", __func__, i);
+ goto err_destroy_cb_param;
+ }
- for (i = 0; i < param->config->num_components; i++) {
- if (is_dummy_engine(mdp, path->config->components[i].type))
- continue;
+ for (j = 0; j < param->config[i].num_components; j++) {
+ if (is_dummy_engine(mdp, paths[i]->config->components[j].type))
+ continue;
- memcpy(&comps[i], path->comps[i].comp,
- sizeof(struct mdp_comp));
- }
- cb_param->mdp = mdp;
- cb_param->user_cmdq_cb = param->cmdq_cb;
- cb_param->user_cb_data = param->cb_data;
- cb_param->pkt = cmd.pkt;
- cb_param->comps = comps;
- cb_param->num_comps = param->config->num_components;
- cb_param->mdp_ctx = param->mdp_ctx;
-
- cmdq_pkt_finalize(cmd.pkt);
- ret = cmdq_pkt_flush_async(cmd.pkt,
- mdp_handle_cmdq_callback,
- (void *)cb_param);
- if (ret) {
- dev_err(dev, "cmdq_pkt_flush_async fail!\n");
- goto err_clock_off;
+ memcpy(&comps[i][j], paths[i]->comps[j].comp,
+ sizeof(struct mdp_comp));
+ }
+ cb_param[i]->mdp = mdp;
+ cb_param[i]->user_cmdq_cb = param->cmdq_cb;
+ cb_param[i]->user_cb_data = param->cb_data;
+ cb_param[i]->pkt = cmd[i].pkt;
+ cb_param[i]->comps = comps[i];
+ cb_param[i]->num_comps = param->config[i].num_components;
+ cb_param[i]->mdp_ctx = param->mdp_ctx;
+ cb_param[i]->cmdq_user = param->cmdq_user;
+ cb_param[i]->dualpipe = (get_pipe_num(scenario) > 1 ? true : false);
+ }
+
+ /* Flush cmdq */
+ if (atomic_read(&mdp->cmdq_count[param->cmdq_user]))
+ dev_dbg(dev, "%s: Warning: cmdq_count:%d !\n", __func__,
+ atomic_read(&mdp->cmdq_count[param->cmdq_user]));
+
+ atomic_set(&mdp->cmdq_count[param->cmdq_user], get_pipe_num(scenario));
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ cmdq_pkt_finalize(cmd[i].pkt);
+
+ ret = cmdq_pkt_flush_async(cmd[i].pkt,
+ mdp_handle_cmdq_callback,
+ (void *)cb_param[i]);
+ if (ret) {
+ dev_err(dev, "pkt %d cmdq_pkt_flush_async fail!\n", i);
+ goto err_destroy_cmdq_request;
+ }
+ kfree(paths[i]);
}
- kfree(path);
+
return 0;
+err_destroy_cmdq_request:
+ atomic_set(&mdp->cmdq_count[param->cmdq_user], 0);
+err_destroy_cb_param:
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ kfree(comps[i]);
+ kfree(cb_param[i]);
+ }
err_clock_off:
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
@@ -898,15 +953,22 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
if (i >= 0)
mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
- mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
- cb_param->num_comps);
+ for (i = 0; i < get_pipe_num(scenario); i++) {
+ for (j = 0; j < param->config[i].num_components; j++) {
+ if (is_dummy_engine(mdp, paths[i]->config->components[j].type) == false)
+ mdp_comp_clock_off(&mdp->pdev->dev, paths[i]->comps[j].comp);
+ }
+ }
+err_destroy_paths:
+ for (i = 0; i < get_pipe_num(scenario); i++)
+ kfree(paths[i]);
err_destroy_pkt:
- cmdq_pkt_destroy(cmd.pkt);
+ for (i = 0; i < get_pipe_num(scenario); i++)
+ if (!IS_ERR(cmd[i].pkt))
+ cmdq_pkt_destroy(cmd[i].pkt);
+
atomic_dec(&mdp->job_count);
wake_up(&mdp->callback_wq);
- kfree(comps);
- kfree(cb_param);
- kfree(path);
return ret;
}
@@ -923,6 +985,7 @@ int mdp_cmdq_sendtask(struct platform_device *pdev, struct img_config *config,
.composes[0] = compose,
.cmdq_cb = cmdq_cb,
.cb_data = cb_data,
+ .cmdq_user = MDP_CMDQ_DL,
};
return mdp_cmdq_send(mdp, &task);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
index 16933507333b..7e6ad3760677 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
@@ -26,6 +26,7 @@ struct mdp_cmdq_param {
void (*cmdq_cb)(struct cmdq_cb_data data);
void *cb_data;
void *mdp_ctx;
+ u32 cmdq_user;
};
struct mdp_cmdq_cb_param {
@@ -37,6 +38,9 @@ struct mdp_cmdq_cb_param {
struct mdp_comp *comps;
u8 num_comps;
void *mdp_ctx;
+ u32 cmdq_user;
+ bool finalize;
+ bool dualpipe;
};
struct mdp_dev;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index d8161be8c556..495a6aa3a759 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -292,12 +292,20 @@ static int mdp_probe(struct platform_device *pdev)
mutex_init(&mdp->vpu_lock);
mutex_init(&mdp->m2m_lock);
- mdp->cmdq_clt = cmdq_mbox_create(dev, 0);
- if (IS_ERR(mdp->cmdq_clt)) {
- ret = PTR_ERR(mdp->cmdq_clt);
+ mdp->cmdq_clt[0] = cmdq_mbox_create(dev, 0);
+ if (IS_ERR(mdp->cmdq_clt[0])) {
+ ret = PTR_ERR(mdp->cmdq_clt[0]);
goto err_put_scp;
}
+ if (mdp->mdp_data->mdp_cfg->support_dual_pipe) {
+ mdp->cmdq_clt[1] = cmdq_mbox_create(dev, 1);
+ if (IS_ERR(mdp->cmdq_clt[1])) {
+ ret = PTR_ERR(mdp->cmdq_clt[1]);
+ goto err_mbox_destroy;
+ }
+ }
+
init_waitqueue_head(&mdp->callback_wq);
ida_init(&mdp->mdp_ida);
platform_set_drvdata(pdev, mdp);
@@ -308,7 +316,7 @@ static int mdp_probe(struct platform_device *pdev)
if (ret) {
dev_err(dev, "Failed to register v4l2 device\n");
ret = -EINVAL;
- goto err_mbox_destroy;
+ goto err_dual_mbox_destroy;
}
ret = mdp_m2m_device_register(mdp);
@@ -323,8 +331,11 @@ static int mdp_probe(struct platform_device *pdev)
err_unregister_device:
v4l2_device_unregister(&mdp->v4l2_dev);
+err_dual_mbox_destroy:
+ if (mdp->mdp_data->mdp_cfg->support_dual_pipe)
+ cmdq_mbox_destroy(mdp->cmdq_clt[1]);
err_mbox_destroy:
- cmdq_mbox_destroy(mdp->cmdq_clt);
+ cmdq_mbox_destroy(mdp->cmdq_clt[0]);
err_put_scp:
scp_put(mdp->scp);
err_destroy_clock_wq:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index 8ee70763a18f..0fb932ad3560 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -15,6 +15,7 @@
#include "mtk-mdp3-vpu.h"
#define MDP_MODULE_NAME "mtk-mdp3"
+#define MDP_DUAL_PIPE 2
enum mdp_buffer_usage {
MDP_BUFFER_USAGE_HW_READ,
@@ -24,6 +25,12 @@ enum mdp_buffer_usage {
MDP_BUFFER_USAGE_WPE,
};
+enum mdp_cmdq_usage {
+ MDP_CMDQ_V4L2,
+ MDP_CMDQ_DL,
+ MDP_CMDQ_NUM
+};
+
struct mdp_platform_config {
bool rdma_support_10bit;
bool rdma_rsz1_sram_sharing;
@@ -43,6 +50,7 @@ struct mdp_platform_config {
u8 tdshp_dyn_contrast_version;
u32 gce_event_offset;
bool support_multi_larb;
+ bool support_dual_pipe;
};
struct mtk_mdp_driver_data {
@@ -77,7 +85,7 @@ struct mdp_dev {
s32 vpu_count;
u32 id_count;
struct ida mdp_ida;
- struct cmdq_client *cmdq_clt;
+ struct cmdq_client *cmdq_clt[MDP_DUAL_PIPE];
wait_queue_head_t callback_wq;
struct v4l2_device v4l2_dev;
@@ -87,6 +95,7 @@ struct mdp_dev {
struct mutex m2m_lock;
atomic_t suspended;
atomic_t job_count;
+ atomic_t cmdq_count[MDP_CMDQ_NUM];
};
struct mdp_pipe_info {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index 1e749bb2b338..72a1864d880c 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -95,6 +95,10 @@ static void mdp_m2m_worker(struct work_struct *work)
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
mdp_set_src_config(¶m.inputs[0], frame, &src_vb->vb2_buf);
+ mdp_set_scenario(ctx->mdp_dev, ¶m, frame);
+ if (param.frame_change)
+ dev_info(&ctx->mdp_dev->pdev->dev,
+ "MDP Scenario: %d\n", param.type);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
@@ -115,6 +119,7 @@ static void mdp_m2m_worker(struct work_struct *work)
task.cmdq_cb = NULL;
task.cb_data = NULL;
task.mdp_ctx = ctx;
+ task.cmdq_user = MDP_CMDQ_V4L2;
ret = mdp_cmdq_send(ctx->mdp_dev, &task);
if (ret) {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index 8c2b74c67273..c0a7e3569853 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -11,6 +11,8 @@
#include "mtk-mdp3-regs.h"
#include "mtk-mdp3-m2m.h"
+#define FHD (1920 * 1080)
+
static const struct mdp_format *mdp_formats;
static u32 format_len;
@@ -427,6 +429,22 @@ static u32 mdp_fmt_get_plane_size(const struct mdp_format *fmt,
return 0;
}
+void mdp_set_scenario(struct mdp_dev *mdp,
+ struct img_ipi_frameparam *param,
+ struct mdp_frame *frame)
+{
+ u32 width = frame->format.fmt.pix_mp.width;
+ u32 height = frame->format.fmt.pix_mp.height;
+
+ if (!mdp)
+ return;
+
+ if (mdp->mdp_data->mdp_cfg->support_dual_pipe) {
+ if ((width * height) >= FHD)
+ param->type = MDP_STREAM_TYPE_DUAL_BITBLT;
+ }
+}
+
static void mdp_prepare_buffer(struct img_image_buffer *b,
struct mdp_frame *frame, struct vb2_buffer *vb)
{
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 1ef32b747233..3547ce10948f 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -10,6 +10,7 @@
#include <linux/videodev2.h>
#include <media/videobuf2-core.h>
#include "mtk-img-ipi.h"
+#include "mtk-mdp3-cmdq.h"
/*
* MDP native color code
@@ -407,6 +408,9 @@ int mdp_try_crop(struct mdp_m2m_ctx *ctx, struct v4l2_rect *r,
int mdp_check_scaling_ratio(const struct v4l2_rect *crop,
const struct v4l2_rect *compose, s32 rotation,
const struct mdp_limit *limit);
+void mdp_set_scenario(struct mdp_dev *mdp,
+ struct img_ipi_frameparam *param,
+ struct mdp_frame *frame);
void mdp_set_src_config(struct img_input *in,
struct mdp_frame *frame, struct vb2_buffer *vb);
void mdp_set_dst_config(struct img_output *out,
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
index fc008d96c7c0..035fa3e55335 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
@@ -10,7 +10,7 @@
#include "mtk-mdp3-core.h"
#define MDP_VPU_MESSAGE_TIMEOUT 500U
-#define vpu_alloc_size 0x600000
+#define vpu_alloc_size 0x7F8000
static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
{
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
index e831070b44d0..3140d2925a1a 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
@@ -39,6 +39,7 @@ struct mdp_ipi_deinit_msg {
enum mdp_config_id {
MDP_DEV_M2M = 0,
+ MDP_DEV_M2M_2ND = 1,
MDP_CONFIG_POOL_SIZE /* ALWAYS keep at the end */
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 11/14] media: platform: mtk-mdp3: Revise frame change criteria
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
frame_change will trigger MDP SCP to re-calculate path and parameter.
MDP fails when it doesn't get correct parameters to process frame,
and it will activate by the following conditions:
1. first frame
2. Scenario changes (single/dual pipe)
3. input size changes
4. input format changes
5. output size changes (crop included)
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 2 ++
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 22 +++++++++++++++----
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 19 ++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 9 ++++++++
4 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index 0fb932ad3560..0eb08ce69781 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -11,6 +11,7 @@
#include <media/v4l2-mem2mem.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include "mtk-mdp3-regs.h"
#include "mtk-mdp3-comp.h"
#include "mtk-mdp3-vpu.h"
@@ -96,6 +97,7 @@ struct mdp_dev {
atomic_t suspended;
atomic_t job_count;
atomic_t cmdq_count[MDP_CMDQ_NUM];
+ struct mdp_framechange_param prev_image;
};
struct mdp_pipe_info {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index 72a1864d880c..9afe56882208 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -77,6 +77,7 @@ static void mdp_m2m_worker(struct work_struct *work)
struct vb2_v4l2_buffer *src_vb, *dst_vb;
struct img_ipi_frameparam param = {0};
struct mdp_cmdq_param task = {0};
+ struct mdp_framechange_param cur_frame = {0};
enum vb2_buffer_state vb_state = VB2_BUF_STATE_ERROR;
int ret;
@@ -90,20 +91,33 @@ static void mdp_m2m_worker(struct work_struct *work)
param.type = ctx->curr_param.type;
param.num_inputs = 1;
param.num_outputs = 1;
- param.frame_change = (ctx->frame_count[MDP_M2M_SRC] == 0);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
mdp_set_src_config(¶m.inputs[0], frame, &src_vb->vb2_buf);
mdp_set_scenario(ctx->mdp_dev, ¶m, frame);
- if (param.frame_change)
- dev_info(&ctx->mdp_dev->pdev->dev,
- "MDP Scenario: %d\n", param.type);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
mdp_set_dst_config(¶m.outputs[0], frame, &dst_vb->vb2_buf);
+ cur_frame.scenario = param.type;
+ cur_frame.frame_count = ctx->frame_count[MDP_M2M_SRC];
+ memcpy(&cur_frame.in, ¶m.inputs[0], sizeof(cur_frame.in));
+ memcpy(&cur_frame.out, ¶m.outputs[0], sizeof(cur_frame.out));
+
+ if (mdp_is_framechange(&ctx->mdp_dev->prev_image, &cur_frame)) {
+ memcpy(&ctx->mdp_dev->prev_image, &cur_frame,
+ sizeof(struct mdp_framechange_param));
+ param.frame_change = true;
+ } else {
+ param.frame_change = false;
+ }
+
+ if (param.frame_change)
+ dev_dbg(&ctx->mdp_dev->pdev->dev,
+ "MDP Scenario: %d\n", param.type);
+
param.timestamp = src_vb->vb2_buf.timestamp;
ret = mdp_vpu_process(&ctx->vpu, ¶m);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index c0a7e3569853..ccd9c338ff49 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -429,6 +429,25 @@ static u32 mdp_fmt_get_plane_size(const struct mdp_format *fmt,
return 0;
}
+bool mdp_is_framechange(struct mdp_framechange_param *prev,
+ struct mdp_framechange_param *cur)
+{
+ if (cur->frame_count == 0 ||
+ prev->scenario != cur->scenario ||
+ prev->in.buffer.format.colorformat != cur->in.buffer.format.colorformat ||
+ prev->in.buffer.format.width != cur->in.buffer.format.width ||
+ prev->in.buffer.format.height != cur->in.buffer.format.height ||
+ prev->out.buffer.format.width != cur->out.buffer.format.width ||
+ prev->out.buffer.format.height != cur->out.buffer.format.height ||
+ prev->out.crop.left != cur->out.crop.left ||
+ prev->out.crop.top != cur->out.crop.top ||
+ prev->out.crop.width != cur->out.crop.width ||
+ prev->out.crop.height != cur->out.crop.height)
+ return true;
+
+ return false;
+}
+
void mdp_set_scenario(struct mdp_dev *mdp,
struct img_ipi_frameparam *param,
struct mdp_frame *frame)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 3547ce10948f..436d5c899bc5 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -397,6 +397,13 @@ struct mdp_frameparam {
enum v4l2_quantization quant;
};
+struct mdp_framechange_param {
+ u8 scenario;
+ u32 frame_count;
+ struct img_input in;
+ struct img_output out;
+};
+
int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f);
const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
struct mdp_frameparam *param,
@@ -408,6 +415,8 @@ int mdp_try_crop(struct mdp_m2m_ctx *ctx, struct v4l2_rect *r,
int mdp_check_scaling_ratio(const struct v4l2_rect *crop,
const struct v4l2_rect *compose, s32 rotation,
const struct mdp_limit *limit);
+bool mdp_is_framechange(struct mdp_framechange_param *prev,
+ struct mdp_framechange_param *cur);
void mdp_set_scenario(struct mdp_dev *mdp,
struct img_ipi_frameparam *param,
struct mdp_frame *frame);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 11/14] media: platform: mtk-mdp3: Revise frame change criteria
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
frame_change will trigger MDP SCP to re-calculate path and parameter.
MDP fails when it doesn't get correct parameters to process frame,
and it will activate by the following conditions:
1. first frame
2. Scenario changes (single/dual pipe)
3. input size changes
4. input format changes
5. output size changes (crop included)
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 2 ++
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 22 +++++++++++++++----
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 19 ++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 9 ++++++++
4 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index 0fb932ad3560..0eb08ce69781 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -11,6 +11,7 @@
#include <media/v4l2-mem2mem.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include "mtk-mdp3-regs.h"
#include "mtk-mdp3-comp.h"
#include "mtk-mdp3-vpu.h"
@@ -96,6 +97,7 @@ struct mdp_dev {
atomic_t suspended;
atomic_t job_count;
atomic_t cmdq_count[MDP_CMDQ_NUM];
+ struct mdp_framechange_param prev_image;
};
struct mdp_pipe_info {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index 72a1864d880c..9afe56882208 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -77,6 +77,7 @@ static void mdp_m2m_worker(struct work_struct *work)
struct vb2_v4l2_buffer *src_vb, *dst_vb;
struct img_ipi_frameparam param = {0};
struct mdp_cmdq_param task = {0};
+ struct mdp_framechange_param cur_frame = {0};
enum vb2_buffer_state vb_state = VB2_BUF_STATE_ERROR;
int ret;
@@ -90,20 +91,33 @@ static void mdp_m2m_worker(struct work_struct *work)
param.type = ctx->curr_param.type;
param.num_inputs = 1;
param.num_outputs = 1;
- param.frame_change = (ctx->frame_count[MDP_M2M_SRC] == 0);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
mdp_set_src_config(¶m.inputs[0], frame, &src_vb->vb2_buf);
mdp_set_scenario(ctx->mdp_dev, ¶m, frame);
- if (param.frame_change)
- dev_info(&ctx->mdp_dev->pdev->dev,
- "MDP Scenario: %d\n", param.type);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
mdp_set_dst_config(¶m.outputs[0], frame, &dst_vb->vb2_buf);
+ cur_frame.scenario = param.type;
+ cur_frame.frame_count = ctx->frame_count[MDP_M2M_SRC];
+ memcpy(&cur_frame.in, ¶m.inputs[0], sizeof(cur_frame.in));
+ memcpy(&cur_frame.out, ¶m.outputs[0], sizeof(cur_frame.out));
+
+ if (mdp_is_framechange(&ctx->mdp_dev->prev_image, &cur_frame)) {
+ memcpy(&ctx->mdp_dev->prev_image, &cur_frame,
+ sizeof(struct mdp_framechange_param));
+ param.frame_change = true;
+ } else {
+ param.frame_change = false;
+ }
+
+ if (param.frame_change)
+ dev_dbg(&ctx->mdp_dev->pdev->dev,
+ "MDP Scenario: %d\n", param.type);
+
param.timestamp = src_vb->vb2_buf.timestamp;
ret = mdp_vpu_process(&ctx->vpu, ¶m);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index c0a7e3569853..ccd9c338ff49 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -429,6 +429,25 @@ static u32 mdp_fmt_get_plane_size(const struct mdp_format *fmt,
return 0;
}
+bool mdp_is_framechange(struct mdp_framechange_param *prev,
+ struct mdp_framechange_param *cur)
+{
+ if (cur->frame_count == 0 ||
+ prev->scenario != cur->scenario ||
+ prev->in.buffer.format.colorformat != cur->in.buffer.format.colorformat ||
+ prev->in.buffer.format.width != cur->in.buffer.format.width ||
+ prev->in.buffer.format.height != cur->in.buffer.format.height ||
+ prev->out.buffer.format.width != cur->out.buffer.format.width ||
+ prev->out.buffer.format.height != cur->out.buffer.format.height ||
+ prev->out.crop.left != cur->out.crop.left ||
+ prev->out.crop.top != cur->out.crop.top ||
+ prev->out.crop.width != cur->out.crop.width ||
+ prev->out.crop.height != cur->out.crop.height)
+ return true;
+
+ return false;
+}
+
void mdp_set_scenario(struct mdp_dev *mdp,
struct img_ipi_frameparam *param,
struct mdp_frame *frame)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index 3547ce10948f..436d5c899bc5 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -397,6 +397,13 @@ struct mdp_frameparam {
enum v4l2_quantization quant;
};
+struct mdp_framechange_param {
+ u8 scenario;
+ u32 frame_count;
+ struct img_input in;
+ struct img_output out;
+};
+
int mdp_enum_fmt_mplane(struct v4l2_fmtdesc *f);
const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f,
struct mdp_frameparam *param,
@@ -408,6 +415,8 @@ int mdp_try_crop(struct mdp_m2m_ctx *ctx, struct v4l2_rect *r,
int mdp_check_scaling_ratio(const struct v4l2_rect *crop,
const struct v4l2_rect *compose, s32 rotation,
const struct mdp_limit *limit);
+bool mdp_is_framechange(struct mdp_framechange_param *prev,
+ struct mdp_framechange_param *cur);
void mdp_set_scenario(struct mdp_dev *mdp,
struct img_ipi_frameparam *param,
struct mdp_frame *frame);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 12/14] media: platform: mtk-mdp3: Reconfigure shared memory
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
MDP communicates with SCP through shared memory.
SCP is responsible for calculating information that MDP needed,
however SCP has poor performance.
In order to improve performance,
shared memory is reconfigured into three buffer
to make more logical sense.
The third buffer - path buffer
which allocated in scp before is used for scp calculation.
This buffer need to be clear when frame_change occurs,
but it costs lot of time for scp doing memset which decreases performance.
Thus we move this buffer to kernel,
do memset in ap side to accelerate frame processing.
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 106 +++++++++---------
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 8 ++
2 files changed, 58 insertions(+), 56 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
index 035fa3e55335..73da786b5270 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
@@ -10,7 +10,7 @@
#include "mtk-mdp3-core.h"
#define MDP_VPU_MESSAGE_TIMEOUT 500U
-#define vpu_alloc_size 0x7F8000
+#define MDP_VPU_PATH_SIZE 0x78000
static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
{
@@ -19,23 +19,46 @@ static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu)
{
- if (vpu->work && vpu->work_addr)
- return 0;
+ vpu->work = dma_alloc_wc(scp_get_device(vpu->scp), vpu->work_size,
+ &vpu->work_addr, GFP_KERNEL);
+ if (!vpu->work)
+ goto err_return;
- vpu->work = dma_alloc_coherent(scp_get_device(vpu->scp), vpu_alloc_size,
- &vpu->work_addr, GFP_KERNEL);
+ vpu->config = dma_alloc_wc(scp_get_device(vpu->scp), vpu->config_size,
+ &vpu->config_addr, GFP_KERNEL);
+ if (!vpu->config)
+ goto err_free_work;
- if (!vpu->work)
- return -ENOMEM;
- else
- return 0;
+ vpu->path = dma_alloc_wc(scp_get_device(vpu->scp), vpu->path_size,
+ &vpu->path_addr, GFP_KERNEL);
+ if (!vpu->path)
+ goto err_free_config;
+
+ return 0;
+
+err_free_config:
+ dma_free_wc(scp_get_device(vpu->scp), vpu->config_size,
+ vpu->config, vpu->config_addr);
+err_free_work:
+ dma_free_wc(scp_get_device(vpu->scp), vpu->work_size,
+ vpu->work, vpu->work_addr);
+err_return:
+ return -ENOMEM;
}
void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu)
{
if (vpu->work && vpu->work_addr)
- dma_free_coherent(scp_get_device(vpu->scp), vpu_alloc_size,
- vpu->work, vpu->work_addr);
+ dma_free_wc(scp_get_device(vpu->scp), vpu->work_size,
+ vpu->work, vpu->work_addr);
+
+ if (vpu->config && vpu->config_addr)
+ dma_free_wc(scp_get_device(vpu->scp), vpu->config_size,
+ vpu->config, vpu->config_addr);
+
+ if (vpu->path && vpu->path_addr)
+ dma_free_wc(scp_get_device(vpu->scp), vpu->path_size,
+ vpu->path, vpu->path_addr);
}
static void mdp_vpu_ipi_handle_init_ack(void *data, unsigned int len,
@@ -156,9 +179,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
struct mdp_ipi_init_msg msg = {
.drv_data = (unsigned long)vpu,
};
- size_t mem_size;
- phys_addr_t pool;
- const size_t pool_size = sizeof(struct mdp_config_pool);
struct mdp_dev *mdp = vpu_to_mdp(vpu);
int err;
@@ -171,33 +191,20 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
goto err_work_size;
/* vpu work_size was set in mdp_vpu_ipi_handle_init_ack */
- mem_size = vpu_alloc_size;
- if (mdp_vpu_shared_mem_alloc(vpu)) {
+ vpu->config_size = MDP_DUAL_PIPE * sizeof(struct img_config);
+ vpu->path_size = MDP_VPU_PATH_SIZE;
+ err = mdp_vpu_shared_mem_alloc(vpu);
+ if (err) {
dev_err(&mdp->pdev->dev, "VPU memory alloc fail!");
goto err_mem_alloc;
}
- pool = ALIGN((uintptr_t)vpu->work + vpu->work_size, 8);
- if (pool + pool_size - (uintptr_t)vpu->work > mem_size) {
- dev_err(&mdp->pdev->dev,
- "VPU memory insufficient: %zx + %zx > %zx",
- vpu->work_size, pool_size, mem_size);
- err = -ENOMEM;
- goto err_mem_size;
- }
-
- dev_dbg(&mdp->pdev->dev,
- "VPU work:%pK pa:%pad sz:%zx pool:%pa sz:%zx (mem sz:%zx)",
- vpu->work, &vpu->work_addr, vpu->work_size,
- &pool, pool_size, mem_size);
- vpu->pool = (struct mdp_config_pool *)(uintptr_t)pool;
msg.work_addr = vpu->work_addr;
msg.work_size = vpu->work_size;
err = mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_INIT, &msg, sizeof(msg));
if (err)
goto err_work_size;
- memset(vpu->pool, 0, sizeof(*vpu->pool));
return 0;
err_work_size:
@@ -210,7 +217,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
break;
}
return err;
-err_mem_size:
err_mem_alloc:
return err;
}
@@ -233,11 +239,8 @@ static struct img_config *mdp_config_get(struct mdp_vpu_dev *vpu,
if (id < 0 || id >= MDP_CONFIG_POOL_SIZE)
return ERR_PTR(-EINVAL);
- mutex_lock(vpu->lock);
- vpu->pool->cfg_count[id]++;
- config = &vpu->pool->configs[id];
- *addr = vpu->work_addr + ((uintptr_t)config - (uintptr_t)vpu->work);
- mutex_unlock(vpu->lock);
+ config = vpu->config;
+ *addr = vpu->config_addr;
return config;
}
@@ -250,14 +253,7 @@ static int mdp_config_put(struct mdp_vpu_dev *vpu,
if (id < 0 || id >= MDP_CONFIG_POOL_SIZE)
return -EINVAL;
- if (vpu->lock)
- mutex_lock(vpu->lock);
- if (!vpu->pool->cfg_count[id] || config != &vpu->pool->configs[id])
- err = -EINVAL;
- else
- vpu->pool->cfg_count[id]--;
- if (vpu->lock)
- mutex_unlock(vpu->lock);
+
return err;
}
@@ -288,25 +284,23 @@ int mdp_vpu_ctx_deinit(struct mdp_vpu_ctx *ctx)
int mdp_vpu_process(struct mdp_vpu_ctx *ctx, struct img_ipi_frameparam *param)
{
- struct mdp_vpu_dev *vpu = ctx->vpu_dev;
- struct mdp_dev *mdp = vpu_to_mdp(vpu);
struct img_sw_addr addr;
- if (!ctx->vpu_dev->work || !ctx->vpu_dev->work_addr) {
- if (mdp_vpu_shared_mem_alloc(vpu)) {
- dev_err(&mdp->pdev->dev, "VPU memory alloc fail!");
- return -ENOMEM;
- }
- }
memset((void *)ctx->vpu_dev->work, 0, ctx->vpu_dev->work_size);
- memset(ctx->config, 0, sizeof(*ctx->config));
- param->config_data.va = (unsigned long)ctx->config;
+
+ if (param->frame_change)
+ memset((void *)ctx->vpu_dev->path, 0, ctx->vpu_dev->path_size);
+ param->self_data.pa = ctx->vpu_dev->path_addr;
+ param->self_data.va = (u64)ctx->vpu_dev->path;
+
+ memset(ctx->config, 0, ctx->vpu_dev->config_size);
+ param->config_data.va = (u64)ctx->config;
param->config_data.pa = ctx->inst_addr;
param->drv_data = (unsigned long)ctx;
memcpy((void *)ctx->vpu_dev->work, param, sizeof(*param));
addr.pa = ctx->vpu_dev->work_addr;
- addr.va = (uintptr_t)ctx->vpu_dev->work;
+ addr.va = (u64)ctx->vpu_dev->work;
return mdp_vpu_sendmsg(ctx->vpu_dev, SCP_IPI_MDP_FRAME,
&addr, sizeof(addr));
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
index 3140d2925a1a..597589c73266 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
@@ -58,6 +58,14 @@ struct mdp_vpu_dev {
size_t work_size;
struct mdp_config_pool *pool;
u32 status;
+
+ void *config;
+ dma_addr_t config_addr;
+ size_t config_size;
+
+ void *path;
+ dma_addr_t path_addr;
+ size_t path_size;
};
struct mdp_vpu_ctx {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 12/14] media: platform: mtk-mdp3: Reconfigure shared memory
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
MDP communicates with SCP through shared memory.
SCP is responsible for calculating information that MDP needed,
however SCP has poor performance.
In order to improve performance,
shared memory is reconfigured into three buffer
to make more logical sense.
The third buffer - path buffer
which allocated in scp before is used for scp calculation.
This buffer need to be clear when frame_change occurs,
but it costs lot of time for scp doing memset which decreases performance.
Thus we move this buffer to kernel,
do memset in ap side to accelerate frame processing.
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 106 +++++++++---------
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 8 ++
2 files changed, 58 insertions(+), 56 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
index 035fa3e55335..73da786b5270 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
@@ -10,7 +10,7 @@
#include "mtk-mdp3-core.h"
#define MDP_VPU_MESSAGE_TIMEOUT 500U
-#define vpu_alloc_size 0x7F8000
+#define MDP_VPU_PATH_SIZE 0x78000
static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
{
@@ -19,23 +19,46 @@ static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu)
{
- if (vpu->work && vpu->work_addr)
- return 0;
+ vpu->work = dma_alloc_wc(scp_get_device(vpu->scp), vpu->work_size,
+ &vpu->work_addr, GFP_KERNEL);
+ if (!vpu->work)
+ goto err_return;
- vpu->work = dma_alloc_coherent(scp_get_device(vpu->scp), vpu_alloc_size,
- &vpu->work_addr, GFP_KERNEL);
+ vpu->config = dma_alloc_wc(scp_get_device(vpu->scp), vpu->config_size,
+ &vpu->config_addr, GFP_KERNEL);
+ if (!vpu->config)
+ goto err_free_work;
- if (!vpu->work)
- return -ENOMEM;
- else
- return 0;
+ vpu->path = dma_alloc_wc(scp_get_device(vpu->scp), vpu->path_size,
+ &vpu->path_addr, GFP_KERNEL);
+ if (!vpu->path)
+ goto err_free_config;
+
+ return 0;
+
+err_free_config:
+ dma_free_wc(scp_get_device(vpu->scp), vpu->config_size,
+ vpu->config, vpu->config_addr);
+err_free_work:
+ dma_free_wc(scp_get_device(vpu->scp), vpu->work_size,
+ vpu->work, vpu->work_addr);
+err_return:
+ return -ENOMEM;
}
void mdp_vpu_shared_mem_free(struct mdp_vpu_dev *vpu)
{
if (vpu->work && vpu->work_addr)
- dma_free_coherent(scp_get_device(vpu->scp), vpu_alloc_size,
- vpu->work, vpu->work_addr);
+ dma_free_wc(scp_get_device(vpu->scp), vpu->work_size,
+ vpu->work, vpu->work_addr);
+
+ if (vpu->config && vpu->config_addr)
+ dma_free_wc(scp_get_device(vpu->scp), vpu->config_size,
+ vpu->config, vpu->config_addr);
+
+ if (vpu->path && vpu->path_addr)
+ dma_free_wc(scp_get_device(vpu->scp), vpu->path_size,
+ vpu->path, vpu->path_addr);
}
static void mdp_vpu_ipi_handle_init_ack(void *data, unsigned int len,
@@ -156,9 +179,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
struct mdp_ipi_init_msg msg = {
.drv_data = (unsigned long)vpu,
};
- size_t mem_size;
- phys_addr_t pool;
- const size_t pool_size = sizeof(struct mdp_config_pool);
struct mdp_dev *mdp = vpu_to_mdp(vpu);
int err;
@@ -171,33 +191,20 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
goto err_work_size;
/* vpu work_size was set in mdp_vpu_ipi_handle_init_ack */
- mem_size = vpu_alloc_size;
- if (mdp_vpu_shared_mem_alloc(vpu)) {
+ vpu->config_size = MDP_DUAL_PIPE * sizeof(struct img_config);
+ vpu->path_size = MDP_VPU_PATH_SIZE;
+ err = mdp_vpu_shared_mem_alloc(vpu);
+ if (err) {
dev_err(&mdp->pdev->dev, "VPU memory alloc fail!");
goto err_mem_alloc;
}
- pool = ALIGN((uintptr_t)vpu->work + vpu->work_size, 8);
- if (pool + pool_size - (uintptr_t)vpu->work > mem_size) {
- dev_err(&mdp->pdev->dev,
- "VPU memory insufficient: %zx + %zx > %zx",
- vpu->work_size, pool_size, mem_size);
- err = -ENOMEM;
- goto err_mem_size;
- }
-
- dev_dbg(&mdp->pdev->dev,
- "VPU work:%pK pa:%pad sz:%zx pool:%pa sz:%zx (mem sz:%zx)",
- vpu->work, &vpu->work_addr, vpu->work_size,
- &pool, pool_size, mem_size);
- vpu->pool = (struct mdp_config_pool *)(uintptr_t)pool;
msg.work_addr = vpu->work_addr;
msg.work_size = vpu->work_size;
err = mdp_vpu_sendmsg(vpu, SCP_IPI_MDP_INIT, &msg, sizeof(msg));
if (err)
goto err_work_size;
- memset(vpu->pool, 0, sizeof(*vpu->pool));
return 0;
err_work_size:
@@ -210,7 +217,6 @@ int mdp_vpu_dev_init(struct mdp_vpu_dev *vpu, struct mtk_scp *scp,
break;
}
return err;
-err_mem_size:
err_mem_alloc:
return err;
}
@@ -233,11 +239,8 @@ static struct img_config *mdp_config_get(struct mdp_vpu_dev *vpu,
if (id < 0 || id >= MDP_CONFIG_POOL_SIZE)
return ERR_PTR(-EINVAL);
- mutex_lock(vpu->lock);
- vpu->pool->cfg_count[id]++;
- config = &vpu->pool->configs[id];
- *addr = vpu->work_addr + ((uintptr_t)config - (uintptr_t)vpu->work);
- mutex_unlock(vpu->lock);
+ config = vpu->config;
+ *addr = vpu->config_addr;
return config;
}
@@ -250,14 +253,7 @@ static int mdp_config_put(struct mdp_vpu_dev *vpu,
if (id < 0 || id >= MDP_CONFIG_POOL_SIZE)
return -EINVAL;
- if (vpu->lock)
- mutex_lock(vpu->lock);
- if (!vpu->pool->cfg_count[id] || config != &vpu->pool->configs[id])
- err = -EINVAL;
- else
- vpu->pool->cfg_count[id]--;
- if (vpu->lock)
- mutex_unlock(vpu->lock);
+
return err;
}
@@ -288,25 +284,23 @@ int mdp_vpu_ctx_deinit(struct mdp_vpu_ctx *ctx)
int mdp_vpu_process(struct mdp_vpu_ctx *ctx, struct img_ipi_frameparam *param)
{
- struct mdp_vpu_dev *vpu = ctx->vpu_dev;
- struct mdp_dev *mdp = vpu_to_mdp(vpu);
struct img_sw_addr addr;
- if (!ctx->vpu_dev->work || !ctx->vpu_dev->work_addr) {
- if (mdp_vpu_shared_mem_alloc(vpu)) {
- dev_err(&mdp->pdev->dev, "VPU memory alloc fail!");
- return -ENOMEM;
- }
- }
memset((void *)ctx->vpu_dev->work, 0, ctx->vpu_dev->work_size);
- memset(ctx->config, 0, sizeof(*ctx->config));
- param->config_data.va = (unsigned long)ctx->config;
+
+ if (param->frame_change)
+ memset((void *)ctx->vpu_dev->path, 0, ctx->vpu_dev->path_size);
+ param->self_data.pa = ctx->vpu_dev->path_addr;
+ param->self_data.va = (u64)ctx->vpu_dev->path;
+
+ memset(ctx->config, 0, ctx->vpu_dev->config_size);
+ param->config_data.va = (u64)ctx->config;
param->config_data.pa = ctx->inst_addr;
param->drv_data = (unsigned long)ctx;
memcpy((void *)ctx->vpu_dev->work, param, sizeof(*param));
addr.pa = ctx->vpu_dev->work_addr;
- addr.va = (uintptr_t)ctx->vpu_dev->work;
+ addr.va = (u64)ctx->vpu_dev->work;
return mdp_vpu_sendmsg(ctx->vpu_dev, SCP_IPI_MDP_FRAME,
&addr, sizeof(addr));
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
index 3140d2925a1a..597589c73266 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
@@ -58,6 +58,14 @@ struct mdp_vpu_dev {
size_t work_size;
struct mdp_config_pool *pool;
u32 status;
+
+ void *config;
+ dma_addr_t config_addr;
+ size_t config_size;
+
+ void *path;
+ dma_addr_t path_addr;
+ size_t path_size;
};
struct mdp_vpu_ctx {
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 13/14] arm64: dts: mt8195: add mdp3 node
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mdp3 node.
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 633 +++++++++++++++++++++++
1 file changed, 633 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index ded98ff7b724..89600116ff26 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1245,9 +1245,261 @@
vppsys0: syscon@14000000 {
compatible = "mediatek,mt8195-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
+ mdp3_rdma0: mdp_rdma0@14001000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8183-mdp3-rdma0";
+ mediatek,scp = <&scp>;
+ mdp3-comps = "mediatek,mt8195-mdp3-path1", "mediatek,mt8195-mdp3-path2",
+ "mediatek,mt8195-mdp3-path3", "mediatek,mt8195-mdp3-path4",
+ "mediatek,mt8195-mdp3-path5", "mediatek,mt8195-mdp3-path6",
+ "mediatek,mt8195-mdp3-dl1", "mediatek,mt8195-mdp3-dl2";
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>,
+ <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>,
+ <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP0>,
+ <&topckgen CLK_TOP_CFG_26M_VPP0>,
+ <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>,
+ <&vppsys0 CLK_VPP0_WARP0_RELAY>,
+ <&vppsys0 CLK_VPP0_WARP0_MDP_DL_ASYNC>,
+ <&vppsys0 CLK_VPP0_WARP1_ASYNC_TX>,
+ <&vppsys0 CLK_VPP0_WARP1_RELAY>,
+ <&vppsys0 CLK_VPP0_WARP1_MDP_DL_ASYNC>,
+ <&vppsys0 CLK_VPP0_VPP02VPP1_RELAY>,
+ <&vppsys1 CLK_VPP1_DL_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL_RELAY>,
+ <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP2_VDO0_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP3_VDO1_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP2_VDO1_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP3_VDO0_DL_RELAY>;
+ clock-names = "MDP_RDMA0",
+ "TOP_CFG_VPP0",
+ "TOP_CFG_26M_VPP0",
+ "WARP0_ASYNC_TX",
+ "WARP0_RELAY",
+ "WARP0_MDP_DL_ASYNC",
+ "WARP1_ASYNC_TX",
+ "WARP1_RELAY",
+ "WARP1_MDP_DL_ASYNC",
+ "VPP02VPP1_RELAY",
+ "VPP0_DL_ASYNC_VPP1",
+ "VPP0_DL_ASYNC_VPP0",
+ "VPP0_DL_RELAY",
+ "VPP12VPP0_ASYNC",
+ "VPP0_DL1_RELAY",
+ "SVPP2_VDO0_DL_RELAY",
+ "SVPP3_VDO1_DL_RELAY",
+ "SVPP2_VDO1_DL_RELAY",
+ "SVPP3_VDO0_DL_RELAY";
+ mediatek,mmsys2 = <&vppsys1>;
+ mediatek,mm-mutex2 = <&vpp1_mutex>;
+ mediatek,mmsys = <&vppsys0>;
+ mediatek,mm-mutex = <&vpp0_mutex>;
+ mboxes =
+ <&gce1 12 CMDQ_THR_PRIO_1>,
+ <&gce1 13 CMDQ_THR_PRIO_1>,
+ <&gce1 14 CMDQ_THR_PRIO_1>,
+ <&gce1 21 CMDQ_THR_PRIO_1>,
+ <&gce1 22 CMDQ_THR_PRIO_1>;
+ mdp3-rdma0 = <&mdp3_rdma0>;
+ mdp3-rdma1 = <&svpp1_mdp3_rdma>;
+ mdp3-rdma2 = <&svpp2_mdp3_rdma>;
+ mdp3-rdma3 = <&svpp3_mdp3_rdma>;
+ mdp3-stitch = <&mdp3_stitch0>;
+ mdp3-rsz0 = <&mdp3_rsz0>;
+ mdp3-rsz1 = <&svpp1_mdp3_rsz>;
+ mdp3-rsz2 = <&svpp2_mdp3_rsz>;
+ mdp3-rsz3 = <&svpp3_mdp3_rsz>;
+ mdp3-wrot0 = <&mdp3_wrot0>;
+ mdp3-wrot1 = <&svpp1_mdp3_wrot>;
+ mdp3-wrot2 = <&svpp2_mdp3_wrot>;
+ mdp3-wrot3 = <&svpp3_mdp3_wrot>;
+ mdp3-tdshp0 = <&mdp3_tdshp0>;
+ mdp3-tdshp1 = <&svpp1_mdp3_tdshp>;
+ mdp3-tdshp2 = <&svpp2_mdp3_tdshp>;
+ mdp3-tdshp3 = <&svpp3_mdp3_tdshp>;
+ mdp3-aal0 = <&mdp3_aal0>;
+ mdp3-aal1 = <&svpp1_mdp3_aal>;
+ mdp3-aal2 = <&svpp2_mdp3_aal>;
+ mdp3-aal3 = <&svpp3_mdp3_aal>;
+ mdp3-color0 = <&mdp3_color0>;
+ mdp3-color1 = <&svpp1_mdp3_color>;
+ mdp3-color2 = <&svpp2_mdp3_color>;
+ mdp3-color3 = <&svpp3_mdp3_color>;
+ mdp3-hdr0 = <&mdp3_hdr0>;
+ mdp3-hdr1 = <&svpp1_mdp3_hdr>;
+ mdp3-hdr2 = <&svpp2_mdp3_hdr>;
+ mdp3-hdr3 = <&svpp3_mdp3_hdr>;
+ mdp3-fg0 = <&mdp3_fg0>;
+ mdp3-fg1 = <&svpp1_mdp3_fg>;
+ mdp3-fg2 = <&svpp2_mdp3_fg>;
+ mdp3-fg3 = <&svpp3_mdp3_fg>;
+ mdp3-tcc0 = <&mdp3_tcc0>;
+ mdp3-tcc1 = <&svpp1_mdp3_tcc>;
+ mdp3-ovl0 = <&mdp3_ovl0>;
+ mdp3-ovl1 = <&svpp1_mdp3_ovl>;
+ mdp3-pad0 = <&mdp3_pad0>;
+ mdp3-pad1 = <&svpp1_mdp3_pad>;
+ mdp3-pad2 = <&svpp2_mdp3_pad>;
+ mdp3-pad3 = <&svpp3_mdp3_pad>;
+ mdp3-split = <&vpp_split0>;
+ mdp3-merge2 = <&svpp2_mdp3_merge>;
+ mdp3-merge3 = <&svpp3_mdp3_merge>;
+ };
+
+ mdp3_fg0: mdp_fg0@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg0";
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ clock-names = "MDP_FG0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_stitch0: mdp_stich0@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ clock-names = "MDP_STITCH";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_hdr0: mdp_hdr0@14004000 {
+ compatible = "mediatek,mt8195-mdp3-hdr0";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ clock-names = "MDP_HDR0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_aal0: mdp_aal0@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal0";
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ clock-names = "MDP_AAL0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_rsz0: mdp_rsz0@14006000 {
+ compatible = "mediatek,mt8183-mdp3-rsz0";
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+ clock-names = "MDP_RSZ0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_tdshp0: mdp_tdshp0@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp0";
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_color0: mdp_color0@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color0";
+ reg = <0 0x14008000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ clock-names = "MDP_COLOR0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_ovl0: mdp_ovl0@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl0";
+ reg = <0 0x14009000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ clock-names = "MDP_OVL0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_pad0: mdp_pad0@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad0";
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ clock-names = "MDP_PAD0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_tcc0: mdp_tcc0@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc0";
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ clock-names = "MDP_TCC0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_wrot0: mdp_wrot0@1400c000 {
+ compatible = "mediatek,mt8183-mdp3-wrot0";
+ reg = <0 0x1400c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+ clock-names = "MDP_WROT0";
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ vpp0_mutex: vpp0_mutex@1400f000 {
+ compatible = "mediatek,mt8195-vpp0-mutex";
+ reg = <0 0x1400f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
+ #clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+ #clock-names = "MDP_MUTEX0";
+ clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+ clock-names = "MDP_MUTEX0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -1269,9 +1521,390 @@
vppsys1: syscon@14f00000 {
compatible = "mediatek,mt8195-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
#clock-cells = <1>;
};
+ vpp1_mutex: vpp1_mutex@14f01000 {
+ compatible = "mediatek,mt8195-vpp1-mutex";
+ reg = <0 0x14f01000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+ #clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+ #clock-names = "DISP_MUTEX";
+ clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+ clock-names = "DISP_MUTEX";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ vpp_split0: vpp_split0@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
+ <&vppsys1 CLK_VPP1_DGI_IN>,
+ <&vppsys1 CLK_VPP1_DGI_OUT>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>;
+ clock-names = "MDP_SPLIT",
+ "HDMI_META",
+ "SPLIT_HDMI",
+ "DGI_IN",
+ "DGI_OUT",
+ "SPLIT_DGI",
+ "VPP_SPLIT_26M";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_tcc: svpp1_mdp_tcc@14f07000 {
+ compatible = "mediatek,mt8195-mdp3-tcc1";
+ reg = <0 0x14f07000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
+ clock-names = "MDP_TCC1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_rdma: svpp1_mdp_rdma@14f08000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8195-mdp3-rdma1";
+ reg = <0 0x14f08000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA1",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>,
+ <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_rdma: svpp2_mdp_rdma@14f09000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8195-mdp3-rdma2";
+ reg = <0 0x14f09000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA2",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>,
+ <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_rdma: svpp3_mdp_rdma@14f0a000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8195-mdp3-rdma3";
+ reg = <0 0x14f0a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA3",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>,
+ <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_fg: svpp1_mdp_fg@14f0b000 {
+ compatible = "mediatek,mt8195-mdp3-fg1";
+ reg = <0 0x14f0b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
+ clock-names = "MDP_FG1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_fg: svpp2_mdp_fg@14f0c000 {
+ compatible = "mediatek,mt8195-mdp3-fg2";
+ reg = <0 0x14f0c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+ clock-names = "MDP_FG2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_fg: svpp3_mdp_fg@14f0d000 {
+ compatible = "mediatek,mt8195-mdp3-fg3";
+ reg = <0 0x14f0d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+ clock-names = "MDP_FG3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_hdr: svpp1_mdp_hdr@14f0e000 {
+ compatible = "mediatek,mt8195-mdp3-hdr1";
+ reg = <0 0x14f0e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
+ clock-names = "MDP_HDR1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_hdr: svpp2_mdp_hdr@14f0f000 {
+ compatible = "mediatek,mt8195-mdp3-hdr2";
+ reg = <0 0x14f0f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+ clock-names = "MDP_HDR2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_hdr: svpp3_mdp_hdr@14f10000 {
+ compatible = "mediatek,mt8195-mdp3-hdr3";
+ reg = <0 0x14f10000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
+ interrupts = <GIC_SPI 616 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+ clock-names = "MDP_HDR3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_aal: svpp1_mdp_aal@14f11000 {
+ compatible = "mediatek,mt8195-mdp3-aal1";
+ reg = <0 0x14f11000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
+ clock-names = "MDP_AAL1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_aal: svpp2_mdp_aal@14f12000 {
+ compatible = "mediatek,mt8195-mdp3-aal2";
+ reg = <0 0x14f12000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+ clock-names = "MDP_AAL2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_aal: svpp3_mdp_aal@14f13000 {
+ compatible = "mediatek,mt8195-mdp3-aal3";
+ reg = <0 0x14f13000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+ clock-names = "MDP_AAL3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_rsz: svpp1_mdp_rsz@14f14000 {
+ compatible = "mediatek,mt8183-mdp3-rsz1";
+ reg = <0 0x14f14000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
+ clock-names = "MDP_RSZ1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_rsz: svpp2_mdp_rsz@14f15000 {
+ compatible = "mediatek,mt8195-mdp3-rsz2";
+ reg = <0 0x14f15000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>,
+ <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ clock-names = "MDP_RSZ2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_rsz: svpp3_mdp_rsz@14f16000 {
+ compatible = "mediatek,mt8195-mdp3-rsz3";
+ reg = <0 0x14f16000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>,
+ <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ clock-names = "MDP_RSZ3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_tdshp: svpp1_mdp_tdshp@14f17000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp1";
+ reg = <0 0x14f17000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_tdshp: svpp2_mdp_tdshp@14f18000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp2";
+ reg = <0 0x14f18000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_tdshp: svpp3_mdp_tdshp@14f19000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp3";
+ reg = <0 0x14f19000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge2";
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ clock-names = "MDP_MERGE2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_merge: svpp3_mdp_merge@14f1b000 {
+ compatible = "mediatek,mt8195-mdp3-merge3";
+ reg = <0 0x14f1b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ clock-names = "MDP_MERGE3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_color: svpp1_mdp_color@14f1c000 {
+ compatible = "mediatek,mt8195-mdp3-color1";
+ reg = <0 0x14f1c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
+ clock-names = "MDP_COLOR1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_color: svpp2_mdp_color@14f1d000 {
+ compatible = "mediatek,mt8195-mdp3-color2";
+ reg = <0 0x14f1d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+ clock-names = "MDP_COLOR2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_color: svpp3_mdp_color@14f1e000 {
+ compatible = "mediatek,mt8195-mdp3-color3";
+ reg = <0 0x14f1e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
+ interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+ clock-names = "MDP_COLOR3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_ovl: svpp1_mdp_ovl@14f1f000 {
+ compatible = "mediatek,mt8195-mdp3-ovl1";
+ reg = <0 0x14f1f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
+ clock-names = "MDP_OVL1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_pad: svpp1_mdp_pad@14f20000 {
+ compatible = "mediatek,mt8195-mdp3-pad1";
+ reg = <0 0x14f20000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
+ interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
+ clock-names = "MDP_PAD1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_pad: svpp2_mdp_pad@14f21000 {
+ compatible = "mediatek,mt8195-mdp3-pad2";
+ reg = <0 0x14f21000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+ clock-names = "MDP_PAD2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_pad: svpp3_mdp_pad@14f22000 {
+ compatible = "mediatek,mt8195-mdp3-pad3";
+ reg = <0 0x14f22000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+ clock-names = "MDP_PAD3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_wrot: svpp1_mdp_wrot@14f23000 {
+ compatible = "mediatek,mt8195-mdp3-wrot1";
+ reg = <0 0x14f23000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
+ clock-names = "MDP_WROT1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_wrot: svpp2_mdp_wrot@14f24000 {
+ compatible = "mediatek,mt8195-mdp3-wrot2";
+ reg = <0 0x14f24000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+ clock-names = "MDP_WROT2";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_wrot: svpp3_mdp_wrot@14f25000 {
+ compatible = "mediatek,mt8195-mdp3-wrot3";
+ reg = <0 0x14f25000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+ clock-names = "MDP_WROT3";
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 13/14] arm64: dts: mt8195: add mdp3 node
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mdp3 node.
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 633 +++++++++++++++++++++++
1 file changed, 633 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index ded98ff7b724..89600116ff26 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1245,9 +1245,261 @@
vppsys0: syscon@14000000 {
compatible = "mediatek,mt8195-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
+ mdp3_rdma0: mdp_rdma0@14001000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8183-mdp3-rdma0";
+ mediatek,scp = <&scp>;
+ mdp3-comps = "mediatek,mt8195-mdp3-path1", "mediatek,mt8195-mdp3-path2",
+ "mediatek,mt8195-mdp3-path3", "mediatek,mt8195-mdp3-path4",
+ "mediatek,mt8195-mdp3-path5", "mediatek,mt8195-mdp3-path6",
+ "mediatek,mt8195-mdp3-dl1", "mediatek,mt8195-mdp3-dl2";
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>,
+ <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>,
+ <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP0>,
+ <&topckgen CLK_TOP_CFG_26M_VPP0>,
+ <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>,
+ <&vppsys0 CLK_VPP0_WARP0_RELAY>,
+ <&vppsys0 CLK_VPP0_WARP0_MDP_DL_ASYNC>,
+ <&vppsys0 CLK_VPP0_WARP1_ASYNC_TX>,
+ <&vppsys0 CLK_VPP0_WARP1_RELAY>,
+ <&vppsys0 CLK_VPP0_WARP1_MDP_DL_ASYNC>,
+ <&vppsys0 CLK_VPP0_VPP02VPP1_RELAY>,
+ <&vppsys1 CLK_VPP1_DL_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL_RELAY>,
+ <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP2_VDO0_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP3_VDO1_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP2_VDO1_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP3_VDO0_DL_RELAY>;
+ clock-names = "MDP_RDMA0",
+ "TOP_CFG_VPP0",
+ "TOP_CFG_26M_VPP0",
+ "WARP0_ASYNC_TX",
+ "WARP0_RELAY",
+ "WARP0_MDP_DL_ASYNC",
+ "WARP1_ASYNC_TX",
+ "WARP1_RELAY",
+ "WARP1_MDP_DL_ASYNC",
+ "VPP02VPP1_RELAY",
+ "VPP0_DL_ASYNC_VPP1",
+ "VPP0_DL_ASYNC_VPP0",
+ "VPP0_DL_RELAY",
+ "VPP12VPP0_ASYNC",
+ "VPP0_DL1_RELAY",
+ "SVPP2_VDO0_DL_RELAY",
+ "SVPP3_VDO1_DL_RELAY",
+ "SVPP2_VDO1_DL_RELAY",
+ "SVPP3_VDO0_DL_RELAY";
+ mediatek,mmsys2 = <&vppsys1>;
+ mediatek,mm-mutex2 = <&vpp1_mutex>;
+ mediatek,mmsys = <&vppsys0>;
+ mediatek,mm-mutex = <&vpp0_mutex>;
+ mboxes =
+ <&gce1 12 CMDQ_THR_PRIO_1>,
+ <&gce1 13 CMDQ_THR_PRIO_1>,
+ <&gce1 14 CMDQ_THR_PRIO_1>,
+ <&gce1 21 CMDQ_THR_PRIO_1>,
+ <&gce1 22 CMDQ_THR_PRIO_1>;
+ mdp3-rdma0 = <&mdp3_rdma0>;
+ mdp3-rdma1 = <&svpp1_mdp3_rdma>;
+ mdp3-rdma2 = <&svpp2_mdp3_rdma>;
+ mdp3-rdma3 = <&svpp3_mdp3_rdma>;
+ mdp3-stitch = <&mdp3_stitch0>;
+ mdp3-rsz0 = <&mdp3_rsz0>;
+ mdp3-rsz1 = <&svpp1_mdp3_rsz>;
+ mdp3-rsz2 = <&svpp2_mdp3_rsz>;
+ mdp3-rsz3 = <&svpp3_mdp3_rsz>;
+ mdp3-wrot0 = <&mdp3_wrot0>;
+ mdp3-wrot1 = <&svpp1_mdp3_wrot>;
+ mdp3-wrot2 = <&svpp2_mdp3_wrot>;
+ mdp3-wrot3 = <&svpp3_mdp3_wrot>;
+ mdp3-tdshp0 = <&mdp3_tdshp0>;
+ mdp3-tdshp1 = <&svpp1_mdp3_tdshp>;
+ mdp3-tdshp2 = <&svpp2_mdp3_tdshp>;
+ mdp3-tdshp3 = <&svpp3_mdp3_tdshp>;
+ mdp3-aal0 = <&mdp3_aal0>;
+ mdp3-aal1 = <&svpp1_mdp3_aal>;
+ mdp3-aal2 = <&svpp2_mdp3_aal>;
+ mdp3-aal3 = <&svpp3_mdp3_aal>;
+ mdp3-color0 = <&mdp3_color0>;
+ mdp3-color1 = <&svpp1_mdp3_color>;
+ mdp3-color2 = <&svpp2_mdp3_color>;
+ mdp3-color3 = <&svpp3_mdp3_color>;
+ mdp3-hdr0 = <&mdp3_hdr0>;
+ mdp3-hdr1 = <&svpp1_mdp3_hdr>;
+ mdp3-hdr2 = <&svpp2_mdp3_hdr>;
+ mdp3-hdr3 = <&svpp3_mdp3_hdr>;
+ mdp3-fg0 = <&mdp3_fg0>;
+ mdp3-fg1 = <&svpp1_mdp3_fg>;
+ mdp3-fg2 = <&svpp2_mdp3_fg>;
+ mdp3-fg3 = <&svpp3_mdp3_fg>;
+ mdp3-tcc0 = <&mdp3_tcc0>;
+ mdp3-tcc1 = <&svpp1_mdp3_tcc>;
+ mdp3-ovl0 = <&mdp3_ovl0>;
+ mdp3-ovl1 = <&svpp1_mdp3_ovl>;
+ mdp3-pad0 = <&mdp3_pad0>;
+ mdp3-pad1 = <&svpp1_mdp3_pad>;
+ mdp3-pad2 = <&svpp2_mdp3_pad>;
+ mdp3-pad3 = <&svpp3_mdp3_pad>;
+ mdp3-split = <&vpp_split0>;
+ mdp3-merge2 = <&svpp2_mdp3_merge>;
+ mdp3-merge3 = <&svpp3_mdp3_merge>;
+ };
+
+ mdp3_fg0: mdp_fg0@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg0";
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ clock-names = "MDP_FG0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_stitch0: mdp_stich0@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ clock-names = "MDP_STITCH";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_hdr0: mdp_hdr0@14004000 {
+ compatible = "mediatek,mt8195-mdp3-hdr0";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ clock-names = "MDP_HDR0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_aal0: mdp_aal0@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal0";
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ clock-names = "MDP_AAL0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_rsz0: mdp_rsz0@14006000 {
+ compatible = "mediatek,mt8183-mdp3-rsz0";
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+ clock-names = "MDP_RSZ0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_tdshp0: mdp_tdshp0@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp0";
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_color0: mdp_color0@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color0";
+ reg = <0 0x14008000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ clock-names = "MDP_COLOR0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_ovl0: mdp_ovl0@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl0";
+ reg = <0 0x14009000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ clock-names = "MDP_OVL0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_pad0: mdp_pad0@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad0";
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ clock-names = "MDP_PAD0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_tcc0: mdp_tcc0@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc0";
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ clock-names = "MDP_TCC0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_wrot0: mdp_wrot0@1400c000 {
+ compatible = "mediatek,mt8183-mdp3-wrot0";
+ reg = <0 0x1400c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+ clock-names = "MDP_WROT0";
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ vpp0_mutex: vpp0_mutex@1400f000 {
+ compatible = "mediatek,mt8195-vpp0-mutex";
+ reg = <0 0x1400f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
+ #clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+ #clock-names = "MDP_MUTEX0";
+ clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+ clock-names = "MDP_MUTEX0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -1269,9 +1521,390 @@
vppsys1: syscon@14f00000 {
compatible = "mediatek,mt8195-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
#clock-cells = <1>;
};
+ vpp1_mutex: vpp1_mutex@14f01000 {
+ compatible = "mediatek,mt8195-vpp1-mutex";
+ reg = <0 0x14f01000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+ #clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+ #clock-names = "DISP_MUTEX";
+ clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+ clock-names = "DISP_MUTEX";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ vpp_split0: vpp_split0@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
+ <&vppsys1 CLK_VPP1_DGI_IN>,
+ <&vppsys1 CLK_VPP1_DGI_OUT>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>;
+ clock-names = "MDP_SPLIT",
+ "HDMI_META",
+ "SPLIT_HDMI",
+ "DGI_IN",
+ "DGI_OUT",
+ "SPLIT_DGI",
+ "VPP_SPLIT_26M";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_tcc: svpp1_mdp_tcc@14f07000 {
+ compatible = "mediatek,mt8195-mdp3-tcc1";
+ reg = <0 0x14f07000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
+ clock-names = "MDP_TCC1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_rdma: svpp1_mdp_rdma@14f08000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8195-mdp3-rdma1";
+ reg = <0 0x14f08000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA1",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>,
+ <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_rdma: svpp2_mdp_rdma@14f09000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8195-mdp3-rdma2";
+ reg = <0 0x14f09000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA2",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>,
+ <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_rdma: svpp3_mdp_rdma@14f0a000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8195-mdp3-rdma3";
+ reg = <0 0x14f0a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA3",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>,
+ <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; /* 8G - 12G IOVA*/
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_fg: svpp1_mdp_fg@14f0b000 {
+ compatible = "mediatek,mt8195-mdp3-fg1";
+ reg = <0 0x14f0b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
+ clock-names = "MDP_FG1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_fg: svpp2_mdp_fg@14f0c000 {
+ compatible = "mediatek,mt8195-mdp3-fg2";
+ reg = <0 0x14f0c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+ clock-names = "MDP_FG2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_fg: svpp3_mdp_fg@14f0d000 {
+ compatible = "mediatek,mt8195-mdp3-fg3";
+ reg = <0 0x14f0d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+ clock-names = "MDP_FG3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_hdr: svpp1_mdp_hdr@14f0e000 {
+ compatible = "mediatek,mt8195-mdp3-hdr1";
+ reg = <0 0x14f0e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
+ clock-names = "MDP_HDR1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_hdr: svpp2_mdp_hdr@14f0f000 {
+ compatible = "mediatek,mt8195-mdp3-hdr2";
+ reg = <0 0x14f0f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+ clock-names = "MDP_HDR2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_hdr: svpp3_mdp_hdr@14f10000 {
+ compatible = "mediatek,mt8195-mdp3-hdr3";
+ reg = <0 0x14f10000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
+ interrupts = <GIC_SPI 616 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+ clock-names = "MDP_HDR3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_aal: svpp1_mdp_aal@14f11000 {
+ compatible = "mediatek,mt8195-mdp3-aal1";
+ reg = <0 0x14f11000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
+ clock-names = "MDP_AAL1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_aal: svpp2_mdp_aal@14f12000 {
+ compatible = "mediatek,mt8195-mdp3-aal2";
+ reg = <0 0x14f12000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+ clock-names = "MDP_AAL2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_aal: svpp3_mdp_aal@14f13000 {
+ compatible = "mediatek,mt8195-mdp3-aal3";
+ reg = <0 0x14f13000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+ clock-names = "MDP_AAL3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_rsz: svpp1_mdp_rsz@14f14000 {
+ compatible = "mediatek,mt8183-mdp3-rsz1";
+ reg = <0 0x14f14000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
+ clock-names = "MDP_RSZ1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_rsz: svpp2_mdp_rsz@14f15000 {
+ compatible = "mediatek,mt8195-mdp3-rsz2";
+ reg = <0 0x14f15000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>,
+ <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ clock-names = "MDP_RSZ2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_rsz: svpp3_mdp_rsz@14f16000 {
+ compatible = "mediatek,mt8195-mdp3-rsz3";
+ reg = <0 0x14f16000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>,
+ <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ clock-names = "MDP_RSZ3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_tdshp: svpp1_mdp_tdshp@14f17000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp1";
+ reg = <0 0x14f17000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_tdshp: svpp2_mdp_tdshp@14f18000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp2";
+ reg = <0 0x14f18000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_tdshp: svpp3_mdp_tdshp@14f19000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp3";
+ reg = <0 0x14f19000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge2";
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ clock-names = "MDP_MERGE2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_merge: svpp3_mdp_merge@14f1b000 {
+ compatible = "mediatek,mt8195-mdp3-merge3";
+ reg = <0 0x14f1b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ clock-names = "MDP_MERGE3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_color: svpp1_mdp_color@14f1c000 {
+ compatible = "mediatek,mt8195-mdp3-color1";
+ reg = <0 0x14f1c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
+ clock-names = "MDP_COLOR1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_color: svpp2_mdp_color@14f1d000 {
+ compatible = "mediatek,mt8195-mdp3-color2";
+ reg = <0 0x14f1d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+ clock-names = "MDP_COLOR2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_color: svpp3_mdp_color@14f1e000 {
+ compatible = "mediatek,mt8195-mdp3-color3";
+ reg = <0 0x14f1e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
+ interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+ clock-names = "MDP_COLOR3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_ovl: svpp1_mdp_ovl@14f1f000 {
+ compatible = "mediatek,mt8195-mdp3-ovl1";
+ reg = <0 0x14f1f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
+ clock-names = "MDP_OVL1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_pad: svpp1_mdp_pad@14f20000 {
+ compatible = "mediatek,mt8195-mdp3-pad1";
+ reg = <0 0x14f20000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
+ interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
+ clock-names = "MDP_PAD1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_pad: svpp2_mdp_pad@14f21000 {
+ compatible = "mediatek,mt8195-mdp3-pad2";
+ reg = <0 0x14f21000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+ clock-names = "MDP_PAD2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_pad: svpp3_mdp_pad@14f22000 {
+ compatible = "mediatek,mt8195-mdp3-pad3";
+ reg = <0 0x14f22000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+ clock-names = "MDP_PAD3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_wrot: svpp1_mdp_wrot@14f23000 {
+ compatible = "mediatek,mt8195-mdp3-wrot1";
+ reg = <0 0x14f23000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
+ clock-names = "MDP_WROT1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_wrot: svpp2_mdp_wrot@14f24000 {
+ compatible = "mediatek,mt8195-mdp3-wrot2";
+ reg = <0 0x14f24000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+ clock-names = "MDP_WROT2";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_wrot: svpp3_mdp_wrot@14f25000 {
+ compatible = "mediatek,mt8195-mdp3-wrot3";
+ reg = <0 0x14f25000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+ clock-names = "MDP_WROT3";
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 14/14] dt-bindings: media: mediatek: mdp3: add yaml for new modules added in mt8195
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-17 5:52 ` roy-cw.yeh
-1 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add yaml for new modules added in mt8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
This patch is base on [1]
[1] dt-bindings: arm: mediatek: move out common module from display folder
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220107101425.6917-8-jason-jh.lin@mediatek.com/
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
.../bindings/media/mediatek,mdp3-aal.yaml | 56 +++++++++++++++++
.../bindings/media/mediatek,mdp3-color.yaml | 56 +++++++++++++++++
.../bindings/media/mediatek,mdp3-fg.yaml | 55 +++++++++++++++++
.../bindings/media/mediatek,mdp3-hdr.yaml | 55 +++++++++++++++++
.../bindings/media/mediatek,mdp3-merge.yaml | 54 ++++++++++++++++
.../bindings/media/mediatek,mdp3-ovl.yaml | 53 ++++++++++++++++
.../bindings/media/mediatek,mdp3-pad.yaml | 56 +++++++++++++++++
.../bindings/media/mediatek,mdp3-rdma.yaml | 28 +++++++++
.../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
.../bindings/media/mediatek,mdp3-split.yaml | 58 ++++++++++++++++++
.../bindings/media/mediatek,mdp3-stitch.yaml | 53 ++++++++++++++++
.../bindings/media/mediatek,mdp3-tcc.yaml | 54 ++++++++++++++++
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 3 +
.../bindings/soc/mediatek/mediatek,mutex.yaml | 6 ++
16 files changed, 652 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 763c62323a74..9e59c8b738bb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,8 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8192-mmsys
- mediatek,mt8365-mmsys
+ - mediatek,mt8195-vppsys0
+ - mediatek,mt8195-vppsys1
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
new file mode 100644
index 000000000000..ba4590031f34
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 AAL Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components is responsible for backlight power saving
+ and sunlight visibility improving.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-aal0
+ - mediatek,mt8195-mdp3-aal1
+ - mediatek,mt8195-mdp3-aal2
+ - mediatek,mt8195-mdp3-aal3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_aal0: mdp_aal0@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal0";
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
new file mode 100644
index 000000000000..5c0d8e686909
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 COLOR Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to adjust hue, luma and saturation
+ to get better picture quality.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-color0
+ - mediatek,mt8195-mdp3-color1
+ - mediatek,mt8195-mdp3-color2
+ - mediatek,mt8195-mdp3-color3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_color0: mdp_color0@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color0";
+ reg = <0 0x14008000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x8000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
new file mode 100644
index 000000000000..d9cb1cb966e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 FG Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to add film grain according to AV1 spec.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-fg0
+ - mediatek,mt8195-mdp3-fg1
+ - mediatek,mt8195-mdp3-fg2
+ - mediatek,mt8195-mdp3-fg3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_fg0: mdp_fg0@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg0";
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
new file mode 100644
index 000000000000..fbb2af5f5b25
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 HDR Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform HDR to SDR
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-hdr0
+ - mediatek,mt8195-mdp3-hdr1
+ - mediatek,mt8195-mdp3-hdr2
+ - mediatek,mt8195-mdp3-hdr3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_hdr0: mdp_hdr0@14004000
+ compatible = "mediatek,mt8195-mdp3-hdr0";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
new file mode 100644
index 000000000000..4e37cb0abe46
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 MERGE Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to merge
+ two slice-per-line inputs into one side-by-side output.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-merge2
+ - mediatek,mt8195-mdp3-merge3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge2";
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
new file mode 100644
index 000000000000..6be6da6b159b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 OVL Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform alpha blending from the memory.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-ovl0
+ - mediatek,mt8195-mdp3-ovl1
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_ovl0: mdp_ovl0@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl0";
+ reg = <0 0x14009000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x9000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
new file mode 100644
index 000000000000..883963a4861f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-pad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 PADDING Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to insert
+ pre-defined color or alpha value to arbitrary side of image.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-pad0
+ - mediatek,mt8195-mdp3-pad1
+ - mediatek,mt8195-mdp3-pad2
+ - mediatek,mt8195-mdp3-pad3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_pad0: mdp_pad0@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad0";
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xa000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
index 002503383934..3b0779e8bfc2 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -26,6 +26,18 @@ properties:
# MDP3 controller node
- const: mediatek,mt8183-mdp3
- const: mediatek,mt8183-mdp3-rdma0
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8183-mdp3-rdma0
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8195-mdp3-rdma1
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8195-mdp3-rdma2
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8195-mdp3-rdma3
- items:
# normal RDMA conponent
- const: mediatek,mt8183-mdp3-rdma0
@@ -46,12 +58,28 @@ properties:
- mediatek,mt8183-mdp3-dl1
- enum:
- mediatek,mt8183-mdp3-dl2
+ - enum:
+ - mediatek,mt8195-mdp3-dl1
+ - enum:
+ - mediatek,mt8195-mdp3-dl2
- enum:
# MDP direct-link output path selection, create a
# component for path connectedness of HW pipe control
- mediatek,mt8183-mdp3-path1
- enum:
- mediatek,mt8183-mdp3-path2
+ - enum:
+ - mediatek,mt8195-mdp3-path1
+ - enum:
+ - mediatek,mt8195-mdp3-path2
+ - enum:
+ - mediatek,mt8195-mdp3-path3
+ - enum:
+ - mediatek,mt8195-mdp3-path4
+ - enum:
+ - mediatek,mt8195-mdp3-path5
+ - enum:
+ - mediatek,mt8195-mdp3-path6
- enum:
# Input DMA of ISP PASS2 (DIP) module for raw image input
- mediatek,mt8183-mdp3-imgi
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
index cd4cf1531535..714038c9bab9 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -18,6 +18,8 @@ properties:
- enum:
- mediatek,mt8183-mdp3-rsz0
- mediatek,mt8183-mdp3-rsz1
+ - mediatek,mt8195-mdp3-rsz2
+ - mediatek,mt8195-mdp3-rsz3
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
new file mode 100644
index 000000000000..f3eb9cc92fd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-solit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 SPLIT Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to split hdmi rx into two stream
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-split
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ vpp_split0: vpp_split0@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
+ <&vppsys1 CLK_VPP1_DGI_IN>,
+ <&vppsys1 CLK_VPP1_DGI_OUT>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
new file mode 100644
index 000000000000..31cf3592c16f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 STITCH Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to combine multiple video frame
+ with overlapping fields of view to produce a segmented panorame.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-stitch
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_stitch0: mdp_stich0@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
new file mode 100644
index 000000000000..b5d6b0214fe0
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TCC Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to support
+ HDR gamma curve conversion HDR displays.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-tcc0
+ - mediatek,mt8195-mdp3-tcc1
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tcc0: mdp_tcc0@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc0";
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
new file mode 100644
index 000000000000..d967abd5fb7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TDSHP Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to improve image sharpness and contrast.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-tdshp0
+ - mediatek,mt8195-mdp3-tdshp1
+ - mediatek,mt8195-mdp3-tdshp2
+ - mediatek,mt8195-mdp3-tdshp3
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tdshp0: mdp_tdshp0@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp0";
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
index 7b0f9c4fffd7..d2e015bc09a2 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -17,6 +17,9 @@ properties:
items:
- enum:
- mediatek,mt8183-mdp3-wrot0
+ - mediatek,mt8195-mdp3-wrot1
+ - mediatek,mt8195-mdp3-wrot2
+ - mediatek,mt8195-mdp3-wrot3
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index a7ba7ebb9c53..26d69e0320ab 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -31,6 +31,12 @@ properties:
- const: mediatek,mt8183-disp-mutex
- items:
- const: mediatek,mt8192-disp-mutex
+ - items:
+ - const: mediatek,mt8192-disp-mutex
+ - items:
+ - const: mediatek,mt8195-vpp0-mutex
+ - items:
+ - const: mediatek,mt8195-vpp1-mutex
reg:
maxItems: 1
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v1 14/14] dt-bindings: media: mediatek: mdp3: add yaml for new modules added in mt8195
@ 2022-01-17 5:52 ` roy-cw.yeh
0 siblings, 0 replies; 39+ messages in thread
From: roy-cw.yeh @ 2022-01-17 5:52 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
river . cheng, Enric Balletbo i Serra, Yongqiang Niu, devicetree,
linux-kernel, linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add yaml for new modules added in mt8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
This patch is base on [1]
[1] dt-bindings: arm: mediatek: move out common module from display folder
- https://patchwork.kernel.org/project/linux-mediatek/patch/20220107101425.6917-8-jason-jh.lin@mediatek.com/
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
.../bindings/media/mediatek,mdp3-aal.yaml | 56 +++++++++++++++++
.../bindings/media/mediatek,mdp3-color.yaml | 56 +++++++++++++++++
.../bindings/media/mediatek,mdp3-fg.yaml | 55 +++++++++++++++++
.../bindings/media/mediatek,mdp3-hdr.yaml | 55 +++++++++++++++++
.../bindings/media/mediatek,mdp3-merge.yaml | 54 ++++++++++++++++
.../bindings/media/mediatek,mdp3-ovl.yaml | 53 ++++++++++++++++
.../bindings/media/mediatek,mdp3-pad.yaml | 56 +++++++++++++++++
.../bindings/media/mediatek,mdp3-rdma.yaml | 28 +++++++++
.../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
.../bindings/media/mediatek,mdp3-split.yaml | 58 ++++++++++++++++++
.../bindings/media/mediatek,mdp3-stitch.yaml | 53 ++++++++++++++++
.../bindings/media/mediatek,mdp3-tcc.yaml | 54 ++++++++++++++++
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 3 +
.../bindings/soc/mediatek/mediatek,mutex.yaml | 6 ++
16 files changed, 652 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 763c62323a74..9e59c8b738bb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,8 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8192-mmsys
- mediatek,mt8365-mmsys
+ - mediatek,mt8195-vppsys0
+ - mediatek,mt8195-vppsys1
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
new file mode 100644
index 000000000000..ba4590031f34
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 AAL Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components is responsible for backlight power saving
+ and sunlight visibility improving.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-aal0
+ - mediatek,mt8195-mdp3-aal1
+ - mediatek,mt8195-mdp3-aal2
+ - mediatek,mt8195-mdp3-aal3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_aal0: mdp_aal0@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal0";
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
new file mode 100644
index 000000000000..5c0d8e686909
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 COLOR Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to adjust hue, luma and saturation
+ to get better picture quality.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-color0
+ - mediatek,mt8195-mdp3-color1
+ - mediatek,mt8195-mdp3-color2
+ - mediatek,mt8195-mdp3-color3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_color0: mdp_color0@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color0";
+ reg = <0 0x14008000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x8000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
new file mode 100644
index 000000000000..d9cb1cb966e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 FG Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to add film grain according to AV1 spec.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-fg0
+ - mediatek,mt8195-mdp3-fg1
+ - mediatek,mt8195-mdp3-fg2
+ - mediatek,mt8195-mdp3-fg3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_fg0: mdp_fg0@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg0";
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
new file mode 100644
index 000000000000..fbb2af5f5b25
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 HDR Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform HDR to SDR
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-hdr0
+ - mediatek,mt8195-mdp3-hdr1
+ - mediatek,mt8195-mdp3-hdr2
+ - mediatek,mt8195-mdp3-hdr3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_hdr0: mdp_hdr0@14004000
+ compatible = "mediatek,mt8195-mdp3-hdr0";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
new file mode 100644
index 000000000000..4e37cb0abe46
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 MERGE Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to merge
+ two slice-per-line inputs into one side-by-side output.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-merge2
+ - mediatek,mt8195-mdp3-merge3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge2";
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
new file mode 100644
index 000000000000..6be6da6b159b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 OVL Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform alpha blending from the memory.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-ovl0
+ - mediatek,mt8195-mdp3-ovl1
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_ovl0: mdp_ovl0@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl0";
+ reg = <0 0x14009000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x9000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
new file mode 100644
index 000000000000..883963a4861f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-pad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 PADDING Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to insert
+ pre-defined color or alpha value to arbitrary side of image.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-pad0
+ - mediatek,mt8195-mdp3-pad1
+ - mediatek,mt8195-mdp3-pad2
+ - mediatek,mt8195-mdp3-pad3
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_pad0: mdp_pad0@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad0";
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xa000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
index 002503383934..3b0779e8bfc2 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -26,6 +26,18 @@ properties:
# MDP3 controller node
- const: mediatek,mt8183-mdp3
- const: mediatek,mt8183-mdp3-rdma0
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8183-mdp3-rdma0
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8195-mdp3-rdma1
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8195-mdp3-rdma2
+ # MDP3 controller node
+ - const: mediatek,mt8195-mdp3
+ - const: mediatek,mt8195-mdp3-rdma3
- items:
# normal RDMA conponent
- const: mediatek,mt8183-mdp3-rdma0
@@ -46,12 +58,28 @@ properties:
- mediatek,mt8183-mdp3-dl1
- enum:
- mediatek,mt8183-mdp3-dl2
+ - enum:
+ - mediatek,mt8195-mdp3-dl1
+ - enum:
+ - mediatek,mt8195-mdp3-dl2
- enum:
# MDP direct-link output path selection, create a
# component for path connectedness of HW pipe control
- mediatek,mt8183-mdp3-path1
- enum:
- mediatek,mt8183-mdp3-path2
+ - enum:
+ - mediatek,mt8195-mdp3-path1
+ - enum:
+ - mediatek,mt8195-mdp3-path2
+ - enum:
+ - mediatek,mt8195-mdp3-path3
+ - enum:
+ - mediatek,mt8195-mdp3-path4
+ - enum:
+ - mediatek,mt8195-mdp3-path5
+ - enum:
+ - mediatek,mt8195-mdp3-path6
- enum:
# Input DMA of ISP PASS2 (DIP) module for raw image input
- mediatek,mt8183-mdp3-imgi
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
index cd4cf1531535..714038c9bab9 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -18,6 +18,8 @@ properties:
- enum:
- mediatek,mt8183-mdp3-rsz0
- mediatek,mt8183-mdp3-rsz1
+ - mediatek,mt8195-mdp3-rsz2
+ - mediatek,mt8195-mdp3-rsz3
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
new file mode 100644
index 000000000000..f3eb9cc92fd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-solit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 SPLIT Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to split hdmi rx into two stream
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-split
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ vpp_split0: vpp_split0@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
+ <&vppsys1 CLK_VPP1_DGI_IN>,
+ <&vppsys1 CLK_VPP1_DGI_OUT>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
new file mode 100644
index 000000000000..31cf3592c16f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 STITCH Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to combine multiple video frame
+ with overlapping fields of view to produce a segmented panorame.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-stitch
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_stitch0: mdp_stich0@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
new file mode 100644
index 000000000000..b5d6b0214fe0
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TCC Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to support
+ HDR gamma curve conversion HDR displays.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-tcc0
+ - mediatek,mt8195-mdp3-tcc1
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tcc0: mdp_tcc0@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc0";
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
new file mode 100644
index 000000000000..d967abd5fb7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TDSHP Device Tree Bindings
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to improve image sharpness and contrast.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8195-mdp3-tdshp0
+ - mediatek,mt8195-mdp3-tdshp1
+ - mediatek,mt8195-mdp3-tdshp2
+ - mediatek,mt8195-mdp3-tdshp3
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tdshp0: mdp_tdshp0@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp0";
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
index 7b0f9c4fffd7..d2e015bc09a2 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -17,6 +17,9 @@ properties:
items:
- enum:
- mediatek,mt8183-mdp3-wrot0
+ - mediatek,mt8195-mdp3-wrot1
+ - mediatek,mt8195-mdp3-wrot2
+ - mediatek,mt8195-mdp3-wrot3
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index a7ba7ebb9c53..26d69e0320ab 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -31,6 +31,12 @@ properties:
- const: mediatek,mt8183-disp-mutex
- items:
- const: mediatek,mt8192-disp-mutex
+ - items:
+ - const: mediatek,mt8192-disp-mutex
+ - items:
+ - const: mediatek,mt8195-vpp0-mutex
+ - items:
+ - const: mediatek,mt8195-vpp1-mutex
reg:
maxItems: 1
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v1 14/14] dt-bindings: media: mediatek: mdp3: add yaml for new modules added in mt8195
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-01-21 21:06 ` Rob Herring
-1 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-01-21 21:06 UTC (permalink / raw)
To: roy-cw.yeh
Cc: Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu,
Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
On Sun, Jan 16, 2022 at 11:53 PM roy-cw.yeh <roy-cw.yeh@mediatek.com> wrote:
>
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> Add yaml for new modules added in mt8195
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
> This patch is base on [1]
> [1] dt-bindings: arm: mediatek: move out common module from display folder
> - https://patchwork.kernel.org/project/linux-mediatek/patch/20220107101425.6917-8-jason-jh.lin@mediatek.com/
Looks to me like this is based on:
https://lore.kernel.org/r/20220105093758.6850-1-moudy.ho@mediatek.com
Can we have some coordination between all the MDP3 series. I have no
idea how all these sub-blocks fit together to provide any meaningful
review.
> ---
> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
> .../bindings/media/mediatek,mdp3-aal.yaml | 56 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-color.yaml | 56 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-fg.yaml | 55 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-hdr.yaml | 55 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-merge.yaml | 54 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-ovl.yaml | 53 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-pad.yaml | 56 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-rdma.yaml | 28 +++++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
> .../bindings/media/mediatek,mdp3-split.yaml | 58 ++++++++++++++++++
> .../bindings/media/mediatek,mdp3-stitch.yaml | 53 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-tcc.yaml | 54 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 3 +
> .../bindings/soc/mediatek/mediatek,mutex.yaml | 6 ++
> 16 files changed, 652 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 763c62323a74..9e59c8b738bb 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -31,6 +31,8 @@ properties:
> - mediatek,mt8183-mmsys
> - mediatek,mt8192-mmsys
> - mediatek,mt8365-mmsys
> + - mediatek,mt8195-vppsys0
> + - mediatek,mt8195-vppsys1
What's the difference between 0 and 1? Defining instance indices is
not how things are described in DT. If this is just the same block
with different connections, then you should be describing the
connections (with the graph binding). If there's some other
difference, then maybe those should be properties. I'm pretty sure
I've said this before.
The same question applies to the rest of the schemas with numbering.
Rob
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 14/14] dt-bindings: media: mediatek: mdp3: add yaml for new modules added in mt8195
@ 2022-01-21 21:06 ` Rob Herring
0 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-01-21 21:06 UTC (permalink / raw)
To: roy-cw.yeh
Cc: Matthias Brugger, AngeloGioacchino Del Regno, Chun-Kuang Hu,
Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
On Sun, Jan 16, 2022 at 11:53 PM roy-cw.yeh <roy-cw.yeh@mediatek.com> wrote:
>
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> Add yaml for new modules added in mt8195
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
> This patch is base on [1]
> [1] dt-bindings: arm: mediatek: move out common module from display folder
> - https://patchwork.kernel.org/project/linux-mediatek/patch/20220107101425.6917-8-jason-jh.lin@mediatek.com/
Looks to me like this is based on:
https://lore.kernel.org/r/20220105093758.6850-1-moudy.ho@mediatek.com
Can we have some coordination between all the MDP3 series. I have no
idea how all these sub-blocks fit together to provide any meaningful
review.
> ---
> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
> .../bindings/media/mediatek,mdp3-aal.yaml | 56 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-color.yaml | 56 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-fg.yaml | 55 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-hdr.yaml | 55 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-merge.yaml | 54 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-ovl.yaml | 53 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-pad.yaml | 56 +++++++++++++++++
> .../bindings/media/mediatek,mdp3-rdma.yaml | 28 +++++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
> .../bindings/media/mediatek,mdp3-split.yaml | 58 ++++++++++++++++++
> .../bindings/media/mediatek,mdp3-stitch.yaml | 53 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-tcc.yaml | 54 ++++++++++++++++
> .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 3 +
> .../bindings/soc/mediatek/mediatek,mutex.yaml | 6 ++
> 16 files changed, 652 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 763c62323a74..9e59c8b738bb 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -31,6 +31,8 @@ properties:
> - mediatek,mt8183-mmsys
> - mediatek,mt8192-mmsys
> - mediatek,mt8365-mmsys
> + - mediatek,mt8195-vppsys0
> + - mediatek,mt8195-vppsys1
What's the difference between 0 and 1? Defining instance indices is
not how things are described in DT. If this is just the same block
with different connections, then you should be describing the
connections (with the graph binding). If there's some other
difference, then maybe those should be properties. I'm pretty sure
I've said this before.
The same question applies to the rest of the schemas with numbering.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 06/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP
2022-01-17 5:52 ` roy-cw.yeh
(?)
@ 2022-01-27 15:02 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-27 15:02 UTC (permalink / raw)
To: roy-cw.yeh, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Yongqiang Niu, devicetree, linux-kernel, linux-media,
linux-arm-kernel, linux-mediatek
Il 17/01/22 06:52, roy-cw.yeh ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> 1. Modify struct member to 4 byte-alignment for MT8195 SCP limitation
> 2. Add new struct for hw engine adding in MT8195
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
This will break MT8183; is there any new firmware for that SoC that will
synchronize these structures?
Alternatively, you should add a new version of these structures and select
them with a wrapper function on a per-SoC basis, or per firmware version.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 06/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP
@ 2022-01-27 15:02 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-27 15:02 UTC (permalink / raw)
To: roy-cw.yeh, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Yongqiang Niu, devicetree, linux-kernel, linux-media,
linux-arm-kernel, linux-mediatek
Il 17/01/22 06:52, roy-cw.yeh ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> 1. Modify struct member to 4 byte-alignment for MT8195 SCP limitation
> 2. Add new struct for hw engine adding in MT8195
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
This will break MT8183; is there any new firmware for that SoC that will
synchronize these structures?
Alternatively, you should add a new version of these structures and select
them with a wrapper function on a per-SoC basis, or per firmware version.
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 06/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP
@ 2022-01-27 15:02 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-27 15:02 UTC (permalink / raw)
To: roy-cw.yeh, Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Yongqiang Niu, devicetree, linux-kernel, linux-media,
linux-arm-kernel, linux-mediatek
Il 17/01/22 06:52, roy-cw.yeh ha scritto:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> 1. Modify struct member to 4 byte-alignment for MT8195 SCP limitation
> 2. Add new struct for hw engine adding in MT8195
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
This will break MT8183; is there any new firmware for that SoC that will
synchronize these structures?
Alternatively, you should add a new version of these structures and select
them with a wrapper function on a per-SoC basis, or per firmware version.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 03/14] soc: mediatek: mmsys: support mt8195 vppsys0/1
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-03-18 8:58 ` CK Hu
-1 siblings, 0 replies; 39+ messages in thread
From: CK Hu @ 2022-03-18 8:58 UTC (permalink / raw)
To: roy-cw.yeh, Rob Herring, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
Hi, Roy:
On Mon, 2022-01-17 at 13:52 +0800, roy-cw.yeh wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> Add mt8195 vppsys driver data
> Add interface for mdp to set config table
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 23 +++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 22 ++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 3 +++
> include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
> 4 files changed, 52 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> b/drivers/soc/mediatek/mt8195-mmsys.h
> index e04cabdfa2dc..460d55e3ef86 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -165,6 +165,18 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 BIT(17)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> (BIT(17) | BIT(16))
>
> +/* VPPSYS0 */
> +#define VPPSYS0_HW_DCM_1ST_DIS0
> 0x050
> +
> +/* VPPSYS1 */
> +#define VPPSYS1_HW_DCM_1ST_DIS0
> 0x150
> +#define VPPSYS1_HW_DCM_1ST_DIS1
> 0x160
> +#define VPPSYS1_HW_DCM_2ND_DIS0
> 0x1a0
> +#define VPPSYS1_HW_DCM_2ND_DIS1
> 0x1b0
> +#define VPP0_DL_IRELAY_WR 0x920
> +#define SVPP2_BUF_BF_RSZ_SWITCH
> 0xf48
> +#define SVPP3_BUF_BF_RSZ_SWITCH
> 0xf74
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] =
> {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -217,4 +229,15 @@ static const struct mtk_mmsys_routes
> mmsys_mt8195_routing_table[] = {
> }
> };
>
> +static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = {
> + VPPSYS0_HW_DCM_1ST_DIS0,
> + VPP0_DL_IRELAY_WR,
> + VPPSYS1_HW_DCM_1ST_DIS0,
> + VPPSYS1_HW_DCM_1ST_DIS1,
> + VPPSYS1_HW_DCM_2ND_DIS0,
> + VPPSYS1_HW_DCM_2ND_DIS1,
> + SVPP2_BUF_BF_RSZ_SWITCH,
> + SVPP3_BUF_BF_RSZ_SWITCH,
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index a6ae10946eb6..c7beaa61ad64 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -79,10 +79,16 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys1_driver_data = {
>
> static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data
> = {
> .clk_driver = "clk-mt8195-vpp0",
> + .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
> + .mdp_num_mmsys_configs =
> ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
> + .vppsys = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data
> = {
> .clk_driver = "clk-mt8195-vpp1",
> + .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
> + .mdp_num_mmsys_configs =
> ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
> + .vppsys = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =
> {
> @@ -137,6 +143,18 @@ void mtk_mmsys_ddp_disconnect(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_mdp_write_config(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask)
Provide high level interface instead of this low level interface.
Regards,
CK
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const u32 *configs = mmsys->data->mdp_mmsys_configs;
> +
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> + mmsys->addr + configs[alias_id], value,
> mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_write_config);
> +
> void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> struct mmsys_cmdq_cmd *cmd,
> u32 offset, u32 value, u32 mask)
> @@ -367,6 +385,9 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> if (IS_ERR(clks))
> return PTR_ERR(clks);
>
> + if (mmsys->data->vppsys)
> + goto EXIT;
> +
> drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> PLATFORM_DEVID_AUTO, NULL,
> 0);
> if (IS_ERR(drm)) {
> @@ -374,6 +395,7 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> return PTR_ERR(drm);
> }
>
> +EXIT:
> return 0;
> }
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index ad8b92389b54..909713a28c14 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -94,6 +94,9 @@ struct mtk_mmsys_driver_data {
> const unsigned int num_routes;
> bool has_gce_client_reg;
> const unsigned int *mdp_isp_ctrl;
> + const u32 *mdp_mmsys_configs;
> + const unsigned int mdp_num_mmsys_configs;
> + bool vppsys;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index a772e53af9b5..946d161c8937 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -194,4 +194,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev,
> struct mmsys_cmdq_cmd *cmd,
> enum mtk_mdp_comp_id id,
> u32 camin_w, u32 camin_h);
>
> +void mtk_mmsys_mdp_write_config(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask);
> +
> #endif /* __MTK_MMSYS_H */
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 03/14] soc: mediatek: mmsys: support mt8195 vppsys0/1
@ 2022-03-18 8:58 ` CK Hu
0 siblings, 0 replies; 39+ messages in thread
From: CK Hu @ 2022-03-18 8:58 UTC (permalink / raw)
To: roy-cw.yeh, Rob Herring, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
Hi, Roy:
On Mon, 2022-01-17 at 13:52 +0800, roy-cw.yeh wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> Add mt8195 vppsys driver data
> Add interface for mdp to set config table
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 23 +++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 22 ++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 3 +++
> include/linux/soc/mediatek/mtk-mmsys.h | 4 ++++
> 4 files changed, 52 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> b/drivers/soc/mediatek/mt8195-mmsys.h
> index e04cabdfa2dc..460d55e3ef86 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -165,6 +165,18 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 BIT(17)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> (BIT(17) | BIT(16))
>
> +/* VPPSYS0 */
> +#define VPPSYS0_HW_DCM_1ST_DIS0
> 0x050
> +
> +/* VPPSYS1 */
> +#define VPPSYS1_HW_DCM_1ST_DIS0
> 0x150
> +#define VPPSYS1_HW_DCM_1ST_DIS1
> 0x160
> +#define VPPSYS1_HW_DCM_2ND_DIS0
> 0x1a0
> +#define VPPSYS1_HW_DCM_2ND_DIS1
> 0x1b0
> +#define VPP0_DL_IRELAY_WR 0x920
> +#define SVPP2_BUF_BF_RSZ_SWITCH
> 0xf48
> +#define SVPP3_BUF_BF_RSZ_SWITCH
> 0xf74
> +
> static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] =
> {
> {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -217,4 +229,15 @@ static const struct mtk_mmsys_routes
> mmsys_mt8195_routing_table[] = {
> }
> };
>
> +static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = {
> + VPPSYS0_HW_DCM_1ST_DIS0,
> + VPP0_DL_IRELAY_WR,
> + VPPSYS1_HW_DCM_1ST_DIS0,
> + VPPSYS1_HW_DCM_1ST_DIS1,
> + VPPSYS1_HW_DCM_2ND_DIS0,
> + VPPSYS1_HW_DCM_2ND_DIS1,
> + SVPP2_BUF_BF_RSZ_SWITCH,
> + SVPP3_BUF_BF_RSZ_SWITCH,
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index a6ae10946eb6..c7beaa61ad64 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -79,10 +79,16 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys1_driver_data = {
>
> static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data
> = {
> .clk_driver = "clk-mt8195-vpp0",
> + .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
> + .mdp_num_mmsys_configs =
> ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
> + .vppsys = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data
> = {
> .clk_driver = "clk-mt8195-vpp1",
> + .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
> + .mdp_num_mmsys_configs =
> ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
> + .vppsys = true,
> };
>
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =
> {
> @@ -137,6 +143,18 @@ void mtk_mmsys_ddp_disconnect(struct device
> *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_mdp_write_config(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask)
Provide high level interface instead of this low level interface.
Regards,
CK
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const u32 *configs = mmsys->data->mdp_mmsys_configs;
> +
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
> + mmsys->addr + configs[alias_id], value,
> mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_write_config);
> +
> void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
> struct mmsys_cmdq_cmd *cmd,
> u32 offset, u32 value, u32 mask)
> @@ -367,6 +385,9 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> if (IS_ERR(clks))
> return PTR_ERR(clks);
>
> + if (mmsys->data->vppsys)
> + goto EXIT;
> +
> drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
> PLATFORM_DEVID_AUTO, NULL,
> 0);
> if (IS_ERR(drm)) {
> @@ -374,6 +395,7 @@ static int mtk_mmsys_probe(struct platform_device
> *pdev)
> return PTR_ERR(drm);
> }
>
> +EXIT:
> return 0;
> }
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index ad8b92389b54..909713a28c14 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -94,6 +94,9 @@ struct mtk_mmsys_driver_data {
> const unsigned int num_routes;
> bool has_gce_client_reg;
> const unsigned int *mdp_isp_ctrl;
> + const u32 *mdp_mmsys_configs;
> + const unsigned int mdp_num_mmsys_configs;
> + bool vppsys;
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index a772e53af9b5..946d161c8937 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -194,4 +194,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev,
> struct mmsys_cmdq_cmd *cmd,
> enum mtk_mdp_comp_id id,
> u32 camin_w, u32 camin_h);
>
> +void mtk_mmsys_mdp_write_config(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + u32 alias_id, u32 value, u32 mask);
> +
> #endif /* __MTK_MMSYS_H */
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 02/14] soc: mediatek: mutex: expand parameter for mdp mutex function
2022-01-17 5:52 ` roy-cw.yeh
@ 2022-03-18 9:23 ` CK Hu
-1 siblings, 0 replies; 39+ messages in thread
From: CK Hu @ 2022-03-18 9:23 UTC (permalink / raw)
To: roy-cw.yeh, Rob Herring, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
Hi, Roy:
On Mon, 2022-01-17 at 13:52 +0800, roy-cw.yeh wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> Expand parameter for mdp mutex function
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
> This patch is base on [1][2]
> [1] soc: mediatek: mutex: add functions that operate registers by
> CMDQ
> -
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220104091712.25670-5-moudy.ho@mediatek.com/__;!!CTRNKA9wMg0ARbw!28saNp-15JnZswiyVpRSXYtGcevLvGr2FEapxkshXVSBltSnkpE2iPgK4HDCWg$
>
> [2] media: platform: mtk-mdp3: add Mediatek MDP3 driver
> -
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220105093758.6850-4-moudy.ho@mediatek.com/__;!!CTRNKA9wMg0ARbw!28saNp-15JnZswiyVpRSXYtGcevLvGr2FEapxkshXVSBltSnkpE2iPhg9ACQ7Q$
>
> ---
> .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 3 ++-
> drivers/soc/mediatek/mtk-mutex.c | 26 +++++++++++++--
> ----
> include/linux/soc/mediatek/mtk-mutex.h | 2 +-
> 3 files changed, 21 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> index 4a08502952d6..87751f0e2513 100644
> --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> @@ -101,7 +101,8 @@ static int mdp_path_subfrm_require(struct
> mdp_path_subfrm *subfrm,
> }
>
> if (subfrm->mutex_mod)
> - mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm-
> >mutex_mod, cmd);
> + mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm-
> >mutex_mod,
> + 0, 0, cmd);
>
> /* Set SOF */
> for (index = 0; index < config->num_components; index++) {
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index 89daab7e6863..7da0f44b6f9a 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -27,8 +27,9 @@
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 *
> (n))
> -#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 *
> (n))
> -#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 *
> (n))
> +#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20
> * (n))
> +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg
> ) + 0x20 * (n) + 0x4)
> +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) ((mutex_sof_reg) + 0x20
> * (n))
> #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 *
> (n))
>
> #define INT_MUTEX BIT(1)
> @@ -180,6 +181,11 @@
> #define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
> #define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
>
> +#define
> MT8183_MDP_PIPE_IMGI MT8183_MUTEX_MDP_START
> +#define
> MT8183_MDP_PIPE_RDMA0 (MT8183_MUTEX_MDP_START + 1)
> +#define
> MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
> +#define
> MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -364,10 +370,10 @@ static const unsigned int
> mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>
> /* indicate which mutex is used by each pipepline */
> static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
> - [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> - [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> - [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> - [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> + [MDP_PIPE_IMGI] = MT8183_MDP_PIPE_IMGI,
> + [MDP_PIPE_RDMA0] = MT8183_MDP_PIPE_RDMA0,
> + [MDP_PIPE_WPEI] = MT8183_MDP_PIPE_WPEI,
> + [MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2,
> };
>
> static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> @@ -606,7 +612,7 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex
> *mutex, enum mtk_mdp_comp_id id)
> EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
>
> void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> - struct mmsys_cmdq_cmd *cmd)
> + u32 mod1, u32 sof, struct mmsys_cmdq_cmd
> *cmd)
In cover letter, describe this series depend on which series.
And, why do you need add mod by cmdq? I expect that pipeline is fixed
before it start working.
Regards,
CK
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> mutex[mutex->id]);
> @@ -618,9 +624,13 @@ void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex
> *mutex, u32 mod,
> cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> mod, mtx->data->mutex_mdp_mod_mask);
>
> + offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + mod1, mtx->data->mutex_mdp_mod_mask);
> +
> offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex-
> >id);
> cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> - 0, mtx->data->mutex_mdp_sof_mask);
> + sof, mtx->data->mutex_mdp_sof_mask);
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
>
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index 05de7ad4a124..dbb7324c12d9 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -18,7 +18,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> - struct mmsys_cmdq_cmd *cmd);
> + u32 mod1, u32 sof, struct mmsys_cmdq_cmd
> *cmd);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> struct mmsys_cmdq_cmd *cmd);
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v1 02/14] soc: mediatek: mutex: expand parameter for mdp mutex function
@ 2022-03-18 9:23 ` CK Hu
0 siblings, 0 replies; 39+ messages in thread
From: CK Hu @ 2022-03-18 9:23 UTC (permalink / raw)
To: roy-cw.yeh, Rob Herring, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, jason-jh . lin,
daoyuan huang, Ping-Hsun Wu, Moudy Ho, river . cheng,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
Hi, Roy:
On Mon, 2022-01-17 at 13:52 +0800, roy-cw.yeh wrote:
> From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
>
> Expand parameter for mdp mutex function
>
> Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
> ---
> This patch is base on [1][2]
> [1] soc: mediatek: mutex: add functions that operate registers by
> CMDQ
> -
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220104091712.25670-5-moudy.ho@mediatek.com/__;!!CTRNKA9wMg0ARbw!28saNp-15JnZswiyVpRSXYtGcevLvGr2FEapxkshXVSBltSnkpE2iPgK4HDCWg$
>
> [2] media: platform: mtk-mdp3: add Mediatek MDP3 driver
> -
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220105093758.6850-4-moudy.ho@mediatek.com/__;!!CTRNKA9wMg0ARbw!28saNp-15JnZswiyVpRSXYtGcevLvGr2FEapxkshXVSBltSnkpE2iPhg9ACQ7Q$
>
> ---
> .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 3 ++-
> drivers/soc/mediatek/mtk-mutex.c | 26 +++++++++++++--
> ----
> include/linux/soc/mediatek/mtk-mutex.h | 2 +-
> 3 files changed, 21 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> index 4a08502952d6..87751f0e2513 100644
> --- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> +++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> @@ -101,7 +101,8 @@ static int mdp_path_subfrm_require(struct
> mdp_path_subfrm *subfrm,
> }
>
> if (subfrm->mutex_mod)
> - mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm-
> >mutex_mod, cmd);
> + mtk_mutex_add_mod_by_cmdq(mutex[mutex_id], subfrm-
> >mutex_mod,
> + 0, 0, cmd);
>
> /* Set SOF */
> for (index = 0; index < config->num_components; index++) {
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index 89daab7e6863..7da0f44b6f9a 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -27,8 +27,9 @@
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 *
> (n))
> -#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 *
> (n))
> -#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 *
> (n))
> +#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20
> * (n))
> +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg
> ) + 0x20 * (n) + 0x4)
> +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) ((mutex_sof_reg) + 0x20
> * (n))
> #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 *
> (n))
>
> #define INT_MUTEX BIT(1)
> @@ -180,6 +181,11 @@
> #define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
> #define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
>
> +#define
> MT8183_MDP_PIPE_IMGI MT8183_MUTEX_MDP_START
> +#define
> MT8183_MDP_PIPE_RDMA0 (MT8183_MUTEX_MDP_START + 1)
> +#define
> MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
> +#define
> MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -364,10 +370,10 @@ static const unsigned int
> mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
>
> /* indicate which mutex is used by each pipepline */
> static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
> - [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> - [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> - [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> - [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> + [MDP_PIPE_IMGI] = MT8183_MDP_PIPE_IMGI,
> + [MDP_PIPE_RDMA0] = MT8183_MDP_PIPE_RDMA0,
> + [MDP_PIPE_WPEI] = MT8183_MDP_PIPE_WPEI,
> + [MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2,
> };
>
> static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> @@ -606,7 +612,7 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex
> *mutex, enum mtk_mdp_comp_id id)
> EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
>
> void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> - struct mmsys_cmdq_cmd *cmd)
> + u32 mod1, u32 sof, struct mmsys_cmdq_cmd
> *cmd)
In cover letter, describe this series depend on which series.
And, why do you need add mod by cmdq? I expect that pipeline is fixed
before it start working.
Regards,
CK
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> mtk_mutex_ctx,
> mutex[mutex->id]);
> @@ -618,9 +624,13 @@ void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex
> *mutex, u32 mod,
> cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> mod, mtx->data->mutex_mdp_mod_mask);
>
> + offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, mutex-
> >id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> + mod1, mtx->data->mutex_mdp_mod_mask);
> +
> offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex-
> >id);
> cmdq_pkt_write_mask(cmd->pkt, mtx->cmdq_reg.subsys, mtx->addr +
> offset,
> - 0, mtx->data->mutex_mdp_sof_mask);
> + sof, mtx->data->mutex_mdp_sof_mask);
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
>
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> b/include/linux/soc/mediatek/mtk-mutex.h
> index 05de7ad4a124..dbb7324c12d9 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -18,7 +18,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum
> mtk_mdp_comp_id id);
> void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
> - struct mmsys_cmdq_cmd *cmd);
> + u32 mod1, u32 sof, struct mmsys_cmdq_cmd
> *cmd);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> struct mmsys_cmdq_cmd *cmd);
_______________________________________________
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^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2022-03-18 9:28 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-17 5:52 [PATCH v1 00/14] Add mdp support for mt8195 roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 01/14] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 02/14] soc: mediatek: mutex: expand parameter for mdp mutex function roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-03-18 9:23 ` CK Hu
2022-03-18 9:23 ` CK Hu
2022-01-17 5:52 ` [PATCH v1 03/14] soc: mediatek: mmsys: support mt8195 vppsys0/1 roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-03-18 8:58 ` CK Hu
2022-03-18 8:58 ` CK Hu
2022-01-17 5:52 ` [PATCH v1 04/14] soc: mediatek: mutex: " roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 05/14] media: platform: mtk-mdp3: add chip independence architecture roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 06/14] media: platform: mtk-mdp3: Modify mtk-img-ipi.h for MT8195 SCP roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-27 15:02 ` AngeloGioacchino Del Regno
2022-01-27 15:02 ` AngeloGioacchino Del Regno
2022-01-27 15:02 ` AngeloGioacchino Del Regno
2022-01-17 5:52 ` [PATCH v1 07/14] media: platform: mtk-mdp3: Add platform configuration for MT8195 roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 08/14] media: platform: mtk-mdp3: Add engine setting " roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 09/14] media: platform: mtk-mdp3: Add support MT8195 roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 10/14] media: platform: mtk-mdp3: Add dual pipe feature support roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 11/14] media: platform: mtk-mdp3: Revise frame change criteria roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 12/14] media: platform: mtk-mdp3: Reconfigure shared memory roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 13/14] arm64: dts: mt8195: add mdp3 node roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-17 5:52 ` [PATCH v1 14/14] dt-bindings: media: mediatek: mdp3: add yaml for new modules added in mt8195 roy-cw.yeh
2022-01-17 5:52 ` roy-cw.yeh
2022-01-21 21:06 ` Rob Herring
2022-01-21 21:06 ` Rob Herring
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