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SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(40470700002)(54906003)(8676002)(316002)(8936002)(4326008)(36860700001)(83380400001)(508600001)(336012)(426003)(40460700001)(82310400004)(5660300002)(356005)(7696005)(36756003)(70586007)(6916009)(70206006)(1076003)(2616005)(16526019)(26005)(86362001)(2906002)(81166007)(186003)(47076005)(6666004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2022 06:33:19.5597 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d35d1403-1ed5-4045-35be-08d9d983408a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5314 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexander.deucher@amd.com, Somalapuram Amaranath , christian.koenig@amd.com, shashank.sharma@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Implementation of register trace dump function on the AMD GPU resets Signed-off-by: Somalapuram Amaranath --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 8 ++++ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 53 ++++++++++++++++++++++- drivers/gpu/drm/amd/include/amd_shared.h | 1 + 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index d855cb53c7e0..c97b53b54333 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -537,6 +537,14 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, __entry->seqno) ); +TRACE_EVENT(gfx_v10_0_reset_reg_dumps, + TP_PROTO(char *reg_dumps), + TP_ARGS(reg_dumps), + TP_STRUCT__entry(__string(dumps, reg_dumps)), + TP_fast_assign(__assign_str(dumps, reg_dumps);), + TP_printk("amdgpu register dump {%s}", __get_str(dumps)) +); + #undef AMDGPU_JOB_GET_TIMELINE_NAME #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index dbe7442fb25c..a63cdd0ad53a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -46,7 +46,7 @@ #include "v10_structs.h" #include "gfx_v10_0.h" #include "nbio_v2_3.h" - +#include "amdgpu_trace.h" /* * Navi10 has two graphic rings to share each graphic pipe. * 1. Primary ring @@ -188,6 +188,12 @@ #define RLCG_ERROR_REPORT_ENABLED(adev) \ (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) +#define N_REGS (17) +#define DUMP_REG(addr) do { \ + (dump)[i][0] = (addr); \ + (dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ + } while (0) + MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); MODULE_FIRMWARE("amdgpu/navi10_me.bin"); @@ -7466,7 +7472,6 @@ static int gfx_v10_0_hw_init(void *handle) { int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (!amdgpu_emu_mode) gfx_v10_0_init_golden_registers(adev); @@ -7580,6 +7585,49 @@ static int gfx_v10_0_hw_fini(void *handle) return 0; } +static int gfx_v10_0_reset_reg_dumps(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uint32_t i = 0; + uint32_t (*dump)[2], n_regs = 0; + char *reg_dumps; + + dump = kmalloc(N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + reg_dumps = kmalloc(1024, GFP_KERNEL); + + if (dump == NULL || reg_dumps == NULL) + return -ENOMEM; + + DUMP_REG(mmGRBM_STATUS2); + DUMP_REG(mmGRBM_STATUS_SE0); + DUMP_REG(mmGRBM_STATUS_SE1); + DUMP_REG(mmGRBM_STATUS_SE2); + DUMP_REG(mmGRBM_STATUS_SE3); + DUMP_REG(mmSDMA0_STATUS_REG); + DUMP_REG(mmSDMA1_STATUS_REG); + DUMP_REG(mmCP_STAT); + DUMP_REG(mmCP_STALLED_STAT1); + DUMP_REG(mmCP_STALLED_STAT1); + DUMP_REG(mmCP_STALLED_STAT3); + DUMP_REG(mmCP_CPC_STATUS); + DUMP_REG(mmCP_CPC_BUSY_STAT); + DUMP_REG(mmCP_CPC_STALLED_STAT1); + DUMP_REG(mmCP_CPF_STATUS); + DUMP_REG(mmCP_CPF_BUSY_STAT); + DUMP_REG(mmCP_CPF_STALLED_STAT1); + + n_regs = i; + + for (i = 0; i < n_regs; i++) + sprintf(reg_dumps + strlen(reg_dumps), "%08x: %08x, ", dump[i][0], dump[i][1]); + + trace_gfx_v10_0_reset_reg_dumps(reg_dumps); + kfree(dump); + kfree(reg_dumps); + + return 0; +} + static int gfx_v10_0_suspend(void *handle) { return gfx_v10_0_hw_fini(handle); @@ -9359,6 +9407,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { .set_clockgating_state = gfx_v10_0_set_clockgating_state, .set_powergating_state = gfx_v10_0_set_powergating_state, .get_clockgating_state = gfx_v10_0_get_clockgating_state, + .reset_reg_dumps = gfx_v10_0_reset_reg_dumps, }; static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 4b9e68a79f06..a165680d73a2 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -298,6 +298,7 @@ struct amd_ip_funcs { enum amd_powergating_state state); void (*get_clockgating_state)(void *handle, u32 *flags); int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level); + int (*reset_reg_dumps)(void *handle); }; -- 2.25.1