From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5F55C433F5 for ; Mon, 17 Jan 2022 15:03:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240100AbiAQPDX (ORCPT ); Mon, 17 Jan 2022 10:03:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233003AbiAQPDW (ORCPT ); Mon, 17 Jan 2022 10:03:22 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09BC5C061574; Mon, 17 Jan 2022 07:03:22 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 1A1ECCE13C4; Mon, 17 Jan 2022 15:03:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA80BC36AE7; Mon, 17 Jan 2022 15:03:16 +0000 (UTC) Date: Mon, 17 Jan 2022 10:03:14 -0500 From: Steven Rostedt To: Sai Prakash Ranjan Cc: Will Deacon , Catalin Marinas , Marc Zyngier , Arnd Bergmann , gregkh , , "Trilok Soni" , , , , Prasad Sodagudi Subject: Re: [PATCHv8 4/5] lib: Add register read/write tracing support Message-ID: <20220117100314.416a4d68@rorschach.local.home> In-Reply-To: <8ad60797d6d8f40c3bdba20b1678fa9014bc1a20.1642309054.git.quic_saipraka@quicinc.com> References: <8ad60797d6d8f40c3bdba20b1678fa9014bc1a20.1642309054.git.quic_saipraka@quicinc.com> X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, 17 Jan 2022 09:02:53 +0530 Sai Prakash Ranjan wrote: > diff --git a/include/trace/events/rwmmio.h b/include/trace/events/rwmmio.h > new file mode 100644 > index 000000000000..798fbe1ac9f9 > --- /dev/null > +++ b/include/trace/events/rwmmio.h > @@ -0,0 +1,112 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > +#undef TRACE_SYSTEM > +#define TRACE_SYSTEM rwmmio > + > +#if !defined(_TRACE_RWMMIO_H) || defined(TRACE_HEADER_MULTI_READ) > +#define _TRACE_RWMMIO_H > + > +#include > + > +TRACE_EVENT(rwmmio_write, > + > + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), > + > + TP_ARGS(caller, val, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, val) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->val = val; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d val=%#llx addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, > + __entry->val, __entry->addr) > +); > + > +TRACE_EVENT(rwmmio_post_write, > + > + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), > + > + TP_ARGS(caller, val, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, val) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->val = val; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d val=%#llx addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, > + __entry->val, __entry->addr) > +); > + > +TRACE_EVENT(rwmmio_read, > + > + TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr), > + > + TP_ARGS(caller, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr) > +); > + > +TRACE_EVENT(rwmmio_post_read, > + > + TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr), > + > + TP_ARGS(caller, val, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, val) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->val = val; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d val=%#llx addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, > + __entry->val, __entry->addr) > +); The above should be replaced with: DECLARE_EVENT_CLASS(rwmmio_rw_template, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr), TP_STRUCT__entry( __field(u64, caller) __field(u64, val) __field(u64, addr) __field(u8, width) ), TP_fast_assign( __entry->caller = caller; __entry->val = val; __entry->addr = (unsigned long)(void *)addr; __entry->width = width; ), TP_printk("%pS width=%d val=%#llx addr=%#llx", (void *)(unsigned long)__entry->caller, __entry->width, __entry->val, __entry->addr) ); DEFINE_EVENT(rwmmio_rw_template, rwmmio_write, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr) ); DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr) ); DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_read, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr) ); It will save around 15k in memory. And since rwmmio_read doesn't have a val field, it can stay a TRACE_EVENT. TRACE_EVENT(rwmmio_read, TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr), TP_ARGS(caller, width, addr), TP_STRUCT__entry( __field(u64, caller) __field(u64, addr) __field(u8, width) ), TP_fast_assign( __entry->caller = caller; __entry->addr = (unsigned long)(void *)addr; __entry->width = width; ), TP_printk("%pS width=%d addr=%#llx", (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr) ); -- Steve > + > +#endif /* _TRACE_RWMMIO_H */ > + > +#include > diff --git a/lib/Kconfig b/lib/Kconfig > index c80fde816a7e..ea520c315c0f 100644 > --- a/lib/Kconfig > +++ b/lib/Kconfig > @@ -119,6 +119,13 @@ config INDIRECT_IOMEM_FALLBACK > mmio accesses when the IO memory address is not a registered > emulated region. > > +config TRACE_MMIO_ACCESS > + bool "Register read/write tracing" > + depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS > + help > + Create tracepoints for MMIO read/write operations. These trace events > + can be used for logging all MMIO read/write operations. > + > source "lib/crypto/Kconfig" > > config CRC_CCITT > diff --git a/lib/Makefile b/lib/Makefile > index 300f569c626b..43813b0061cd 100644 > --- a/lib/Makefile > +++ b/lib/Makefile > @@ -152,6 +152,8 @@ lib-y += logic_pio.o > > lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o > > +obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o > + > obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o > > obj-$(CONFIG_BTREE) += btree.o > diff --git a/lib/trace_readwrite.c b/lib/trace_readwrite.c > new file mode 100644 > index 000000000000..88637038b30c > --- /dev/null > +++ b/lib/trace_readwrite.c > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Register read and write tracepoints > + * > + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > + > +#define CREATE_TRACE_POINTS > +#include > + > +#ifdef CONFIG_TRACE_MMIO_ACCESS > +void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_write(caller_addr, val, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_write_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write); > + > +void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_post_write(caller_addr, val, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_post_write_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write); > + > +void log_read_mmio(u8 width, const volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_read(caller_addr, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_read_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read); > + > +void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_post_read(caller_addr, val, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_post_read_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read); > +#endif /* CONFIG_TRACE_MMIO_ACCESS */ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B759C433FE for ; Mon, 17 Jan 2022 15:04:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ul3KAkGjJzRig8g1pB6LgdAxtPo4CgXt5D7ESPhuA3U=; b=AvyHAwgeuOByix ViOdK7qLRoeW9aFGCdvq2YJDfCMlcOdGOO2Eo/ZWXL7lUoBPYVj2wik9ETWaC0/ZaXMamH4dEndS3 hrtf0SlMflCmsNeD5ymcwaLPgF4LhUDy2+KFpIIchFFUmsyN1qO5VZjUqu89i1c5YsS0AAvfTrS7L yyi5VpUBxC21JswuNNfasut+EtYQCN+KP24fnBnWI3XE850UmgfVguhstSlwUgr9YEiNf2T2ABbyR EoOUfka6aYFcEt8ZI6qGEGXr+TyXeLlRWfbEwTduXGo8LuJDJbq8V623awlKLHXLJ2RCJ9OsNj0lk LIqcZZrFnV80BtCh1kfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9TXZ-00FJku-IO; Mon, 17 Jan 2022 15:03:25 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9TXU-00FJj7-CM for linux-arm-kernel@lists.infradead.org; Mon, 17 Jan 2022 15:03:22 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1FE0360AAD; Mon, 17 Jan 2022 15:03:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA80BC36AE7; Mon, 17 Jan 2022 15:03:16 +0000 (UTC) Date: Mon, 17 Jan 2022 10:03:14 -0500 From: Steven Rostedt To: Sai Prakash Ranjan Cc: Will Deacon , Catalin Marinas , Marc Zyngier , Arnd Bergmann , gregkh , , "Trilok Soni" , , , , Prasad Sodagudi Subject: Re: [PATCHv8 4/5] lib: Add register read/write tracing support Message-ID: <20220117100314.416a4d68@rorschach.local.home> In-Reply-To: <8ad60797d6d8f40c3bdba20b1678fa9014bc1a20.1642309054.git.quic_saipraka@quicinc.com> References: <8ad60797d6d8f40c3bdba20b1678fa9014bc1a20.1642309054.git.quic_saipraka@quicinc.com> X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220117_070320_576630_7744F71A X-CRM114-Status: GOOD ( 20.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 17 Jan 2022 09:02:53 +0530 Sai Prakash Ranjan wrote: > diff --git a/include/trace/events/rwmmio.h b/include/trace/events/rwmmio.h > new file mode 100644 > index 000000000000..798fbe1ac9f9 > --- /dev/null > +++ b/include/trace/events/rwmmio.h > @@ -0,0 +1,112 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > +#undef TRACE_SYSTEM > +#define TRACE_SYSTEM rwmmio > + > +#if !defined(_TRACE_RWMMIO_H) || defined(TRACE_HEADER_MULTI_READ) > +#define _TRACE_RWMMIO_H > + > +#include > + > +TRACE_EVENT(rwmmio_write, > + > + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), > + > + TP_ARGS(caller, val, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, val) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->val = val; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d val=%#llx addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, > + __entry->val, __entry->addr) > +); > + > +TRACE_EVENT(rwmmio_post_write, > + > + TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), > + > + TP_ARGS(caller, val, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, val) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->val = val; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d val=%#llx addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, > + __entry->val, __entry->addr) > +); > + > +TRACE_EVENT(rwmmio_read, > + > + TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr), > + > + TP_ARGS(caller, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr) > +); > + > +TRACE_EVENT(rwmmio_post_read, > + > + TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr), > + > + TP_ARGS(caller, val, width, addr), > + > + TP_STRUCT__entry( > + __field(u64, caller) > + __field(u64, val) > + __field(u64, addr) > + __field(u8, width) > + ), > + > + TP_fast_assign( > + __entry->caller = caller; > + __entry->val = val; > + __entry->addr = (unsigned long)(void *)addr; > + __entry->width = width; > + ), > + > + TP_printk("%pS width=%d val=%#llx addr=%#llx", > + (void *)(unsigned long)__entry->caller, __entry->width, > + __entry->val, __entry->addr) > +); The above should be replaced with: DECLARE_EVENT_CLASS(rwmmio_rw_template, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr), TP_STRUCT__entry( __field(u64, caller) __field(u64, val) __field(u64, addr) __field(u8, width) ), TP_fast_assign( __entry->caller = caller; __entry->val = val; __entry->addr = (unsigned long)(void *)addr; __entry->width = width; ), TP_printk("%pS width=%d val=%#llx addr=%#llx", (void *)(unsigned long)__entry->caller, __entry->width, __entry->val, __entry->addr) ); DEFINE_EVENT(rwmmio_rw_template, rwmmio_write, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr) ); DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr) ); DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_read, TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr), TP_ARGS(caller, val, width, addr) ); It will save around 15k in memory. And since rwmmio_read doesn't have a val field, it can stay a TRACE_EVENT. TRACE_EVENT(rwmmio_read, TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr), TP_ARGS(caller, width, addr), TP_STRUCT__entry( __field(u64, caller) __field(u64, addr) __field(u8, width) ), TP_fast_assign( __entry->caller = caller; __entry->addr = (unsigned long)(void *)addr; __entry->width = width; ), TP_printk("%pS width=%d addr=%#llx", (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr) ); -- Steve > + > +#endif /* _TRACE_RWMMIO_H */ > + > +#include > diff --git a/lib/Kconfig b/lib/Kconfig > index c80fde816a7e..ea520c315c0f 100644 > --- a/lib/Kconfig > +++ b/lib/Kconfig > @@ -119,6 +119,13 @@ config INDIRECT_IOMEM_FALLBACK > mmio accesses when the IO memory address is not a registered > emulated region. > > +config TRACE_MMIO_ACCESS > + bool "Register read/write tracing" > + depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS > + help > + Create tracepoints for MMIO read/write operations. These trace events > + can be used for logging all MMIO read/write operations. > + > source "lib/crypto/Kconfig" > > config CRC_CCITT > diff --git a/lib/Makefile b/lib/Makefile > index 300f569c626b..43813b0061cd 100644 > --- a/lib/Makefile > +++ b/lib/Makefile > @@ -152,6 +152,8 @@ lib-y += logic_pio.o > > lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o > > +obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o > + > obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o > > obj-$(CONFIG_BTREE) += btree.o > diff --git a/lib/trace_readwrite.c b/lib/trace_readwrite.c > new file mode 100644 > index 000000000000..88637038b30c > --- /dev/null > +++ b/lib/trace_readwrite.c > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Register read and write tracepoints > + * > + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > + > +#define CREATE_TRACE_POINTS > +#include > + > +#ifdef CONFIG_TRACE_MMIO_ACCESS > +void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_write(caller_addr, val, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_write_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write); > + > +void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_post_write(caller_addr, val, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_post_write_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write); > + > +void log_read_mmio(u8 width, const volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_read(caller_addr, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_read_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read); > + > +void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr, > + unsigned long caller_addr) > +{ > + trace_rwmmio_post_read(caller_addr, val, width, addr); > +} > +EXPORT_SYMBOL_GPL(log_post_read_mmio); > +EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read); > +#endif /* CONFIG_TRACE_MMIO_ACCESS */ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel