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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT019.mail.protection.outlook.com (10.13.175.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4888.9 via Frontend Transport; Tue, 18 Jan 2022 11:06:49 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 18 Jan 2022 05:06:40 -0600 From: Nikunj A Dadhania To: Paolo Bonzini CC: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Brijesh Singh , Tom Lendacky , Peter Gonda , , , Nikunj A Dadhania Subject: [RFC PATCH 0/6] KVM: SVM: Defer page pinning for SEV guests Date: Tue, 18 Jan 2022 16:36:15 +0530 Message-ID: <20220118110621.62462-1-nikunj@amd.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f36799a7-a3d1-4ed2-95b7-08d9da72a05d X-MS-TrafficTypeDiagnostic: CY4PR12MB1173:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2022 11:06:49.9688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f36799a7-a3d1-4ed2-95b7-08d9da72a05d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1173 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SEV guest requires the guest's pages to be pinned in host physical memory as migration of encrypted pages is not supported. The memory encryption scheme uses the physical address of the memory being encrypted. If guest pages are moved by the host, content decrypted in the guest would be incorrect thereby corrupting guest's memory. For SEV/SEV-ES guests, the hypervisor doesn't know which pages are encrypted and when the guest is done using those pages. Hypervisor should treat all the guest pages as encrypted until the guest is destroyed. Actual pinning management is handled by vendor code via new kvm_x86_ops hooks. MMU calls in to vendor code to pin the page on demand. Metadata of the pinning is stored in architecture specific memslot area. During the memslot freeing path guest pages are unpinned. Initially started with [1], where the idea was to store the pinning information using the software bit in the SPTE to track the pinned page. That is not feasible for the following reason: The pinned SPTE information gets stored in the shadow pages(SP). The way current MMU is designed, the full MMU context gets dropped multiple number of times even when CR0.WP bit gets flipped. Due to dropping of the MMU context (aka roots), there is a huge amount of SP alloc/remove churn. Pinned information stored in the SP gets lost during the dropping of the root and subsequent SP at the child levels. Without this information making decisions about re-pinnning page or unpinning during the guest shutdown will not be possible [1] https://patchwork.kernel.org/project/kvm/cover/20200731212323.21746-1-sean.j.christopherson@intel.com/ Nikunj A Dadhania (4): KVM: x86/mmu: Add hook to pin PFNs on demand in MMU KVM: SVM: Add pinning metadata in the arch memslot KVM: SVM: Implement demand page pinning KVM: SEV: Carve out routine for allocation of pages Sean Christopherson (2): KVM: x86/mmu: Introduce kvm_mmu_map_tdp_page() for use by SEV/TDX KVM: SVM: Pin SEV pages in MMU during sev_launch_update_data() arch/x86/include/asm/kvm-x86-ops.h | 3 + arch/x86/include/asm/kvm_host.h | 9 + arch/x86/kvm/mmu.h | 3 + arch/x86/kvm/mmu/mmu.c | 41 +++ arch/x86/kvm/mmu/tdp_mmu.c | 7 + arch/x86/kvm/svm/sev.c | 423 +++++++++++++++++++---------- arch/x86/kvm/svm/svm.c | 4 + arch/x86/kvm/svm/svm.h | 9 +- arch/x86/kvm/x86.c | 11 +- 9 files changed, 359 insertions(+), 151 deletions(-) -- 2.32.0