From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A5A9C433FE for ; Wed, 19 Jan 2022 04:53:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351587AbiASExv (ORCPT ); Tue, 18 Jan 2022 23:53:51 -0500 Received: from mo-csw1516.securemx.jp ([210.130.202.155]:48472 "EHLO mo-csw.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351335AbiASExu (ORCPT ); Tue, 18 Jan 2022 23:53:50 -0500 Received: by mo-csw.securemx.jp (mx-mo-csw1516) id 20J4qDKk018584; Wed, 19 Jan 2022 13:52:14 +0900 X-Iguazu-Qid: 34trXZuAsxlohqpaPS X-Iguazu-QSIG: v=2; s=0; t=1642567933; q=34trXZuAsxlohqpaPS; m=0yidoEs59p9yDaB5qifBWEqQ4TxJweLoniwSrs5tqCI= Received: from imx12-a.toshiba.co.jp (imx12-a.toshiba.co.jp [61.202.160.135]) by relay.securemx.jp (mx-mr1513) id 20J4qBLp037215 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Wed, 19 Jan 2022 13:52:12 +0900 X-SA-MID: 31820870 From: Yuji Ishikawa To: "David S . Miller" , Jakub Kicinski Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, nobuhiro1.iwamatsu@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp Subject: [PATCH v2 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode Date: Wed, 19 Jan 2022 13:46:46 +0900 X-TSB-HOP: ON X-TSB-HOP2: ON Message-Id: <20220119044648.18094-1-yuji2.ishikawa@toshiba.co.jp> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, This series is a fix for RMII/MII operation mode of the dwmac-visconti driver. It is composed of two parts: * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode. Best regards, Yuji net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL v1 -> v2: - added Fixes tag to commit message net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode v1 -> v2: - added Fixes tag to commit message Yuji Ishikawa (2): net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode .../ethernet/stmicro/stmmac/dwmac-visconti.c | 42 ++++++++++++------- 1 file changed, 26 insertions(+), 16 deletions(-) -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5911C433EF for ; Wed, 19 Jan 2022 04:54:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=93I312CDsLDKulfOm53C1n18/PMOVE05tVJTwxLQLzg=; b=NXCgsanZ89jDk2 oGiftKUlaRhLMb1ybMVhMMZM/9iDHKdQtkGFQtA/IvRXMmVZVC3baAg7Lg4ov3jrqTZbSpTASeRxE l4NE2zKpmfHHn1ps9UwY5aDq2DYCu9TXigwwVaagZPb9ikZk5d887FudFDId1EchJXghAXyfQ5mng 2vA8Z7G8WU7kSTKcS8URHW/5cm9Kc0VCEmnWTV/+KSSKdpYS++fHh+gNgdNI+WbxNXD9L7JmTYhXz 3l4KnBHCgw8H0Bavh2D/bI+bcMIHHJnmZ+OuA8gsiMSSMIRwaw+QDER4Pb80yf6hcimUTrvuwVDQW 25lhsDjo3ZKnA0ncpmOQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nA2yO-003nQe-Bw; Wed, 19 Jan 2022 04:53:28 +0000 Received: from mo-csw1516.securemx.jp ([210.130.202.155] helo=mo-csw.securemx.jp) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nA2yL-003nPD-09 for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 04:53:26 +0000 Received: by mo-csw.securemx.jp (mx-mo-csw1516) id 20J4qDKk018584; Wed, 19 Jan 2022 13:52:14 +0900 X-Iguazu-Qid: 34trXZuAsxlohqpaPS X-Iguazu-QSIG: v=2; s=0; t=1642567933; q=34trXZuAsxlohqpaPS; m=0yidoEs59p9yDaB5qifBWEqQ4TxJweLoniwSrs5tqCI= Received: from imx12-a.toshiba.co.jp (imx12-a.toshiba.co.jp [61.202.160.135]) by relay.securemx.jp (mx-mr1513) id 20J4qBLp037215 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Wed, 19 Jan 2022 13:52:12 +0900 X-SA-MID: 31820870 From: Yuji Ishikawa To: "David S . Miller" , Jakub Kicinski Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, nobuhiro1.iwamatsu@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp Subject: [PATCH v2 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode Date: Wed, 19 Jan 2022 13:46:46 +0900 X-TSB-HOP: ON X-TSB-HOP2: ON Message-Id: <20220119044648.18094-1-yuji2.ishikawa@toshiba.co.jp> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220118_205325_276327_60680D6A X-CRM114-Status: UNSURE ( 6.88 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, This series is a fix for RMII/MII operation mode of the dwmac-visconti driver. It is composed of two parts: * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode. Best regards, Yuji net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL v1 -> v2: - added Fixes tag to commit message net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode v1 -> v2: - added Fixes tag to commit message Yuji Ishikawa (2): net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode .../ethernet/stmicro/stmmac/dwmac-visconti.c | 42 ++++++++++++------- 1 file changed, 26 insertions(+), 16 deletions(-) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel