From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29514C433F5 for ; Wed, 19 Jan 2022 15:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=i71pJuyFGIPvdOPvsgY2DmCEmneulyLkxsfI+3nVvLw=; b=AOnAYSCGTKvIWm 5fi2vSxTOPN65fYc8fcfouuw3dwuTt9Qb83zXCc6rge81tSwGBOBapi+3tCnWLHVBDFNmenh45rmu AJRmrcLdS8Wgfh/DIeDAJDTaBfzsMb22drFxwjkqplWOrNqTbSXWYDIpq6CDzZ7HhjO0JrYa2r5Vn ZODiL64jfw5f2z/n1ee/Hsu7KN8PtC1s7CJfuD4NPosOAF6cr/b4XFxZpnUxGlgVPbxD06rpzLv3B yPOhXS4BbiIzo4zFkc+37pqH/xfO+sBf5ubYe0vBgg8NUdY1cGTouswemEUh5B/G5Ft3YPC7ELyAw 0wxYYLlZ00pI6qHcUMEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nACn1-0067SJ-ST; Wed, 19 Jan 2022 15:22:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nACmy-0067QU-75 for linux-arm-kernel@lists.infradead.org; Wed, 19 Jan 2022 15:22:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8E0B4ED1; Wed, 19 Jan 2022 07:22:18 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.36.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BED33F774; Wed, 19 Jan 2022 07:22:17 -0800 (PST) Date: Wed, 19 Jan 2022 15:22:09 +0000 From: Mark Rutland To: Mark Brown Cc: Andre Przywara , linux-arm-kernel@lists.infradead.org, Jaxson.Han@arm.com, robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com Subject: Re: [bootwrapper PATCH v2 09/13] aarch64: move the bulk of EL3 initialization to C Message-ID: <20220119152209.GA43919@C02TD0UTHF1T.local> References: <20220114105653.3003399-1-mark.rutland@arm.com> <20220114105653.3003399-10-mark.rutland@arm.com> <20220117143104.28db5001@donnerap.cambridge.arm.com> <20220117180813.GD94025@C02TD0UTHF1T.local> <20220117183117.7f29dc66@donnerap.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220119_072220_344700_7EF9E44D X-CRM114-Status: GOOD ( 30.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jan 18, 2022 at 04:50:12PM +0000, Mark Brown wrote: > On Mon, Jan 17, 2022 at 06:31:17PM +0000, Andre Przywara wrote: > > Mark Rutland wrote: > > > On Mon, Jan 17, 2022 at 02:31:04PM +0000, Andre Przywara wrote: > > > > On Fri, 14 Jan 2022 10:56:49 +0000 > > > > Mark Rutland wrote: > > [Out of office this week so replies might be intermittent] > > > > > And apart from bit 0 missing from it (as noted above), the existing > > > > code writes 0x1ff into that register, presumable to cover future > > > > vector length extensions beyond 2048 bits (which those RAZ/WI fields > > > > in bits[8:4] seem to suggest). > > > > Hmm... I went and found the SVE supplement and I can't see any rationale > > > for what SW *should* do, nor can I find a description of the register > > > (that seems to have been factored into some XML files I can't convince > > > anything to load on my machine). > > ... > > > > TBH, I'm not sure. In the absence of some documented guidance I'd prefer > > > to go with 0xf, but given we already use 0x1ff, I want to dig into this > > > a bit more. > > I'm fairly sure I've seen some explicit discussion of this lurking > somewhere, though I couldn't tell you where - DDI0584 A.i doesn't spell > out the enumeration algorithm unfortunately AFAICT. The theory is that > the extra bits are reserved for any future extension of the vector > length if needed since it'd be inconvenient to have to split the vector > length field up. > > > My impression was that this "[8:4] = RAZ/WI" compared to the "[63:9] = > > RES0" fields suggests this is for a potential extension, but I guess there > > would be more changes needed if SVE ever goes beyond 2048. So chances are > > high we need to adopt the code then anyway, and fixing the number then is > > the least of our problems. > > > So I feel we should stick to what's explicitly documented, and put 0xf in > > there. > > We shouldn't need particularly many changes if the size of the field > ever gets raised, with everything being dynamically sized already and > the existing code starting off setting the WI bits to 1 the updates that > are needed should just be on input validation. Taking a look around, TF-A programs 0xf, and for consistency I think it'd be clearer to only program the currently-allocated LEN bits. I'll spin a preparatory patch reducing ZCR_EL3_LEN_MASK to 0xf (and renaming that to ZCR_EL3_LEN_MAX). If we need to grow it in future it should be trivial to do so. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel