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From: "Jorge Ramirez-Ortiz, Foundries" <jorge@foundries.io>
To: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Cc: "Jorge Ramirez-Ortiz, Foundries" <jorge@foundries.io>,
	michal.simek@xilinx.com, trini@konsulko.com, sjg@chromium.org,
	u-boot@lists.denx.de, ricardo@foundries.io, mike@foundries.io,
	igor.opaniuk@foundries.io
Subject: Re: FIT image: load secure FPGA
Date: Wed, 19 Jan 2022 17:44:22 +0100	[thread overview]
Message-ID: <20220119164422.GA1468952@trex> (raw)
In-Reply-To: <cc4cfdfc-e9c0-9228-65bb-f25157f6e491@fastree3d.com>

On 19/01/22, Adrian Fiergolski wrote:
> Hi Jorge,

hi Adrian,

> 
> Have you succeeded to enable secure boot on ZynqMP with SPL (not Xilinx's
> FSBL)? Is it documented somewhere? Any configuration files/yocto recipes?

somewhere there:
https://github.com/foundriesio/meta-lmp

> Have you managed to resolve problem of the bitstream loaded in such a case
> by SPL?
>

Yes. I wrote the docs here below:
https://docs.foundries.io/latest/reference-manual/security/authentication-xilinx.html


> I need to use an encrypted bitstream. However, it required the use of
> DeviceKeys in post-boot state which eventually requires secure boot.
> 
> Regards,

hope that helps

> 
> Adrian
> 

  reply	other threads:[~2022-01-19 16:44 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-04 20:32 FIT image: load secure FPGA Jorge Ramirez-Ortiz, Foundries
2021-10-04 20:54 ` Alex G.
2021-10-05  5:45   ` Jorge Ramirez-Ortiz, Foundries
2021-10-05  6:08     ` Jorge Ramirez-Ortiz, Foundries
2021-10-05 12:14       ` Michal Simek
2022-01-19 16:03 ` Adrian Fiergolski
2022-01-19 16:44   ` Jorge Ramirez-Ortiz, Foundries [this message]
2022-01-19 16:51     ` Jorge Ramirez-Ortiz, Foundries
2022-01-19 17:22       ` Jorge Ramirez-Ortiz, Foundries
2022-01-19 17:48         ` Oleksandr Suvorov
2022-02-07 12:24           ` Adrian Fiergolski
2022-02-09  7:51             ` Jorge Ramirez-Ortiz, Foundries
2022-02-09 12:20               ` Adrian Fiergolski

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