From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF38AC433F5 for ; Fri, 21 Jan 2022 02:22:14 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CBED4838FE; Fri, 21 Jan 2022 03:22:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="HaJcnRIe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8497583909; Fri, 21 Jan 2022 03:22:11 +0100 (CET) Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 36F73838FD for ; Fri, 21 Jan 2022 03:22:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=takahiro.akashi@linaro.org Received: by mail-pf1-x42a.google.com with SMTP id 192so4095233pfz.3 for ; Thu, 20 Jan 2022 18:22:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:mail-followup-to:references :mime-version:content-disposition:in-reply-to; bh=o6GuLIGoI/vSZkFY+6nIddihWbFUI0rrh7s3/Esfwgs=; b=HaJcnRIesf2uRNfwScvMLfG6hEdOrPwc4EFASFCvDHDlhkF9oZqjpHH0NJJk5k4/1c BK8gVZrheKJ+WlgnzKgBY6Ngf/52RBZ9vpQuMx+/bugCpRdfueobJTbqkI1Z0+cZ7Q4M fCynDQK4YdxGd752VL932OVvSI5J+mN6zpo//xEUzP/vFsYUTxFCDYVDkZjT8uTi/YTa HzJQ0y7m/LT7fggI2kmeKTxwmoiyEX4yzGRD1wJ0SK0DnXJf7CObmwI3hAjMnbB6nJPH xfc7U/j8DBUjFF/bL2hE3+rOvbsQUaa6N1pzL0Wuin6dZqPJ7SqJLOdWl4jjaxnKKcPO ixHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :in-reply-to; bh=o6GuLIGoI/vSZkFY+6nIddihWbFUI0rrh7s3/Esfwgs=; b=2LZSZKcAE5n17sckN5P5rM1d4TsuhdQBTw744iYSK6GYN8bShiDB7nvzzqOZP1qjcu 1vjmRIhiNAPGHpGUYWR9WbdijdL2CC03I4KVIiLZbQUbXGQDrY+S79SQOp+MRJREfq28 dPDYL5FlAThIwu+SmzXBVBHQV5tsaRa+LOhbjhjujgdH59SEOV/jjC2pjWF+9TQ8VxkA 0o7lqQSdjY7RzZW18GfJABEGsg3cabA1FT3Qny4ZlWllt8SIucI5yjXW6x4EB7Rm/3VW qoBDFiakFcCDtJqtgjICmTPWrmisuq6k0Dh8TY8pnHNKLSMAUTET5WpQgy5xF0z0vpF0 75XA== X-Gm-Message-State: AOAM533s2E2PjiFsV2gJBlF0p8OWwNJB7cxykdnSuWhsPL6rsbQ51hyV dzE/9aXnkz/0hEYtOyBZoBRBqg== X-Google-Smtp-Source: ABdhPJzVaXC26YDffLE+LBkYnt4EjRmfNqAw1IlFt26qTBVgZCLtuK6BZqavNzOqNfZtdiUeSiw9bQ== X-Received: by 2002:a05:6a00:2181:b0:4c1:3b84:b43f with SMTP id h1-20020a056a00218100b004c13b84b43fmr1967168pfi.50.1642731726551; Thu, 20 Jan 2022 18:22:06 -0800 (PST) Received: from laputa ([2400:4050:c3e1:100:9dfa:ef9c:130b:a92f]) by smtp.gmail.com with ESMTPSA id f12sm25836pfe.204.2022.01.20.18.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jan 2022 18:22:06 -0800 (PST) Date: Fri, 21 Jan 2022 11:22:01 +0900 From: AKASHI Takahiro To: Masami Hiramatsu Cc: u-boot@lists.denx.de, Patrick Delaunay , Patrice Chotard , Heinrich Schuchardt , Alexander Graf , Simon Glass , Bin Meng , Ilias Apalodimas , Jose Marinho , Grant Likely , Tom Rini , Etienne Carriere , Sughosh Ganu , Paul Liu Subject: Re: [RFC PATCH 12/14] FWU: synquacer: Add FWU Multi bank update support for DeveloperBox Message-ID: <20220121022201.GC44335@laputa> Mail-Followup-To: AKASHI Takahiro , Masami Hiramatsu , u-boot@lists.denx.de, Patrick Delaunay , Patrice Chotard , Heinrich Schuchardt , Alexander Graf , Simon Glass , Bin Meng , Ilias Apalodimas , Jose Marinho , Grant Likely , Tom Rini , Etienne Carriere , Sughosh Ganu , Paul Liu References: <164269255955.39378.260729958623102750.stgit@localhost> <164269268052.39378.8998928319603683374.stgit@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <164269268052.39378.8998928319603683374.stgit@localhost> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Fri, Jan 21, 2022 at 12:31:20AM +0900, Masami Hiramatsu wrote: > The DeveloperBox platform can support the FWU Multi bank > update. SCP firmware will switch the boot mode by DSW3-4 > and load the Multi bank update supported TF-A BL2 from > 0x600000 offset on the SPI flash. Thus it can co-exist > with the legacy boot mode (legacy U-Boot or EDK2). > > Signed-off-by: Masami Hiramatsu > --- > board/socionext/developerbox/Kconfig | 19 ++++ > board/socionext/developerbox/Makefile | 1 > board/socionext/developerbox/fwu_plat.c | 158 +++++++++++++++++++++++++++++++ > include/configs/synquacer.h | 10 ++ > include/efi_loader.h | 3 + > lib/efi_loader/efi_firmware.c | 14 +-- > 6 files changed, 198 insertions(+), 7 deletions(-) > create mode 100644 board/socionext/developerbox/fwu_plat.c > > diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig > index c181d26a44..4e2c341aad 100644 > --- a/board/socionext/developerbox/Kconfig > +++ b/board/socionext/developerbox/Kconfig > @@ -32,4 +32,23 @@ config SYS_CONFIG_NAME > default "synquacer" > > endif > + > +config FWU_MULTI_BANK_UPDATE > + select FWU_MULTI_BANK_UPDATE_SF > + > +config FWU_MULTI_BANK_UPDATE_SF > + select DM_SPI_FLASH > + > +config FWU_NUM_BANKS > + default 6 > + > +config FWU_NUM_IMAGES_PER_BANK > + default 1 > + > +config FWU_SF_PRIMARY_MDATA_OFFSET > + default 0x500000 > + > +config FWU_SF_SECONDARY_MDATA_OFFSET > + default 0x520000 Are those configs DeveloperBox-specific? -Takahiro Akashi > + > endif > diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile > index 4a46de995a..15cce9c57e 100644 > --- a/board/socionext/developerbox/Makefile > +++ b/board/socionext/developerbox/Makefile > @@ -7,3 +7,4 @@ > # > > obj-y := developerbox.o > +obj-$(CONFIG_FWU_MULTI_BANK_UPDATE_SF) += fwu_plat.o > diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c > new file mode 100644 > index 0000000000..dbb814f1fd > --- /dev/null > +++ b/board/socionext/developerbox/fwu_plat.c > @@ -0,0 +1,158 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2021, Linaro Limited > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +/* SPI Flash accessors */ > +static struct spi_flash *plat_spi_flash; > + > +static int __plat_sf_get_flash(void) > +{ > + struct udevice *new; > + int ret; > + > + //TODO: use CONFIG_FWU_SPI_* > + ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, > + CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, > + &new); > + if (ret) > + return ret; > + > + plat_spi_flash = dev_get_uclass_priv(new); > + return 0; > +} > + > +static int plat_sf_get_flash(struct spi_flash **flash) > +{ > + int ret = 0; > + > + if (!plat_spi_flash) > + ret = __plat_sf_get_flash(); > + > + *flash = plat_spi_flash; > + > + return ret; > +} > + > +static int sf_load_data(u32 offs, u32 size, void **data) > +{ > + struct spi_flash *flash; > + int ret; > + > + ret = plat_sf_get_flash(&flash); > + if (ret < 0) > + return ret; > + > + *data = memalign(ARCH_DMA_MINALIGN, size); > + if (!*data) > + return -ENOMEM; > + > + ret = spi_flash_read(flash, offs, size, *data); > + if (ret < 0) { > + free(*data); > + *data = NULL; > + } > + > + return ret; > +} > + > +/* Platform dependent GUIDs */ > + > +/* The GUID for the SNI FIP image type GUID */ > +#define FWU_IMAGE_TYPE_DEVBOX_FIP_GUID \ > + EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \ > + 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08) > + > +#define PLAT_METADATA_OFFSET 0x510000 > +#define PLAT_METADATA_SIZE (sizeof(struct devbox_metadata)) > + > +struct __packed devbox_metadata { > + u32 boot_index; > + u32 boot_count; > + u32 invert_dual; > +} *devbox_plat_metadata; > + > +static const efi_guid_t devbox_fip_image_type_guid = FWU_IMAGE_TYPE_DEVBOX_FIP_GUID; > + > +int fwu_plat_get_image_alt_num(efi_guid_t image_type_id, u32 update_bank, > + int *alt_no) > +{ > + /* DeveloperBox FWU Multi bank only supports FIP image. */ > + if (guidcmp(&image_type_id, &devbox_fip_image_type_guid)) > + return -EOPNOTSUPP; > + > + /* > + * DeveloperBox FWU expects Bank:Image = 1:1, and the dfu_alt_info > + * only has the entries for banks. Thus the alt_no should be equal > + * to the update_bank. > + */ > + update_bank %= CONFIG_FWU_NUM_BANKS; > + *alt_no = update_bank; > + > + return 0; > +} > + > +/* SPI flash doesn't have GPT, and it's not blk device */ > +int fwu_plat_fill_partition_guids(efi_guid_t **part_guid_arr) > +{ > + efi_status_t ret; > + > + free(*part_guid_arr); > + > + ret = efi_fill_part_guid_array(&devbox_fip_image_type_guid, part_guid_arr); > + return (ret != EFI_SUCCESS) ? -ENOMEM : 0; > +} > + > +/* TBD: add a usage counter for wear leveling */ > +int fwu_plat_get_update_index(u32 *update_idx) > +{ > + int ret; > + u32 active_idx; > + > + ret = fwu_get_active_index(&active_idx); > + > + if (ret < 0) > + return -1; > + > + *update_idx = (active_idx + 1) % CONFIG_FWU_NUM_BANKS; > + > + return ret; > +} > + > +static int devbox_load_plat_metadata(void) > +{ > + if (devbox_plat_metadata) > + return 0; > + > + return sf_load_data(PLAT_METADATA_OFFSET, PLAT_METADATA_SIZE, > + (void **)&devbox_plat_metadata); > +} > + > +void fwu_plat_get_bootidx(void *boot_idx) > +{ > + u32 *bootidx = boot_idx; > + > + if (devbox_load_plat_metadata() < 0) > + *bootidx = 0; > + else > + *bootidx = devbox_plat_metadata->boot_index; > +} > + > +struct fwu_mdata_ops *get_plat_fwu_mdata_ops(void) > +{ > + return fwu_sf_get_fwu_mdata_ops(); > +} > + > diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h > index 6d67bd2af5..f859237550 100644 > --- a/include/configs/synquacer.h > +++ b/include/configs/synquacer.h > @@ -47,8 +47,18 @@ > > /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ > > +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE > +#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ > + "mtd nor1=bank0 raw 600000 400000;" \ > + "bank1 raw a00000 400000;" \ > + "bank2 raw e00000 400000;" \ > + "bank3 raw 1200000 400000;" \ > + "bank4 raw 1600000 400000;" \ > + "bank5 raw 1a00000 400000\0" > +#else > #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ > "mtd nor1=fip.bin raw 600000 400000\0" > +#endif > > /* Distro boot settings */ > #ifndef CONFIG_SPL_BUILD > diff --git a/include/efi_loader.h b/include/efi_loader.h > index f20d361876..d6dc173feb 100644 > --- a/include/efi_loader.h > +++ b/include/efi_loader.h > @@ -953,6 +953,9 @@ void efi_memcpy_runtime(void *dest, const void *src, size_t n); > u16 *efi_create_indexed_name(u16 *buffer, size_t buffer_size, const char *name, > unsigned int index); > > +efi_status_t efi_fill_part_guid_array(const efi_guid_t *guid, > + efi_guid_t **part_guid_arr); > + > extern const struct efi_firmware_management_protocol efi_fmp_fit; > extern const struct efi_firmware_management_protocol efi_fmp_raw; > > diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c > index 107f0cb074..c100be35d3 100644 > --- a/lib/efi_loader/efi_firmware.c > +++ b/lib/efi_loader/efi_firmware.c > @@ -97,8 +97,8 @@ efi_status_t EFIAPI efi_firmware_set_package_info_unsupported( > return EFI_EXIT(EFI_UNSUPPORTED); > } > > -static efi_status_t fill_part_guid_array(const efi_guid_t *guid, > - efi_guid_t **part_guid_arr) > +efi_status_t efi_fill_part_guid_array(const efi_guid_t *guid, > + efi_guid_t **part_guid_arr) > { > int i; > int dfu_num = 0; > @@ -309,8 +309,8 @@ efi_status_t EFIAPI efi_firmware_fit_get_image_info( > !descriptor_size || !package_version || !package_version_name)) > return EFI_EXIT(EFI_INVALID_PARAMETER); > > - ret = fill_part_guid_array(&efi_firmware_image_type_uboot_fit, > - &part_guid_arr); > + ret = efi_fill_part_guid_array(&efi_firmware_image_type_uboot_fit, > + &part_guid_arr); > if (ret != EFI_SUCCESS) > goto out; > > @@ -429,7 +429,7 @@ efi_status_t EFIAPI efi_firmware_raw_get_image_info( > return EFI_EXIT(EFI_INVALID_PARAMETER); > > if (IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) { > - ret = fill_part_guid_array(&null_guid, &part_guid_arr); > + ret = efi_fill_part_guid_array(&null_guid, &part_guid_arr); > if (ret != EFI_SUCCESS) > goto out; > > @@ -444,8 +444,8 @@ efi_status_t EFIAPI efi_firmware_raw_get_image_info( > goto out; > } > } else { > - ret = fill_part_guid_array(&efi_firmware_image_type_uboot_raw, > - &part_guid_arr); > + ret = efi_fill_part_guid_array(&efi_firmware_image_type_uboot_raw, > + &part_guid_arr); > if (ret != EFI_SUCCESS) > goto out; > } >