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Date: Fri, 21 Jan 2022 14:27:22 +0100
From: Michal =?iso-8859-1?Q?Such=E1nek?= <msuchanek@suse.de>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: Re: [PATCH v7 1/7] powerpc/pmem: Restrict papr_scm to P8 and above.
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On Fri, Jan 21, 2022 at 02:48:32PM +0530, Aneesh Kumar K.V wrote:
> Michal Suchánek <msuchanek@suse.de> writes:
> 
> > Hello,
> >
> > On Wed, Jul 01, 2020 at 12:52:29PM +0530, Aneesh Kumar K.V wrote:
> >> The PAPR based virtualized persistent memory devices are only supported on
> >> POWER9 and above. In the followup patch, the kernel will switch the persistent
> >> memory cache flush functions to use a new `dcbf` variant instruction. The new
> >> instructions even though added in ISA 3.1 works even on P8 and P9 because these
> >> are implemented as a variant of existing `dcbf` and `hwsync` and on P8 and
> >> P9 behaves as such.
> >> 
> >> Considering these devices are only supported on P8 and above,  update the driver
> >> to prevent a P7-compat guest from using persistent memory devices.
> >> 
> >> We don't update of_pmem driver with the same condition, because, on bare-metal,
> >> the firmware enables pmem support only on P9 and above. There the kernel depends
> >> on OPAL firmware to restrict exposing persistent memory related device tree
> >> entries on older hardware. of_pmem.ko is written without any arch dependency and
> >> we don't want to add ppc64 specific cpu feature check in of_pmem driver.
> >> 
> >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> >> ---
> >>  arch/powerpc/platforms/pseries/pmem.c | 6 ++++++
> >>  1 file changed, 6 insertions(+)
> >> 
> >> diff --git a/arch/powerpc/platforms/pseries/pmem.c b/arch/powerpc/platforms/pseries/pmem.c
> >> index f860a897a9e0..2347e1038f58 100644
> >> --- a/arch/powerpc/platforms/pseries/pmem.c
> >> +++ b/arch/powerpc/platforms/pseries/pmem.c
> >> @@ -147,6 +147,12 @@ const struct of_device_id drc_pmem_match[] = {
> >>  
> >>  static int pseries_pmem_init(void)
> >>  {
> >> +	/*
> >> +	 * Only supported on POWER8 and above.
> >> +	 */
> >> +	if (!cpu_has_feature(CPU_FTR_ARCH_207S))
> >> +		return 0;
> >> +
> >
> > This looks superfluous.
> >
> > The hypervisor is responsible for publishing the pmem in devicetree when
> > present, kernel is responsible for using it when supported by the
> > kernel.
> >
> > Or is there a problem that the flush instruction is not available in P7
> > compat mode?
> 
> We want to avoid the usage of persistent memory on p7 compat mode
> because such a guest can LPM migrate to p7 systems. Now ideally I would
> expect hypervisor to avoid such migration, that is a p7 compat mode
> guest running on p10 using persistence memory migrating to p7
> (considering p7 never really had support for persistent memory).

Yes, I would expect the hypervisor to prevent migration to host that
does not have all the hardawre that the guest uses. It could still
migrate to P8 or whatever in compat mode.

> 
> There was also the complexity w.r.t what instructions the userspace will
> use. So it was discussed at that point that we could comfortably state
> and prevent the usage of persistent memory on p7 and below. 

But is that arbitrary or does POWER7 not support the pmem sync instructions?

If that is true then how is POWER7 compat mode behaving WRT those
instructions?

Thanks

Michal