From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 831ABC433F5 for ; Fri, 21 Jan 2022 16:36:19 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 12EC6820F0; Fri, 21 Jan 2022 17:36:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 20CED81109; Fri, 21 Jan 2022 17:36:16 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 94A22820F0 for ; Fri, 21 Jan 2022 17:36:12 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE377113E; Fri, 21 Jan 2022 08:36:11 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A00A63F73D; Fri, 21 Jan 2022 08:36:10 -0800 (PST) From: Andre Przywara To: Linus Walleij , Liviu Dudau Cc: Tom Rini , Simon Glass , Marek Vasut , Ross Burton , u-boot@lists.denx.de Subject: [PATCH] vexpress64: semi_defconfig: disable CRC32 support Date: Fri, 21 Jan 2022 16:36:04 +0000 Message-Id: <20220121163604.2503548-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Commit 270f8710f92f ("crc32: Add crc32 implementation using __builtin_aarch64_crc32b") enabled the usage of ARMv8 CRC instructions by default, for all arm64 builds. And indeed all Arm Ltd. v8 Cortex-A cores support the instructions, and they are mandatory starting with architecture revision v8.1, so realistically every known hardware implementation should support them. The Arm Fastmodel however defaults to the bare minimum ARMv8 feature set by default, which means v8.0 without the CRC instructions, so U-Boot hangs very early at the moment, without any output (the boot-wrapper or TF-A printing the last visible lines). Support for those instructions can be enabled on the model command line by either: -C cluster0.cpu0.enable_crc32=1 (for each core) or by using a higher architecture revision by default: -C cluster0.has_arm_v8-1=1 (for each cluster) Of course any arch revision higher than v8.1 would work as well. But for the sake of a smooth out-of-the-box experience, let's just disable the usage of those instructions in the defconfig, to avoid random hangs without any clues. Reported-by: Ross Burton Signed-off-by: Andre Przywara --- configs/vexpress_aemv8a_semi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index f9abf29b26..8e6a87c99f 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x90000000 +# CONFIG_ARM64_CRC32 is not set CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y -- 2.25.1