From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA3B0C4332F for ; Mon, 24 Jan 2022 12:21:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239572AbiAXMVq (ORCPT ); Mon, 24 Jan 2022 07:21:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239371AbiAXMVl (ORCPT ); Mon, 24 Jan 2022 07:21:41 -0500 Received: from mxd1.seznam.cz (mxd1.seznam.cz [IPv6:2a02:598:a::78:210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AC0CC061401; Mon, 24 Jan 2022 04:21:40 -0800 (PST) Received: from email.seznam.cz by email-smtpc13b.ko.seznam.cz (email-smtpc13b.ko.seznam.cz [10.53.14.135]) id 2667ca607d699e0927ce063e; Mon, 24 Jan 2022 13:21:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=beta; t=1643026881; bh=Ckw9HZumiyJ9/j0kzCkD0Q78VYDeksJ8NPzC60j675w=; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:X-szn-frgn: X-szn-frgc; b=Ql84f0eRQX2jJJuhT0PnEgKr7WR1/ldYnIPOX9I6doH1D9WRwEJ5VMyRNq7SQ6TWN 4tZmQ2H5JEUv08lXJefu9HvfeYTk4jvtxQ1ZHY+t7p8P3Uh2tKpKUdAsZmci2xTCSf cuRFXmRkXCcnCYPAGpzzfzrdUyptkATuDR4T/948= Received: from localhost.localdomain (ip-244-214.dynamic.ccinternet.cz [185.148.214.244]) by email-relay21.ko.seznam.cz (Seznam SMTPD 1.3.136) with ESMTP; Mon, 24 Jan 2022 13:21:16 +0100 (CET) From: michael.srba@seznam.cz To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Philipp Zabel Cc: Linus Walleij , Florian Fainelli , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Michael Srba Subject: [PATCH v3 2/5] clk: qcom: gcc-msm8998: add SSC-related clocks Date: Mon, 24 Jan 2022 13:18:50 +0100 Message-Id: <20220124121853.23600-2-michael.srba@seznam.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220124121853.23600-1-michael.srba@seznam.cz> References: <20220124121853.23600-1-michael.srba@seznam.cz> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-szn-frgn: X-szn-frgc: <0> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Michael Srba This patch adds four clocks which need to be manipulated in order to initialize the AHB bus which exposes the SCC block in the global address space. Care should be taken not to write to these registers unless the device is known to be configured such that writing to these registers from Linux is permitted. Signed-off-by: Michael Srba --- CHANGES: - v2: none - v3: none --- drivers/clk/qcom/gcc-msm8998.c | 56 ++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 407e2c5caea4..2d14c3d672fc 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -2833,6 +2833,58 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { }, }; +static struct clk_branch gcc_im_sleep_clk = { + .halt_reg = 0x4300C, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4300C, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_im_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch aggre2_snoc_north_axi_clk = { + .halt_reg = 0x83010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x83010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "aggre2_snoc_north_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ssc_xo_clk = { + .halt_reg = 0x63018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x63018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "ssc_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ssc_cnoc_ahbs_clk = { + .halt_reg = 0x6300C, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6300C, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "ssc_cnoc_ahbs_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, .gds_hw_ctrl = 0x0, @@ -3036,6 +3088,10 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, + [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr, + [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, + [SSC_XO] = &ssc_xo_clk.clkr, + [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { -- 2.34.1