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From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: danielhb413@gmail.com, richard.henderson@linaro.org,
	groug@kaod.org, Luis Pires <luis.pires@eldorado.org.br>,
	clg@kaod.org, Matheus Ferst <matheus.ferst@eldorado.org.br>,
	david@gibson.dropbear.id.au
Subject: [PATCH v2 01/38] target/ppc: Introduce TRANS*FLAGS macros
Date: Tue, 25 Jan 2022 09:19:06 -0300	[thread overview]
Message-ID: <20220125121943.3269077-2-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20220125121943.3269077-1-matheus.ferst@eldorado.org.br>

From: Luis Pires <luis.pires@eldorado.org.br>

New macros that add FLAGS and FLAGS2 checking were added for
both TRANS and TRANS64.

Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
[ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E
        - Use the new macros in load/store vector insns ]
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/translate.c              | 19 +++++++++++++++
 target/ppc/translate/vsx-impl.c.inc | 37 ++++++++++-------------------
 2 files changed, 31 insertions(+), 25 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9d2adc0cae..323bbd454d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7424,10 +7424,29 @@ static int times_16(DisasContext *ctx, int x)
 #define TRANS(NAME, FUNC, ...) \
     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
     { return FUNC(ctx, a, __VA_ARGS__); }
+#define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \
+    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+    {                                                          \
+        REQUIRE_INSNS_FLAGS(ctx, FLAGS);                       \
+        return FUNC(ctx, a, __VA_ARGS__);                      \
+    }
+#define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \
+    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+    {                                                          \
+        REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
+        return FUNC(ctx, a, __VA_ARGS__);                      \
+    }
 
 #define TRANS64(NAME, FUNC, ...) \
     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
     { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
+#define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \
+    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+    {                                                          \
+        REQUIRE_64BIT(ctx);                                    \
+        REQUIRE_INSNS_FLAGS2(ctx, FLAGS2);                     \
+        return FUNC(ctx, a, __VA_ARGS__);                      \
+    }
 
 /* TODO: More TRANS* helpers for extra insn_flags checks. */
 
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index c636e38164..b89be57272 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2070,12 +2070,6 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
 
 static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
 {
-    if (paired) {
-        REQUIRE_INSNS_FLAGS2(ctx, ISA310);
-    } else {
-        REQUIRE_INSNS_FLAGS2(ctx, ISA300);
-    }
-
     if (paired || a->rt >= 32) {
         REQUIRE_VSX(ctx);
     } else {
@@ -2089,7 +2083,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
                            bool store, bool paired)
 {
     arg_D d;
-    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
     REQUIRE_VSX(ctx);
 
     if (!resolve_PLS_D(ctx, &d, a)) {
@@ -2101,12 +2094,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
 
 static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
 {
-    if (paired) {
-        REQUIRE_INSNS_FLAGS2(ctx, ISA310);
-    } else {
-        REQUIRE_INSNS_FLAGS2(ctx, ISA300);
-    }
-
     if (paired || a->rt >= 32) {
         REQUIRE_VSX(ctx);
     } else {
@@ -2116,18 +2103,18 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
     return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
 }
 
-TRANS(STXV, do_lstxv_D, true, false)
-TRANS(LXV, do_lstxv_D, false, false)
-TRANS(STXVP, do_lstxv_D, true, true)
-TRANS(LXVP, do_lstxv_D, false, true)
-TRANS(STXVX, do_lstxv_X, true, false)
-TRANS(LXVX, do_lstxv_X, false, false)
-TRANS(STXVPX, do_lstxv_X, true, true)
-TRANS(LXVPX, do_lstxv_X, false, true)
-TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
-TRANS64(PLXV, do_lstxv_PLS_D, false, false)
-TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
-TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
+TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
+TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
+TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
+TRANS_FLAGS2(ISA310, LXVP, do_lstxv_D, false, true)
+TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false)
+TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false)
+TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
+TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
+TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
+TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
+TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
+TRANS64_FLAGS2(ISA310, PLXVP, do_lstxv_PLS_D, false, true)
 
 static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
                              TCGv_vec c)
-- 
2.25.1



  reply	other threads:[~2022-01-26  3:13 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-25 12:19 [PATCH v2 00/38] target/ppc: PowerISA Vector/VSX instruction batch matheus.ferst
2022-01-25 12:19 ` matheus.ferst [this message]
2022-01-25 12:19 ` [PATCH v2 02/38] target/ppc: moved vector even and odd multiplication to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 03/38] target/ppc: Moved vector multiply high and low " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 04/38] target/ppc: vmulh* instructions use gvec matheus.ferst
2022-01-25 12:19 ` [PATCH v2 05/38] target/ppc: Implement vmsumcud instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 06/38] target/ppc: Implement vmsumudm instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 07/38] target/ppc: Move vexts[bhw]2[wd] to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 08/38] target/ppc: Implement vextsd2q matheus.ferst
2022-01-25 12:19 ` [PATCH v2 09/38] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 10/38] target/ppc: Move Vector Compare Not Equal or Zero " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 11/38] target/ppc: Implement Vector Compare Equal Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 12/38] target/ppc: Implement Vector Compare Greater Than Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 13/38] target/ppc: Implement Vector Compare Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 14/38] target/ppc: implement vstri[bh][lr] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 15/38] target/ppc: implement vclrlb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 16/38] target/ppc: implement vclrrb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 17/38] target/ppc: implement vcntmb[bhwd] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 18/38] target/ppc: implement vgnb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 19/38] target/ppc: Move vsel and vperm/vpermr to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 20/38] target/ppc: Move xxsel " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 21/38] target/ppc: move xxperm/xxpermr " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 22/38] target/ppc: Move xxpermdi " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 23/38] target/ppc: Implement xxpermx instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 24/38] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i matheus.ferst
2022-01-25 12:19 ` [PATCH v2 25/38] target/ppc: Implement xxeval matheus.ferst
2022-01-25 12:19 ` [PATCH v2 26/38] target/ppc: Implement xxgenpcv[bhwd]m instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 27/38] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 28/38] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 29/38] target/ppc: Implement xvtlsbb instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 30/38] target/ppc: Remove xscmpnedp instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 31/38] target/ppc: Refactor VSX_SCALAR_CMP_DP matheus.ferst
2022-01-25 12:19 ` [PATCH v2 32/38] target/ppc: Implement xscmp{eq,ge,gt}qp matheus.ferst
2022-01-25 12:19 ` [PATCH v2 33/38] target/ppc: Implement do_helper_XX3 and move xxperm* to use it matheus.ferst
2022-01-25 12:19 ` [PATCH v2 34/38] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 35/38] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3 matheus.ferst
2022-01-25 12:19 ` [PATCH v2 36/38] target/ppc: Refactor VSX_MAX_MINC helper matheus.ferst
2022-01-25 12:19 ` [PATCH v2 37/38] target/ppc: Implement xs{max,min}cqp matheus.ferst
2022-01-25 12:19 ` [PATCH v2 38/38] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions matheus.ferst

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