From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAF80C3525A for ; Wed, 26 Jan 2022 02:06:07 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B36658365D; Wed, 26 Jan 2022 03:06:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 3EFFA81F6B; Wed, 26 Jan 2022 03:06:01 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 8453A837D7 for ; Wed, 26 Jan 2022 03:05:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 72FFA1FB; Tue, 25 Jan 2022 18:05:56 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A74BA3F7D8; Tue, 25 Jan 2022 18:05:53 -0800 (PST) Date: Wed, 26 Jan 2022 02:05:31 +0000 From: Andre Przywara To: Jesse Taube Cc: u-boot@lists.denx.de, jagan@amarulasolutions.com, hdegoede@redhat.com, sjg@chromium.org, icenowy@aosc.io, marek.behun@nic.cz, festevam@denx.de, narmstrong@baylibre.com, tharvey@gateworks.com, christianshewitt@gmail.com, pbrobinson@gmail.com, lokeshvutla@ti.com, jernej.skrabec@gmail.com, hs@denx.de, samuel@sholland.org, arnaud.ferraris@gmail.com, giulio.benetti@benettiengineering.com, thirtythreeforty@gmail.com Subject: Re: [PATCH 05/11] ARM: sunxi: Add support for F1C100s Message-ID: <20220126020511.1461e22c@slackpad.fritz.box> In-Reply-To: <20220105003508.1143140-6-Mr.Bossman075@gmail.com> References: <20220105003508.1143140-1-Mr.Bossman075@gmail.com> <20220105003508.1143140-6-Mr.Bossman075@gmail.com> Organization: Arm Ltd. X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Tue, 4 Jan 2022 19:35:02 -0500 Jesse Taube wrote: Hi, can you please change the subject, to maybe mention clocks? Reads rather generic as is. > From: Icenowy Zheng > > This patch aims to add header files for the F1C100s. > The header files included add support for gpio, dram and clocks. This looks to be about clocks and UARTs only? > > Signed-off-by: Icenowy Zheng > Signed-off-by: Jesse Taube > --- > arch/arm/include/asm/arch-sunxi/clock.h | 2 +- > arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 +++++++++++++++++++ > arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 ++++++ > arch/arm/include/asm/arch-sunxi/gpio.h | 1 + > 4 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h > index cbbe5c7a1e..2cfd540742 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock.h > +++ b/arch/arm/include/asm/arch-sunxi/clock.h > @@ -19,7 +19,7 @@ > #elif defined(CONFIG_SUN50I_GEN_H6) > #include > #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ > - defined(CONFIG_MACH_SUN50I) > + defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV) > #include > #elif defined(CONFIG_MACH_SUN9I) > #include > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > index ee387127f3..5ecdf58bd5 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > @@ -168,6 +168,14 @@ struct sunxi_ccm_reg { > u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */ > }; > > +/* apb1 bit field */ > +#ifdef CONFIG_MACH_SUNIV > +#define APB1_GATE_UART_SHIFT (20) > +#define APB1_GATE_UART_MASK (0x7 << APB1_GATE_UART_SHIFT) > +#define APB1_GATE_TWI_SHIFT (16) > +#define APB1_GATE_TWI_MASK (0x7 << APB1_GATE_TWI_SHIFT) The values match the user manual, but I don't see the *_MASK values used anywhere. Please just drop them. > +#endif > + > /* apb2 bit field */ > #define APB2_CLK_SRC_LOSC (0x0 << 24) > #define APB2_CLK_SRC_OSC24M (0x1 << 24) > @@ -226,7 +234,12 @@ struct sunxi_ccm_reg { > #define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) > #define CCM_PLL5_CTRL_EN (0x1 << 31) > > +#if !defined(CONFIG_MACH_SUNIV) > #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ > +#else > +/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */ > +#define PLL6_CFG_DEFAULT 0x90041800 The manual says that bit 0 resets to 1, as in the other SoCs. It just seems to affect the "back door clock output", so we should leave it as 1. > +#endif > > #define CCM_PLL6_CTRL_N_SHIFT 8 > #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) > @@ -310,6 +323,8 @@ struct sunxi_ccm_reg { > #define AHB_GATE_OFFSET_USB0 25 > #define AHB_GATE_OFFSET_SATA 24 > #endif > +#define AHB_GATE_OFFSET_SPI1 21 > +#define AHB_GATE_OFFSET_SPI0 20 I think this is legacy, we don't need this anymore with the DM clock driver we use in the SPI driver. The SPL SPI is separate anyway. Please just drop. > #define AHB_GATE_OFFSET_MCTL 14 > #define AHB_GATE_OFFSET_GMAC 17 > #define AHB_GATE_OFFSET_NAND0 13 > @@ -458,6 +473,8 @@ struct sunxi_ccm_reg { > #ifdef CONFIG_MACH_SUN8I_R40 > #define AHB_RESET_OFFSET_SATA 24 > #endif > +#define AHB_RESET_OFFSET_SPI1 21 > +#define AHB_RESET_OFFSET_SPI0 20 Same here, I don't see that used anywhere. > #define AHB_RESET_OFFSET_GMAC 17 > #define AHB_RESET_OFFSET_MCTL 14 > #define AHB_RESET_OFFSET_MMC3 11 > @@ -488,6 +505,14 @@ struct sunxi_ccm_reg { > #define AHB_RESET_OFFSET_EPHY 2 > #define AHB_RESET_OFFSET_LVDS 0 > > +/* apb1 reset */ > +#ifdef CONFIG_MACH_SUNIV > +#define APB1_RESET_UART_SHIFT (20) > +#define APB1_RESET_UART_MASK (0x7 << APB1_RESET_UART_SHIFT) > +#define APB1_RESET_TWI_SHIFT (16) > +#define APB1_RESET_TWI_MASK (0x7 << APB1_RESET_TWI_SHIFT) > +#endif > + > /* apb2 reset */ > #define APB2_RESET_UART_SHIFT (16) > #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h > index d4c795d89c..83178dd5c8 100644 > --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h > @@ -122,6 +122,12 @@ defined(CONFIG_MACH_SUN50I) > > #define SUNXI_SJTAG_BASE 0x01c23c00 > > +#ifdef CONFIG_MACH_SUNIV > +#define SUNXI_UART0_BASE 0x01c25000 > +#define SUNXI_UART1_BASE 0x01c25400 > +#define SUNXI_UART2_BASE 0x01c25800 > +#endif That should be moved down and merged into the other chunk below. Rest looks alright. Cheers, Andre > + > #define SUNXI_TP_BASE 0x01c25000 > #define SUNXI_PMU_BASE 0x01c25400 > > @@ -129,9 +135,11 @@ defined(CONFIG_MACH_SUN50I) > #define SUNXI_CPUCFG_BASE 0x01c25c00 > #endif > > +#ifndef CONFIG_MACH_SUNIV > #define SUNXI_UART0_BASE 0x01c28000 > #define SUNXI_UART1_BASE 0x01c28400 > #define SUNXI_UART2_BASE 0x01c28800 > +#endif > #define SUNXI_UART3_BASE 0x01c28c00 > #define SUNXI_UART4_BASE 0x01c29000 > #define SUNXI_UART5_BASE 0x01c29400 > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index f3ab1aea0e..ced69f7dd4 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -165,6 +165,7 @@ enum sunxi_gpio_number { > #define SUNXI_GPD_LVDS0 3 > #define SUNXI_GPD_PWM 2 > > +#define SUNIV_GPE_UART0 5 > #define SUN8I_GPE_TWI2 3 > #define SUN50I_GPE_TWI2 3 >