From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AAE1C5DF62 for ; Wed, 26 Jan 2022 12:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241306AbiAZM2y (ORCPT ); Wed, 26 Jan 2022 07:28:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241298AbiAZM2x (ORCPT ); Wed, 26 Jan 2022 07:28:53 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC78CC06161C; Wed, 26 Jan 2022 04:28:52 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 9CA58B81CE3; Wed, 26 Jan 2022 12:28:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEF30C340E3; Wed, 26 Jan 2022 12:28:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643200130; bh=9yhRa9yRgirMWQHOu0Sdi/mX+JUwRIAf1ljIpuG2t8s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GzhUYGtc+h1A7jRnxuW24Iq/W6ReRoIE+lOekp8jxETGGGvcO/z5jFsyovab437Z/ B5kBVttA7ePYviX7XdaNSEAnVjeShezZkD8WWwVzp+Y4j0xXQZuOJB5ZDhfg221q+n Vr2VvjXML5nB87wBqOGl27+p+3kM9UndBZ9/d/A6xpGErx0HRiBwooJjgNYzgDQRpf 02RQw8ZD0ufA5jZohp3rPaKxrMIa2PjrNb4b86KtoJyOhkpBHG2XQC5z49paeU6iH9 azRk/7eIepR6lxe+v2nqHODgdCHOjY0kd4dZTNSeF92SgZ9vVkmBuyV6nLcERG+wU2 IZx54Zk6BBi+w== Date: Wed, 26 Jan 2022 20:27:49 +0800 From: Shawn Guo To: Abel Vesa Cc: Rob Herring , Dong Aisheng , Sascha Hauer , Greg Kroah-Hartman , Fabio Estevam , Pengutronix Kernel Team , linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team , Linux Kernel Mailing List , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jacky Bai Subject: Re: [RESEND v4 02/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Message-ID: <20220126122748.GP4686@dragon> References: <1639680494-23183-1-git-send-email-abel.vesa@nxp.com> <1639680494-23183-3-git-send-email-abel.vesa@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1639680494-23183-3-git-send-email-abel.vesa@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Dec 16, 2021 at 08:48:06PM +0200, Abel Vesa wrote: > From: Jacky Bai > > The i.MX8DXL is a device targeting the automotive and industrial > market segments. The flexibility of the architecture allows for > use in a wide variety of general embedded applications. The chip > is designed to achieve both high performance and low power consumption. > The chip relies on the power efficient dual (2x) Cortex-A35 cluster. > > Add the reserved memory node property for dsp reserved memory, > the wakeup-irq property for SCU node, the imx ion, the rpmsg and the Not sure what "ion" is. > cm4 rproc support. > > Signed-off-by: Jacky Bai > Signed-off-by: Abel Vesa > --- > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 245 +++++++++++++++++++++ > 1 file changed, 245 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > new file mode 100644 > index 000000000000..f16f88882c39 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > @@ -0,0 +1,245 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019-2021 NXP > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + ethernet0 = &fec1; > + ethernet1 = &eqos; > + gpio0 = &lsio_gpio0; > + gpio1 = &lsio_gpio1; > + gpio2 = &lsio_gpio2; > + gpio3 = &lsio_gpio3; > + gpio4 = &lsio_gpio4; > + gpio5 = &lsio_gpio5; > + gpio6 = &lsio_gpio6; > + gpio7 = &lsio_gpio7; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + mu1 = &lsio_mu1; > + serial0 = &lpuart0; > + serial1 = &lpuart1; > + serial2 = &lpuart2; > + serial3 = &lpuart3; > + }; > + > + cpus: cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + /* We have 1 clusters with 2 Cortex-A35 cores */ s/clusters/cluster > + A35_0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > + #cooling-cells = <2>; > + operating-points-v2 = <&a35_opp_table>; > + }; > + > + A35_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > + #cooling-cells = <2>; > + operating-points-v2 = <&a35_opp_table>; > + }; > + > + A35_L2: l2-cache0 { > + compatible = "cache"; > + }; > + }; > + > + a35_opp_table: opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-900000000 { > + opp-hz = /bits/ 64 <900000000>; > + opp-microvolt = <1000000>; > + clock-latency-ns = <150000>; > + }; > + > + opp-1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > + opp-microvolt = <1100000>; > + clock-latency-ns = <150000>; > + opp-suspend; > + }; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + dsp_reserved: dsp@92400000 { > + reg = <0 0x92400000 0 0x2000000>; > + no-map; > + }; > + }; > + > + gic: interrupt-controller@51a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ > + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = ; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + scu { > + compatible = "fsl,imx-scu"; > + mbox-names = "tx0", > + "rx0", > + "gip3"; > + mboxes = <&lsio_mu1 0 0 > + &lsio_mu1 1 0 > + &lsio_mu1 3 3>; > + > + pd: imx8dxl-pd { > + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; > + #power-domain-cells = <1>; > + }; > + > + clk: clock-controller { > + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; > + #clock-cells = <2>; > + clocks = <&xtal32k &xtal24m>; > + clock-names = "xtal_32KHz", "xtal_24Mhz"; > + }; > + > + iomuxc: pinctrl { > + compatible = "fsl,imx8dxl-iomuxc"; > + }; > + > + ocotp: imx8qx-ocotp { > + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + fec_mac0: mac@2c4 { > + reg = <0x2c4 6>; > + }; > + > + fec_mac1: mac@2c6 { > + reg = <0x2c6 6>; > + }; > + }; > + > + watchdog { > + compatible = "fsl,imx-sc-wdt"; > + timeout-sec = <60>; > + }; > + > + tsens: thermal-sensor { > + compatible = "fsl,imx-sc-thermal"; > + #thermal-sensor-cells = <1>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , /* Physical Secure */ > + , /* Physical Non-Secure */ > + , /* Virtual */ > + ; /* Hypervisor */ > + }; > + > + thermal_zones: thermal-zones { > + cpu-thermal0 { > + polling-delay-passive = <250>; > + polling-delay = <2000>; > + thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; > + > + trips { > + cpu_alert0: trip0 { > + temperature = <107000>; > + hysteresis = <2000>; > + type = "passive"; > + }; Have a newline between nodes. > + cpu_crit0: trip1 { > + temperature = <127000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + cooling-maps { > + map0 { > + trip = <&cpu_alert0>; > + cooling-device = > + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + }; > + > + clk_dummy: clock-dummy { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + clock-output-names = "clk_dummy"; > + }; Why do we need this? Shawn > + > + xtal32k: clock-xtal32k { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "xtal_32KHz"; > + }; > + > + xtal24m: clock-xtal24m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xtal_24MHz"; > + }; > + > + sc_pwrkey: sc-powerkey { > + compatible = "fsl,imx8-pwrkey"; > + linux,keycode = ; > + wakeup-source; > + }; > + > + /* sorted in register address */ > + #include "imx8-ss-adma.dtsi" > + #include "imx8-ss-conn.dtsi" > + #include "imx8-ss-ddr.dtsi" > + #include "imx8-ss-lsio.dtsi" > +}; > + > +#include "imx8dxl-ss-adma.dtsi" > +#include "imx8dxl-ss-conn.dtsi" > +#include "imx8dxl-ss-lsio.dtsi" > +#include "imx8dxl-ss-ddr.dtsi" > -- > 2.31.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29ACAC28CF5 for ; Wed, 26 Jan 2022 12:30:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FBPVggtap3Bil69pLplCYqlkobXpeTJ8r56Fkb6zWyc=; b=i8/D/85xbkBmKK NhIIaa0tq8P5A8k8Ac+bEZHQ8v5NokFQy8HEvhGyrdSrY2T/dkmTNPh8fx3LKtTHZKfrHgZEe22f5 s6bYH4vMNZXmXgw7HZT6xhGS/suqDX1cVtkEr9d7H3M07rSvwGbkL30PSOpADWbOFF9vXwSPLnDHh nUKc+ZI6DThhImdBSzpvqWYf9vvQI6ce2mr6BuNkXfpBcGZ50OXH0z+4iosT2LtOZ2305S8NDRUcE XbAWm1x1IXPlkAwTKbsyHR0k6FTarB3N6xq1gYOuIF1G29FXWQ349d6JbZK/wtJpcB0je3x/Rt+XO MWZ2jcPoMkrpc2nCBrUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nChPy-00BhgK-Ro; Wed, 26 Jan 2022 12:28:55 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nChPv-00BhfB-7A for linux-arm-kernel@lists.infradead.org; Wed, 26 Jan 2022 12:28:53 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9CC43619F4; Wed, 26 Jan 2022 12:28:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEF30C340E3; Wed, 26 Jan 2022 12:28:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643200130; bh=9yhRa9yRgirMWQHOu0Sdi/mX+JUwRIAf1ljIpuG2t8s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GzhUYGtc+h1A7jRnxuW24Iq/W6ReRoIE+lOekp8jxETGGGvcO/z5jFsyovab437Z/ B5kBVttA7ePYviX7XdaNSEAnVjeShezZkD8WWwVzp+Y4j0xXQZuOJB5ZDhfg221q+n Vr2VvjXML5nB87wBqOGl27+p+3kM9UndBZ9/d/A6xpGErx0HRiBwooJjgNYzgDQRpf 02RQw8ZD0ufA5jZohp3rPaKxrMIa2PjrNb4b86KtoJyOhkpBHG2XQC5z49paeU6iH9 azRk/7eIepR6lxe+v2nqHODgdCHOjY0kd4dZTNSeF92SgZ9vVkmBuyV6nLcERG+wU2 IZx54Zk6BBi+w== Date: Wed, 26 Jan 2022 20:27:49 +0800 From: Shawn Guo To: Abel Vesa Cc: Rob Herring , Dong Aisheng , Sascha Hauer , Greg Kroah-Hartman , Fabio Estevam , Pengutronix Kernel Team , linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team , Linux Kernel Mailing List , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jacky Bai Subject: Re: [RESEND v4 02/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Message-ID: <20220126122748.GP4686@dragon> References: <1639680494-23183-1-git-send-email-abel.vesa@nxp.com> <1639680494-23183-3-git-send-email-abel.vesa@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1639680494-23183-3-git-send-email-abel.vesa@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_042851_383766_E536700C X-CRM114-Status: GOOD ( 25.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 16, 2021 at 08:48:06PM +0200, Abel Vesa wrote: > From: Jacky Bai > > The i.MX8DXL is a device targeting the automotive and industrial > market segments. The flexibility of the architecture allows for > use in a wide variety of general embedded applications. The chip > is designed to achieve both high performance and low power consumption. > The chip relies on the power efficient dual (2x) Cortex-A35 cluster. > > Add the reserved memory node property for dsp reserved memory, > the wakeup-irq property for SCU node, the imx ion, the rpmsg and the Not sure what "ion" is. > cm4 rproc support. > > Signed-off-by: Jacky Bai > Signed-off-by: Abel Vesa > --- > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 245 +++++++++++++++++++++ > 1 file changed, 245 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > new file mode 100644 > index 000000000000..f16f88882c39 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > @@ -0,0 +1,245 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019-2021 NXP > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + ethernet0 = &fec1; > + ethernet1 = &eqos; > + gpio0 = &lsio_gpio0; > + gpio1 = &lsio_gpio1; > + gpio2 = &lsio_gpio2; > + gpio3 = &lsio_gpio3; > + gpio4 = &lsio_gpio4; > + gpio5 = &lsio_gpio5; > + gpio6 = &lsio_gpio6; > + gpio7 = &lsio_gpio7; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + mu1 = &lsio_mu1; > + serial0 = &lpuart0; > + serial1 = &lpuart1; > + serial2 = &lpuart2; > + serial3 = &lpuart3; > + }; > + > + cpus: cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + /* We have 1 clusters with 2 Cortex-A35 cores */ s/clusters/cluster > + A35_0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > + #cooling-cells = <2>; > + operating-points-v2 = <&a35_opp_table>; > + }; > + > + A35_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + next-level-cache = <&A35_L2>; > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > + #cooling-cells = <2>; > + operating-points-v2 = <&a35_opp_table>; > + }; > + > + A35_L2: l2-cache0 { > + compatible = "cache"; > + }; > + }; > + > + a35_opp_table: opp-table { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-900000000 { > + opp-hz = /bits/ 64 <900000000>; > + opp-microvolt = <1000000>; > + clock-latency-ns = <150000>; > + }; > + > + opp-1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > + opp-microvolt = <1100000>; > + clock-latency-ns = <150000>; > + opp-suspend; > + }; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + dsp_reserved: dsp@92400000 { > + reg = <0 0x92400000 0 0x2000000>; > + no-map; > + }; > + }; > + > + gic: interrupt-controller@51a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ > + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = ; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + scu { > + compatible = "fsl,imx-scu"; > + mbox-names = "tx0", > + "rx0", > + "gip3"; > + mboxes = <&lsio_mu1 0 0 > + &lsio_mu1 1 0 > + &lsio_mu1 3 3>; > + > + pd: imx8dxl-pd { > + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; > + #power-domain-cells = <1>; > + }; > + > + clk: clock-controller { > + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; > + #clock-cells = <2>; > + clocks = <&xtal32k &xtal24m>; > + clock-names = "xtal_32KHz", "xtal_24Mhz"; > + }; > + > + iomuxc: pinctrl { > + compatible = "fsl,imx8dxl-iomuxc"; > + }; > + > + ocotp: imx8qx-ocotp { > + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + fec_mac0: mac@2c4 { > + reg = <0x2c4 6>; > + }; > + > + fec_mac1: mac@2c6 { > + reg = <0x2c6 6>; > + }; > + }; > + > + watchdog { > + compatible = "fsl,imx-sc-wdt"; > + timeout-sec = <60>; > + }; > + > + tsens: thermal-sensor { > + compatible = "fsl,imx-sc-thermal"; > + #thermal-sensor-cells = <1>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , /* Physical Secure */ > + , /* Physical Non-Secure */ > + , /* Virtual */ > + ; /* Hypervisor */ > + }; > + > + thermal_zones: thermal-zones { > + cpu-thermal0 { > + polling-delay-passive = <250>; > + polling-delay = <2000>; > + thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; > + > + trips { > + cpu_alert0: trip0 { > + temperature = <107000>; > + hysteresis = <2000>; > + type = "passive"; > + }; Have a newline between nodes. > + cpu_crit0: trip1 { > + temperature = <127000>; > + hysteresis = <2000>; > + type = "critical"; > + }; > + }; > + cooling-maps { > + map0 { > + trip = <&cpu_alert0>; > + cooling-device = > + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; > + }; > + > + clk_dummy: clock-dummy { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + clock-output-names = "clk_dummy"; > + }; Why do we need this? Shawn > + > + xtal32k: clock-xtal32k { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "xtal_32KHz"; > + }; > + > + xtal24m: clock-xtal24m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "xtal_24MHz"; > + }; > + > + sc_pwrkey: sc-powerkey { > + compatible = "fsl,imx8-pwrkey"; > + linux,keycode = ; > + wakeup-source; > + }; > + > + /* sorted in register address */ > + #include "imx8-ss-adma.dtsi" > + #include "imx8-ss-conn.dtsi" > + #include "imx8-ss-ddr.dtsi" > + #include "imx8-ss-lsio.dtsi" > +}; > + > +#include "imx8dxl-ss-adma.dtsi" > +#include "imx8dxl-ss-conn.dtsi" > +#include "imx8dxl-ss-lsio.dtsi" > +#include "imx8dxl-ss-ddr.dtsi" > -- > 2.31.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel