From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31B5DC433EF for ; Fri, 28 Jan 2022 22:43:06 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A134F837D2; Fri, 28 Jan 2022 23:43:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="k+fPsJcm"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9E753837E7; Fri, 28 Jan 2022 23:43:03 +0100 (CET) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id ACA73837B5 for ; Fri, 28 Jan 2022 23:43:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=alpernebiyasak@gmail.com Received: by mail-wm1-x32c.google.com with SMTP id c190-20020a1c9ac7000000b0035081bc722dso5005389wme.5 for ; Fri, 28 Jan 2022 14:43:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6HZDZxqgnPMjWGy7uVtl1C0hT+t1WmOGy8v7iLTH+dY=; b=k+fPsJcmFbUU/PXEn8tNkgUyzlRmpkDEXRPITxwcIdlImtbU/kv8Kl4Tl7pTDd8fUy QGaYloqF9Qb4l5/Rlv0J6OyPCS9dC1de6KwdXpu8+evr1ILG3ie35t4WvpDo66/MZRlo wj8g1faWOsh3og/9mhgccpMpMmb9xFAolz7pqDUfRyBoEk/4djnC6M7FNlWJX6ofSnF9 L6XE/xIz3zbI3OTFZNBO16f7u7h2odlOsD8Op9tJNRv3+DjBmSrNL9D0cyuQNKXogLcN pfhsNaAmStFGzsP3GmB3G6KzVeuvxFrUNRorY/2vVUZy5A/dL5NzqtePuxlnFTKrrpXq 7rZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=6HZDZxqgnPMjWGy7uVtl1C0hT+t1WmOGy8v7iLTH+dY=; b=61pPMThSJvGY/Wo2a7S4LF/Hbg95Lo7krUkrwSYZknySZFSK0DlHo3Zj4ZXbfDenfR yKoL9TYl8KPZkI/hdLD/BMZj+8cEx9kMIiGf60F1M0TDxlX7QtxWQRcHSwA4gI73rmLY mYsc/K/lBA1zD7iCAZcLwfMVmTIdTQk30IEpfGEs2yqU+XgA+yZbFgTyB8LcGYkG9z0w VwinCcD0A8J9Ro1/C1zHJ+WwlafV7eh5/TPA4i87Unp2JMClvHdrRuWq8acnYrwSR9l8 +QeMP1QTlebgaPu2QRgKCObLhw1Va9tW2gNyyb122ymMCQOVGCDUOvQJViRsa5ujOe2c usFA== X-Gm-Message-State: AOAM5307WLbWqIR7yD46uO7ZG4FZYsd/8JYeE1zAGLdq9Pwyrm/0rV0+ bJCvVtcVootKzTDsmKLzTkF6kPoC17oD3A== X-Google-Smtp-Source: ABdhPJxBKqK2YSzG3MBrtbNCIWjSrO6UNWyIMwHkhynPMo4tdymxVHS1St9KlOphsz5zCJ9jBODEJA== X-Received: by 2002:a1c:f015:: with SMTP id a21mr17809700wmb.101.1643409780140; Fri, 28 Jan 2022 14:43:00 -0800 (PST) Received: from localhost.localdomain ([178.233.26.119]) by smtp.gmail.com with ESMTPSA id m8sm5413586wrn.106.2022.01.28.14.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jan 2022 14:42:59 -0800 (PST) From: Alper Nebi Yasak To: u-boot@lists.denx.de Cc: Jack Mitchell , Kever Yang , Heinrich Schuchardt , Yifeng Zhao , Samuel Dionne-Riel , Simon Glass , Aswath Govindraju , Philipp Tomsich , Ashok Reddy Soma , Stephen Carlson , Jaehoon Chung , Michal Simek , Faiz Abbas , Jagan Teki , Peng Fan , Peter Robinson , Alper Nebi Yasak Subject: [PATCH v4 0/4] rockchip: sdhci: Fix reinit and add HS400 Enhanced Strobe support Date: Sat, 29 Jan 2022 01:42:35 +0300 Message-Id: <20220128224240.4226-1-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean My rk3399-gru-kevin has some problems with the eMMC. The board can boot to U-Boot proper with the eMMC working at a low speed, but trying to reinitialize it with "mmc dev 0" or "mmc rescan" makes it unusable. If the HS400 mode is enabled, it times out while executing tuning and doesn't even start at a working state. To work around these errors, I had implemented support for the HS400 Enhanced Strobe mode as the first version of this series. I have also managed the fix the issue above (related to power-cycling the eMMC PHY), which exposed another one with this series: reinitialization at lower speeds fail if the ES bit is set. Since fixing that needed changes to this series I decided to send the previous fix as part of this instead of as an independent patch. To test, I'm building with the following configs enabled: +CONFIG_MMC_SPEED_MODE_SET=y [...] CONFIG_MMC_PWRSEQ=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y and running roughly: $ mmc rescan [0|1|3|10|11|12] $ mmc info $ mmc part $ load mmc 0:1 0xd0000000 256MiB.bin $ load mmc 0:1 0xd0000000 16MiB.bin $ load mmc 0:1 0xd0000000 8MiB.bin I used to test by loading different sizes from a very big file (~7GiB), but that's slower than reading fixed-size files for some reason I don't know. I thought loading full files would be a better test so I switched to those. Here's the differences in info and speeds I get with this: Mode | Bus Speed | Bus Width -----------------------+--------------+-------------- MMC Legacy | 25000000 | 8-bit MMC High Speed (26MHz) | 26000000 | 8-bit MMC High Speed (52MHz) | 52000000 | 8-bit HS200 (200MHz) | 200000000 | 8-bit HS400 (200MHz) | 200000000 | 8-bit DDR HS400ES (200MHz) | 200000000 | 8-bit DDR Mode | 256 MiB Load | 16 MiB Load | 8 MiB Load -----------------------+--------------+--------------+-------------- MMC Legacy | ~22.1 MiB/s | ~21.9 MiB/s | ~21.6 MiB/s MMC High Speed (26MHz) | ~22.1 MiB/s | ~21.9 MiB/s | ~21.6 MiB/s MMC High Speed (52MHz) | ~43.7 MiB/s | ~42.8 MiB/s | ~41.7 MiB/s HS200 (200MHz) | ~161.2 MiB/s | ~149.5 MiB/s | ~137.9 MiB/s HS400 (200MHz) | ~254.5 MiB/s | ~235.3 MiB/s | ~216.2 MiB/s HS400ES (200MHz) | ~254.7 MiB/s | ~238.8 MiB/s | ~216.2 MiB/s Hope I haven't missed anything. Enabling the configs above for each board is left to board maintainers as I can't test on those boards. As an aside, I want to further clean up this driver when I have the time (it's a weird combination of what could be three different drivers), but wanted to send this as it at least gets the driver to a working state. Changes in v4: - Add comment for SDHCI set_enhanced_strobe() operation - Add comment for Rockchip SDHCI set_control_reg() driver data op - Add comment for Rockchip SDHCI set_ios_post() driver data op - Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op v3: https://patchwork.ozlabs.org/project/uboot/list/?series=281327&state=* Changes in v3: - Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init() v2: https://patchwork.ozlabs.org/project/uboot/list/?series=280494&state=* Changes in v2: - Add patch to fix PHY power cycling at higher speeds - Unset ES bit in rk3399 set_control_reg() to fix a reinit issue - Don't use unnecessary & for function pointer in ops struct - Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe - Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES - Rewrote cover letter v1: https://patchwork.ozlabs.org/project/uboot/list/?series=269768&state=* Alper Nebi Yasak (4): mmc: sdhci: Add HS400 Enhanced Strobe support rockchip: sdhci: Fix RK3399 eMMC PHY power cycling rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399 rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568 drivers/mmc/rockchip_sdhci.c | 171 +++++++++++++++++++++++++++++++++-- drivers/mmc/sdhci.c | 18 ++++ include/sdhci.h | 12 +++ 3 files changed, 191 insertions(+), 10 deletions(-) -- 2.34.1