Re: [PATCH 27/27] drm: rockchip: Add VOP2 driver

From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH 27/27] drm: rockchip: Add VOP2 driver
Date: Sat, 29 Jan 2022 18:55:45 +0800	[thread overview]
Message-ID: <202201291832.8LdxrySt-lkp@intel.com> (raw)
In-Reply-To: <20220126145549.617165-28-s.hauer@pengutronix.de>

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Hi Sascha,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next v5.17-rc1]
[cannot apply to rockchip/for-next drm-intel/for-linux-next airlied/drm-next next-20220128]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Sascha-Hauer/drm-rockchip-RK356x-VOP2-support/20220126-225854
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: openrisc-allmodconfig (https://download.01.org/0day-ci/archive/20220129/202201291832.8LdxrySt-lkp(a)intel.com/config)
compiler: or1k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/08336907e22eeb28385d746fc74e6f3850c9c838
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Sascha-Hauer/drm-rockchip-RK356x-VOP2-support/20220126-225854
        git checkout 08336907e22eeb28385d746fc74e6f3850c9c838
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=openrisc SHELL=/bin/bash drivers/gpu/drm/rockchip/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/rockchip/rockchip_drm_vop2.c: In function 'vop2_cluster_init':
>> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:2423:1: warning: the frame size of 1100 bytes is larger than 1024 bytes [-Wframe-larger-than=]
    2423 | };
         | ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop2.c: In function 'vop2_esmart_init':
   drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:2495:1: warning: the frame size of 1100 bytes is larger than 1024 bytes [-Wframe-larger-than=]
    2495 | };
         | ^

vim +2423 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

  2348	
  2349	static int vop2_cluster_init(struct vop2_win *win)
  2350	{
  2351		struct vop2 *vop2 = win->vop2;
  2352		int i;
  2353		struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
  2354			[VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
  2355			[VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
  2356			[VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
  2357			[VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
  2358			[VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
  2359			[VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
  2360			[VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
  2361			[VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
  2362			[VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
  2363			[VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
  2364			[VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15),
  2365			[VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31),
  2366			[VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
  2367			[VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
  2368			[VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
  2369	
  2370			/* Scale */
  2371			[VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
  2372			[VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31),
  2373			[VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15),
  2374			[VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13),
  2375			[VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3),
  2376			[VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28),
  2377			[VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29),
  2378	
  2379			/* cluster regs */
  2380			[VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1),
  2381			[VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0),
  2382			[VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7),
  2383	
  2384			/* afbc regs */
  2385			[VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6),
  2386			[VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9),
  2387			[VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10),
  2388			[VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4),
  2389			[VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7),
  2390			[VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8),
  2391			[VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31),
  2392			[VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31),
  2393			[VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15),
  2394			[VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
  2395			[VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
  2396			[VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
  2397			[VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
  2398			[VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
  2399			[VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
  2400			[VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
  2401			[VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3),
  2402			[VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff },
  2403			[VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff },
  2404			[VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff },
  2405			[VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff },
  2406			[VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff },
  2407			[VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
  2408			[VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
  2409			[VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff },
  2410			[VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
  2411			[VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff },
  2412			[VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
  2413			[VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff },
  2414			[VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff },
  2415		};
  2416	
  2417		for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++)
  2418			vop2_cluster_regs[i].reg += win->offset;
  2419	
  2420		return devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
  2421						    vop2_cluster_regs,
  2422						    ARRAY_SIZE(vop2_cluster_regs));
> 2423	};
  2424	

---
0-DAY CI Kernel Test Service, Intel Corporation
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