From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B684CC433EF for ; Sun, 30 Jan 2022 01:12:04 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 04ED68169D; Sun, 30 Jan 2022 02:12:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 638CA8192A; Sun, 30 Jan 2022 02:12:00 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 20D568129B for ; Sun, 30 Jan 2022 02:11:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5B04AED1; Sat, 29 Jan 2022 17:11:56 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B2ACA3F73B; Sat, 29 Jan 2022 17:11:54 -0800 (PST) Date: Sun, 30 Jan 2022 01:11:34 +0000 From: Andre Przywara To: Heinrich Schuchardt Cc: Samuel Holland , Andy Shevchenko , Icenowy Zheng , Jaehoon Chung , Jernej Skrabec , Peng Fan , Simon Glass , u-boot@lists.denx.de, Jagan Teki Subject: Re: [PATCH 2/4] sunxi: gpio: Add per-bank drive and pull setters Message-ID: <20220130011056.68fe7c0e@slackpad.fritz.box> In-Reply-To: References: <20211021045258.30757-1-samuel@sholland.org> <20211021045258.30757-3-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Fri, 5 Nov 2021 15:12:16 +0100 Heinrich Schuchardt wrote: > On 10/21/21 06:52, Samuel Holland wrote: > > The GPIO and pinctrl drivers need these setters for pin configuration. > > Since they are DM drivers, they should not be using hardcoded base > > addresses. Factor out variants of the setter functions which take a > > pointer to the GPIO bank's MMIO registers. > > > > Signed-off-by: Samuel Holland > > --- > > > > arch/arm/include/asm/arch-sunxi/gpio.h | 2 ++ > > arch/arm/mach-sunxi/pinmux.c | 20 ++++++++++++++++---- > > 2 files changed, 18 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > > index 2b72b2263b..106605adf5 100644 > > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > > @@ -227,7 +227,9 @@ void sunxi_gpio_set_cfgpin(u32 pin, u32 val); > > int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); > > int sunxi_gpio_get_cfgpin(u32 pin); > > void sunxi_gpio_set_drv(u32 pin, u32 val); > > Please, add Sphinx style documentation for the new functions, preferably > in the header file. Cf. > https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation I don't think this is necessary or useful, really. Those function are not really an advertised interface, more something we use internally, mostly for our SPL. > > +void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); > > void sunxi_gpio_set_pull(u32 pin, u32 val); > > +void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val); > > int sunxi_name_to_gpio(const char *name); > > > > #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO > > diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c > > index cf9d9daf7c..b2093b623a 100644 > > --- a/arch/arm/mach-sunxi/pinmux.c > > +++ b/arch/arm/mach-sunxi/pinmux.c > > @@ -48,19 +48,31 @@ int sunxi_gpio_get_cfgpin(u32 pin) > > void sunxi_gpio_set_drv(u32 pin, u32 val) > > { > > u32 bank = GPIO_BANK(pin); > > - u32 index = GPIO_DRV_INDEX(pin); > > - u32 offset = GPIO_DRV_OFFSET(pin); > > struct sunxi_gpio *pio = BANK_TO_GPIO(bank); > > > > + sunxi_gpio_set_drv_bank(pio, pin, val); > > +} > > + > > +void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) > > +{ > > + u32 index = GPIO_DRV_INDEX(bank_offset); > > + u32 offset = GPIO_DRV_OFFSET(bank_offset); > > + > > clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); > > } > > > > void sunxi_gpio_set_pull(u32 pin, u32 val) > > { > > u32 bank = GPIO_BANK(pin); > > - u32 index = GPIO_PULL_INDEX(pin); > > - u32 offset = GPIO_PULL_OFFSET(pin); > > struct sunxi_gpio *pio = BANK_TO_GPIO(bank); > > > > + sunxi_gpio_set_pull_bank(pio, pin, val); > > +} > > + > > +void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) > > +{ > > + u32 index = GPIO_PULL_INDEX(bank_offset); > > + u32 offset = GPIO_PULL_OFFSET(bank_offset); > > + > > clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); > > Please, simplify this: > %s/&pio->pull[0] + index/&pio->pull[index]/ Fixing this up locally. Cheers, Andre > > Otherwise the change looks correct to me. > > Best regards > > Heinrich > > > } > > >