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From: Fabiano Rosas <farosas@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org,
	david@gibson.dropbear.id.au
Subject: [PATCH 11/11] target/ppc: 6xx: Set SRRs directly in exception code
Date: Thu,  3 Feb 2022 17:09:57 -0300	[thread overview]
Message-ID: <20220203200957.1434641-12-farosas@linux.ibm.com> (raw)
In-Reply-To: <20220203200957.1434641-1-farosas@linux.ibm.com>

The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 80168355bd..7bdda6f165 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -554,7 +554,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
     target_ulong msr, new_msr, vector;
-    int srr0, srr1;
 
     if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -573,10 +572,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
      */
     new_msr = env->msr & ((target_ulong)1 << MSR_ME);
 
-    /* target registers */
-    srr0 = SPR_SRR0;
-    srr1 = SPR_SRR1;
-
     /*
      * Hypervisor emulation assistance interrupt only exists on server
      * arch 2.05 server or later.
@@ -727,10 +722,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
             cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
                       "no HV support\n", excp);
         }
-        if (srr0 == SPR_HSRR0) {
-            cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
-                      "no HV support\n", excp);
-        }
     }
 
     /*
@@ -742,10 +733,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
     }
 
     /* Save PC */
-    env->spr[srr0] = env->nip;
+    env->spr[SPR_SRR0] = env->nip;
 
     /* Save MSR */
-    env->spr[srr1] = msr;
+    env->spr[SPR_SRR1] = msr;
 
     powerpc_set_excp_state(cpu, vector, new_msr);
 }
-- 
2.34.1



  parent reply	other threads:[~2022-02-03 20:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
2022-02-03 20:09 ` [PATCH 01/11] target/ppc: Merge exception model IDs for 6xx CPUs Fabiano Rosas
2022-02-03 20:09 ` [PATCH 02/11] target/ppc: Introduce powerpc_excp_6xx Fabiano Rosas
2022-02-03 20:09 ` [PATCH 03/11] target/ppc: Simplify powerpc_excp_6xx Fabiano Rosas
2022-02-03 20:09 ` [PATCH 04/11] target/ppc: 6xx: Critical exception cleanup Fabiano Rosas
2022-02-04 12:43   ` BALATON Zoltan
2022-02-04 15:42     ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 05/11] target/ppc: 6xx: Machine Check " Fabiano Rosas
2022-02-03 20:09 ` [PATCH 06/11] target/ppc: 6xx: External interrupt cleanup Fabiano Rosas
2022-02-03 20:09 ` [PATCH 07/11] target/ppc: 6xx: Program exception cleanup Fabiano Rosas
2022-02-03 20:09 ` [PATCH 08/11] target/ppc: 6xx: System Call " Fabiano Rosas
2022-02-03 20:09 ` [PATCH 09/11] target/ppc: 6xx: System Reset interrupt cleanup Fabiano Rosas
2022-02-03 20:09 ` [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup Fabiano Rosas
2022-02-04 12:51   ` BALATON Zoltan
2022-02-04 15:46     ` Fabiano Rosas
2022-02-04 16:36       ` BALATON Zoltan
2022-02-03 20:09 ` Fabiano Rosas [this message]
2022-02-04  6:42 ` [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Cédric Le Goater
2022-02-04 15:50   ` Fabiano Rosas
2022-02-09  7:44 ` Cédric Le Goater

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