From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============3461051736270297382==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: Re: [RFC PATCH 3/6] drm: mxc-epdc: Add display and waveform initialisation Date: Sun, 06 Feb 2022 18:08:20 +0800 Message-ID: <202202061857.ZmlrNbez-lkp@intel.com> In-Reply-To: <20220206080016.796556-4-andreas@kemnade.info> List-Id: --===============3461051736270297382== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi Andreas, [FYI, it's a private test report for your RFC patch.] [auto build test WARNING on drm/drm-next] [also build test WARNING on robh/for-next v5.17-rc2 next-20220204] [cannot apply to pza/reset/next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Andreas-Kemnade/drm-EPDC-d= river-for-i-MX6/20220206-162244 base: git://anongit.freedesktop.org/drm/drm drm-next config: arc-allyesconfig (https://download.01.org/0day-ci/archive/20220206/= 202202061857.ZmlrNbez-lkp(a)intel.com/config) compiler: arceb-elf-gcc (GCC) 11.2.0 reproduce (this is a W=3D1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/= make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/e5b9ffe09a0668f81e87931ae= e2281dc7340d40b git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Andreas-Kemnade/drm-EPDC-driver-fo= r-i-MX6/20220206-162244 git checkout e5b9ffe09a0668f81e87931aee2281dc7340d40b # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=3D$HOME/0day COMPILER=3Dgcc-11.2.0 make.cross= O=3Dbuild_dir ARCH=3Darc SHELL=3D/bin/bash drivers/gpu/drm/mxc-epdc/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): >> drivers/gpu/drm/mxc-epdc/epdc_hw.c:174:6: warning: no previous prototype= for 'epdc_init_settings' [-Wmissing-prototypes] 174 | void epdc_init_settings(struct mxc_epdc *priv, struct drm_displa= y_mode *m) | ^~~~~~~~~~~~~~~~~~ -- >> drivers/gpu/drm/mxc-epdc/epdc_waveform.c:49:6: warning: no previous prot= otype for 'mxc_epdc_set_update_waveform' [-Wmissing-prototypes] 49 | void mxc_epdc_set_update_waveform(struct mxc_epdc *priv, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/mxc-epdc/epdc_waveform.c:77:5: warning: no previous prot= otype for 'mxc_epdc_fb_get_temp_index' [-Wmissing-prototypes] 77 | int mxc_epdc_fb_get_temp_index(struct mxc_epdc *priv, int temp) | ^~~~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/mxc-epdc/epdc_waveform.c:132:5: warning: no previous pro= totype for 'mxc_epdc_prepare_waveform' [-Wmissing-prototypes] 132 | int mxc_epdc_prepare_waveform(struct mxc_epdc *priv, | ^~~~~~~~~~~~~~~~~~~~~~~~~ vim +/epdc_init_settings +174 drivers/gpu/drm/mxc-epdc/epdc_hw.c 172 = 173 = > 174 void epdc_init_settings(struct mxc_epdc *priv, struct drm_display_mo= de *m) 175 { 176 u32 reg_val; 177 int num_ce; 178 int i; 179 = 180 /* Enable clocks to access EPDC regs */ 181 clk_prepare_enable(priv->epdc_clk_axi); 182 clk_prepare_enable(priv->epdc_clk_pix); 183 = 184 /* Reset */ 185 epdc_write(priv, EPDC_CTRL_SET, EPDC_CTRL_SFTRST); 186 while (!(epdc_read(priv, EPDC_CTRL) & EPDC_CTRL_CLKGATE)) 187 ; 188 epdc_write(priv, EPDC_CTRL_CLEAR, EPDC_CTRL_SFTRST); 189 = 190 /* Enable clock gating (clear to enable) */ 191 epdc_write(priv, EPDC_CTRL_CLEAR, EPDC_CTRL_CLKGATE); 192 while (epdc_read(priv, EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_C= LKGATE)) 193 ; 194 = 195 /* EPDC_CTRL */ 196 reg_val =3D epdc_read(priv, EPDC_CTRL); 197 reg_val &=3D ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK; 198 reg_val |=3D EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP; 199 reg_val &=3D ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK; 200 reg_val |=3D EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP; 201 epdc_write(priv, EPDC_CTRL_SET, reg_val); 202 = 203 /* EPDC_FORMAT - 2bit TFT and buf_pix_fmt Buf pixel format */ 204 reg_val =3D EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT 205 | priv->buf_pix_fmt 206 | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) & 207 EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK); 208 epdc_write(priv, EPDC_FORMAT, reg_val); 209 if (priv->rev >=3D 30) { 210 if (priv->buf_pix_fmt =3D=3D EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N) { 211 epdc_write(priv, EPDC_WB_FIELD2, 0xc554); 212 epdc_write(priv, EPDC_WB_FIELD1, 0xa004); 213 } else { 214 epdc_write(priv, EPDC_WB_FIELD2, 0xc443); 215 epdc_write(priv, EPDC_WB_FIELD1, 0xa003); 216 } 217 } 218 = 219 /* EPDC_FIFOCTRL (disabled) */ 220 reg_val =3D 221 ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) & 222 EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK) 223 | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) & 224 EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK) 225 | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) & 226 EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK); 227 epdc_write(priv, EPDC_FIFOCTRL, reg_val); 228 = 229 /* EPDC_TEMP - Use default temp to get index */ 230 epdc_write(priv, EPDC_TEMP, 231 mxc_epdc_fb_get_temp_index(priv, TEMP_USE_AMBIENT)); 232 = 233 /* EPDC_RES */ 234 epdc_set_screen_res(priv, m->hdisplay, m->vdisplay); 235 = 236 /* EPDC_AUTOWV_LUT */ 237 /* Initialize all auto-wavefrom look-up values to 2 - GC16 */ 238 for (i =3D 0; i < 8; i++) 239 epdc_write(priv, EPDC_AUTOWV_LUT, 240 (2 << EPDC_AUTOWV_LUT_DATA_OFFSET) | 241 (i << EPDC_AUTOWV_LUT_ADDR_OFFSET)); 242 = 243 /* 244 * EPDC_TCE_CTRL 245 * VSCAN_HOLDOFF =3D 4 246 * VCOM_MODE =3D MANUAL 247 * VCOM_VAL =3D 0 248 * DDR_MODE =3D DISABLED 249 * LVDS_MODE_CE =3D DISABLED 250 * LVDS_MODE =3D DISABLED 251 * DUAL_SCAN =3D DISABLED 252 * SDDO_WIDTH =3D 8bit 253 * PIXELS_PER_SDCLK =3D 4 254 */ 255 reg_val =3D 256 ((priv->imx_mode.vscan_holdoff << EPDC_TCE_CTRL_VSCAN_HOLDOFF_O= FFSET) & 257 EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK) 258 | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4; 259 epdc_write(priv, EPDC_TCE_CTRL, reg_val); 260 = 261 /* EPDC_TCE_HSCAN */ 262 epdc_set_horizontal_timing(priv, m->hsync_start - m->hdisplay, 263 m->htotal - m->hsync_end, 264 m->hsync_end - m->hsync_start, 265 m->hsync_end - m->hsync_start); 266 = 267 /* EPDC_TCE_VSCAN */ 268 epdc_set_vertical_timing(priv, m->vsync_start - m->vdisplay, 269 m->vtotal - m->vsync_end, 270 m->vsync_end - m->vsync_start); 271 = 272 /* EPDC_TCE_OE */ 273 reg_val =3D 274 ((priv->imx_mode.sdoed_width << EPDC_TCE_OE_SDOED_WIDTH_OFFSET)= & 275 EPDC_TCE_OE_SDOED_WIDTH_MASK) 276 | ((priv->imx_mode.sdoed_delay << EPDC_TCE_OE_SDOED_DLY_OFFSET)= & 277 EPDC_TCE_OE_SDOED_DLY_MASK) 278 | ((priv->imx_mode.sdoez_width << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSE= T) & 279 EPDC_TCE_OE_SDOEZ_WIDTH_MASK) 280 | ((priv->imx_mode.sdoez_delay << EPDC_TCE_OE_SDOEZ_DLY_OFFSET)= & 281 EPDC_TCE_OE_SDOEZ_DLY_MASK); 282 epdc_write(priv, EPDC_TCE_OE, reg_val); 283 = 284 /* EPDC_TCE_TIMING1 */ 285 epdc_write(priv, EPDC_TCE_TIMING1, 0x0); 286 = 287 /* EPDC_TCE_TIMING2 */ 288 reg_val =3D 289 ((priv->imx_mode.gdclk_hp_offs << EPDC_TCE_TIMING2_GDCLK_HP_OFF= SET) & 290 EPDC_TCE_TIMING2_GDCLK_HP_MASK) 291 | ((priv->imx_mode.gdsp_offs << EPDC_TCE_TIMING2_GDSP_OFFSET_OF= FSET) & 292 EPDC_TCE_TIMING2_GDSP_OFFSET_MASK); 293 epdc_write(priv, EPDC_TCE_TIMING2, reg_val); 294 = 295 /* EPDC_TCE_TIMING3 */ 296 reg_val =3D 297 ((priv->imx_mode.gdoe_offs << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFS= ET) & 298 EPDC_TCE_TIMING3_GDOE_OFFSET_MASK) 299 | ((priv->imx_mode.gdclk_offs << EPDC_TCE_TIMING3_GDCLK_OFFSET_= OFFSET) & 300 EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK); 301 epdc_write(priv, EPDC_TCE_TIMING3, reg_val); 302 = 303 /* 304 * EPDC_TCE_SDCFG 305 * SDCLK_HOLD =3D 1 306 * SDSHR =3D 1 307 * NUM_CE =3D 1 308 * SDDO_REFORMAT =3D FLIP_PIXELS 309 * SDDO_INVERT =3D DISABLED 310 * PIXELS_PER_CE =3D display horizontal resolution 311 */ 312 num_ce =3D priv->imx_mode.num_ce; 313 if (num_ce =3D=3D 0) 314 num_ce =3D 1; 315 reg_val =3D EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR 316 | ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & 317 EPDC_TCE_SDCFG_NUM_CE_MASK) 318 | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS 319 | ((priv->epdc_mem_width/num_ce << EPDC_TCE_SDCFG_PIXELS_PER_CE= _OFFSET) & 320 EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK); 321 epdc_write(priv, EPDC_TCE_SDCFG, reg_val); 322 = 323 /* 324 * EPDC_TCE_GDCFG 325 * GDRL =3D 1 326 * GDOE_MODE =3D 0; 327 * GDSP_MODE =3D 0; 328 */ 329 reg_val =3D EPDC_TCE_SDCFG_GDRL; 330 epdc_write(priv, EPDC_TCE_GDCFG, reg_val); 331 = 332 /* 333 * EPDC_TCE_POLARITY 334 * SDCE_POL =3D ACTIVE LOW 335 * SDLE_POL =3D ACTIVE HIGH 336 * SDOE_POL =3D ACTIVE HIGH 337 * GDOE_POL =3D ACTIVE HIGH 338 * GDSP_POL =3D ACTIVE LOW 339 */ 340 reg_val =3D EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH 341 | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH 342 | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH; 343 epdc_write(priv, EPDC_TCE_POLARITY, reg_val); 344 = 345 /* EPDC_IRQ_MASK */ 346 epdc_write(priv, EPDC_IRQ_MASK, EPDC_IRQ_TCE_UNDERRUN_IRQ); 347 = 348 /* 349 * EPDC_GPIO 350 * PWRCOM =3D ? 351 * PWRCTRL =3D ? 352 * BDR =3D ? 353 */ 354 reg_val =3D ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MA= SK) 355 | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK); 356 epdc_write(priv, EPDC_GPIO, reg_val); 357 = 358 epdc_write(priv, EPDC_WVADDR, priv->waveform_buffer_phys); 359 epdc_write(priv, EPDC_WB_ADDR, priv->working_buffer_phys); 360 if (priv->rev >=3D 30) 361 epdc_write(priv, EPDC_WB_ADDR_TCE_V3, 362 priv->working_buffer_phys); 363 else 364 epdc_write(priv, EPDC_WB_ADDR_TCE, 365 priv->working_buffer_phys); 366 = 367 /* Disable clock */ 368 clk_disable_unprepare(priv->epdc_clk_axi); 369 clk_disable_unprepare(priv->epdc_clk_pix); 370 } 371 = --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org --===============3461051736270297382==--