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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id s17sm19987467pfk.156.2022.02.09.13.56.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 13:56:37 -0800 (PST) To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 13/15] hw/mips: Restrict MIPSCPU type to target/ code Date: Wed, 9 Feb 2022 22:54:44 +0100 Message-Id: <20220209215446.58402-14-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209215446.58402-1-f4bug@amsat.org> References: <20220209215446.58402-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= via Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/cpudevs.h | 6 ++---- target/mips/cpu-qom.h | 2 -- target/mips/cpu.h | 4 ++-- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h index f7c9728fa9..6065932b0e 100644 --- a/include/hw/mips/cpudevs.h +++ b/include/hw/mips/cpudevs.h @@ -1,14 +1,12 @@ #ifndef HW_MIPS_CPUDEVS_H #define HW_MIPS_CPUDEVS_H -#include "target/mips/cpu-qom.h" - /* Definitions for MIPS CPU internal devices. */ /* mips_int.c */ -void cpu_mips_irq_init_cpu(MIPSCPU *cpu); +void cpu_mips_irq_init_cpu(ArchCPU *cpu); /* mips_timer.c */ -void cpu_mips_clock_init(MIPSCPU *cpu); +void cpu_mips_clock_init(ArchCPU *cpu); #endif diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 41f3d01a80..666084b09e 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -29,8 +29,6 @@ #define TYPE_MIPS_CPU "mips-cpu" #endif -typedef struct ArchCPU MIPSCPU; - OBJECT_DECLARE_TYPE(ArchCPU, MIPSCPUClass, MIPS_CPU) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 09e98f64de..4aa95d0ce1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1171,7 +1171,7 @@ typedef struct CPUArchState { * * A MIPS CPU. */ -struct ArchCPU { +typedef struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -1187,7 +1187,7 @@ struct ArchCPU { * pipeline clock of the processor, not the issue width of the processor. */ unsigned cp0_count_rate; -}; +} MIPSCPU; void mips_cpu_list(void); -- 2.34.1