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From: Chuansheng Liu <chuansheng.liu@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: lucas.demarchi@intel.com
Subject: [Intel-gfx] [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register
Date: Thu, 10 Feb 2022 13:05:01 +0800	[thread overview]
Message-ID: <20220210050501.87795-1-chuansheng.liu@intel.com> (raw)

Current DMC_DEBUG3(_MMIO(0x101090)) address is for TGL,
it is not wrong for DG1. Just like commit 5bcc95ca382e
("drm/i915/dg1: Update DMC_DEBUG register"), correct
this issue for DG1 platform to avoid wrong register
being read.

BSpec: 49788

Signed-off-by: Chuansheng Liu <chuansheng.liu@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h                      | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f4de004d470f..f6c4ad8fce19 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -474,8 +474,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		 * reg for DC3CO debugging and validation,
 		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
 		 */
-		seq_printf(m, "DC3CO count: %d\n",
-			   intel_de_read(dev_priv, DMC_DEBUG3));
+		seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv, IS_DGFX(dev_priv) ?
+					DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
 	} else {
 		dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
 						 SKL_DMC_DC3_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c92314ee26..9c215a6df659 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5632,7 +5632,8 @@
 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
 #define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
 
-#define DMC_DEBUG3		_MMIO(0x101090)
+#define TGL_DMC_DEBUG3		_MMIO(0x101090)
+#define DG1_DMC_DEBUG3		_MMIO(0x13415c)
 
 /* Display Internal Timeout Register */
 #define RM_TIMEOUT		_MMIO(0x42060)
-- 
2.25.0.rc2


             reply	other threads:[~2022-02-10  5:18 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-10  5:05 Chuansheng Liu [this message]
2022-02-10  5:27 ` [Intel-gfx] [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register Matt Roper
2022-02-10  5:36   ` Liu, Chuansheng
2022-02-10  5:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-02-10  5:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-10  7:10 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-15  5:15   ` Matt Roper
2022-02-22 17:39     ` Vudum, Lakshminarayana
2022-02-10 10:50 ` [Intel-gfx] [PATCH] " Jani Nikula
2022-02-10 16:44 Anusha Srivatsa
2022-02-10 17:37 ` Tvrtko Ursulin
2022-02-10 18:51 ` Matt Roper
2022-02-10 19:15   ` Srivatsa, Anusha

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