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Wed, 9 Feb 2022 22:51:16 -0800 From: Mohan Kumar To: , , , , , , CC: , , , , Mohan Kumar Subject: [PATCH v2 4/6] dt-bindings: Add HDA support for Tegra234 Date: Thu, 10 Feb 2022 12:20:55 +0530 Message-ID: <20220210065057.13555-5-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220210065057.13555-1-mkumard@nvidia.com> References: <20220210065057.13555-1-mkumard@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c6150b75-a42b-49f6-39ac-08d9ec61bef5 X-MS-TrafficTypeDiagnostic: MW3PR12MB4409:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Uv8bbeCj9my/xAI6L/l0JZSZd4fYS1hX7APN6EQtxSSdeAJkFtxDFX7g8J5q3G/5HgDNh8XuEL7y1T/EJQcsICJIWtLMh+WWxBFN5Zt9igTQSPui/YtAPNIpvahgP/p9ExTKtu+PqVYlNr0ZkM/8dJRY1i+QBKzliuFQAinwb6v6+Cj0R9hMzo3Yi79JLv2icOpOsUB3n2ytIsBSwHUnVZ5rrCyLfevnYJKk5KjJwUqPJ3Frnl1u7RyOmSiVbZ+3HKwkdlpUNVRQFqFzvnXTBrBxeMNgf7F044fHaQvlFblSR3pJZztkgVt/a5oQLa65ibD1iD4ZWcYDmKbZPBZgFnYhdyY1iJ6HoYi3OOigIyjB2mFYxdpuvZ9aMTIdig+o2CmzOSAogY3NExGXXu9azsnyPvQrdqTGUu+VrLm6nF5EswUOkU1pKspMIA+f/hd7RzvO82lrM00QSaGnUppL/adaTKbiU3CljZowwE0L2XTMjOpdRgUL/P3eG82JY8w4or6mweXotFiJSdHEJnJ82MefbqvBXElq4javqhD0jJhsnDslCqbnpLtWlp8dUGo90aShuGbJVQSzYtfT9IdghkhXhEBuTtOYpLVNRI8vPYnfm87duVOwcTa99t5OacDHcyj5a1d8buDU4+vZlm9Gr45vBzDchoXlQR0Y6BqJvONUMTyj4Ef5kWtpbs8Y+QVIpQ8MyK2QxypeCIneFEML+gWnTV4ZWZKz3CXp8sLdxks= X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(2616005)(1076003)(426003)(336012)(186003)(26005)(107886003)(36756003)(8936002)(70586007)(4326008)(54906003)(6636002)(316002)(8676002)(70206006)(110136005)(7696005)(2906002)(508600001)(6666004)(82310400004)(40460700003)(5660300002)(356005)(83380400001)(81166007)(36860700001)(47076005)(86362001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2022 06:51:20.8267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6150b75-a42b-49f6-39ac-08d9ec61bef5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4409 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add hda clocks, memory ,power and reset binding entries for Tegra234. Signed-off-by: Mohan Kumar --- include/dt-bindings/clock/tegra234-clock.h | 4 ++++ include/dt-bindings/memory/tegra234-mc.h | 6 ++++++ include/dt-bindings/power/tegra234-powergate.h | 9 +++++++++ include/dt-bindings/reset/tegra234-reset.h | 2 ++ 4 files changed, 21 insertions(+) create mode 100644 include/dt-bindings/power/tegra234-powergate.h diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e1b6ef..c014269b7245 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -30,5 +30,9 @@ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ +#define TEGRA234_CLK_AZA_2XBIT 457U +/** @brief aza_2xbitclk / 2 (aza_bitclk) */ +#define TEGRA234_CLK_AZA_BIT 458U #endif diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 2662f70c15c6..f538fc442cee 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -7,6 +7,8 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f +/* NISO0 SMMU STREAM IDs */ +#define TEGRA234_SID_NISO0_HDA 0x03 /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 @@ -16,6 +18,10 @@ * memory client IDs */ +/* High-definition audio (HDA) read clients */ +#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +/* High-definition audio (HDA) write clients */ +#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h new file mode 100644 index 000000000000..3c5575a51296 --- /dev/null +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T234_POWERGATE_T234_H_ +#define __ABI_MACH_T234_POWERGATE_T234_H_ + +#define TEGRA234_POWER_DOMAIN_DISP 3U + +#endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bced642..2ab61c69a3d9 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -10,6 +10,8 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ +#define TEGRA234_RESET_HDA 20U +#define TEGRA234_RESET_HDACODEC 21U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4654C433EF for ; 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Wed, 9 Feb 2022 22:51:16 -0800 From: Mohan Kumar To: , , , , , , Subject: [PATCH v2 4/6] dt-bindings: Add HDA support for Tegra234 Date: Thu, 10 Feb 2022 12:20:55 +0530 Message-ID: <20220210065057.13555-5-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220210065057.13555-1-mkumard@nvidia.com> References: <20220210065057.13555-1-mkumard@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c6150b75-a42b-49f6-39ac-08d9ec61bef5 X-MS-TrafficTypeDiagnostic: MW3PR12MB4409:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1079; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Uv8bbeCj9my/xAI6L/l0JZSZd4fYS1hX7APN6EQtxSSdeAJkFtxDFX7g8J5q3G/5HgDNh8XuEL7y1T/EJQcsICJIWtLMh+WWxBFN5Zt9igTQSPui/YtAPNIpvahgP/p9ExTKtu+PqVYlNr0ZkM/8dJRY1i+QBKzliuFQAinwb6v6+Cj0R9hMzo3Yi79JLv2icOpOsUB3n2ytIsBSwHUnVZ5rrCyLfevnYJKk5KjJwUqPJ3Frnl1u7RyOmSiVbZ+3HKwkdlpUNVRQFqFzvnXTBrBxeMNgf7F044fHaQvlFblSR3pJZztkgVt/a5oQLa65ibD1iD4ZWcYDmKbZPBZgFnYhdyY1iJ6HoYi3OOigIyjB2mFYxdpuvZ9aMTIdig+o2CmzOSAogY3NExGXXu9azsnyPvQrdqTGUu+VrLm6nF5EswUOkU1pKspMIA+f/hd7RzvO82lrM00QSaGnUppL/adaTKbiU3CljZowwE0L2XTMjOpdRgUL/P3eG82JY8w4or6mweXotFiJSdHEJnJ82MefbqvBXElq4javqhD0jJhsnDslCqbnpLtWlp8dUGo90aShuGbJVQSzYtfT9IdghkhXhEBuTtOYpLVNRI8vPYnfm87duVOwcTa99t5OacDHcyj5a1d8buDU4+vZlm9Gr45vBzDchoXlQR0Y6BqJvONUMTyj4Ef5kWtpbs8Y+QVIpQ8MyK2QxypeCIneFEML+gWnTV4ZWZKz3CXp8sLdxks= X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(2616005)(1076003)(426003)(336012)(186003)(26005)(107886003)(36756003)(8936002)(70586007)(4326008)(54906003)(6636002)(316002)(8676002)(70206006)(110136005)(7696005)(2906002)(508600001)(6666004)(82310400004)(40460700003)(5660300002)(356005)(83380400001)(81166007)(36860700001)(47076005)(86362001)(36900700001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2022 06:51:20.8267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6150b75-a42b-49f6-39ac-08d9ec61bef5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4409 Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Mohan Kumar X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Add hda clocks, memory ,power and reset binding entries for Tegra234. Signed-off-by: Mohan Kumar --- include/dt-bindings/clock/tegra234-clock.h | 4 ++++ include/dt-bindings/memory/tegra234-mc.h | 6 ++++++ include/dt-bindings/power/tegra234-powergate.h | 9 +++++++++ include/dt-bindings/reset/tegra234-reset.h | 2 ++ 4 files changed, 21 insertions(+) create mode 100644 include/dt-bindings/power/tegra234-powergate.h diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e1b6ef..c014269b7245 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -30,5 +30,9 @@ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ +#define TEGRA234_CLK_AZA_2XBIT 457U +/** @brief aza_2xbitclk / 2 (aza_bitclk) */ +#define TEGRA234_CLK_AZA_BIT 458U #endif diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 2662f70c15c6..f538fc442cee 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -7,6 +7,8 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f +/* NISO0 SMMU STREAM IDs */ +#define TEGRA234_SID_NISO0_HDA 0x03 /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 @@ -16,6 +18,10 @@ * memory client IDs */ +/* High-definition audio (HDA) read clients */ +#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +/* High-definition audio (HDA) write clients */ +#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h new file mode 100644 index 000000000000..3c5575a51296 --- /dev/null +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T234_POWERGATE_T234_H_ +#define __ABI_MACH_T234_POWERGATE_T234_H_ + +#define TEGRA234_POWER_DOMAIN_DISP 3U + +#endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bced642..2ab61c69a3d9 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -10,6 +10,8 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ +#define TEGRA234_RESET_HDA 20U +#define TEGRA234_RESET_HDACODEC 21U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U -- 2.17.1